JPH0832055A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of semiconductor device capable of realizing the miniaturization of a MOS transistor in a simple step. CONSTITUTION:A silicon oxide film 2 (gate oxide film 12) is formed on the surface of a p-type semiconductor substrate 1 (a). A gate electrode 3 (13) in a specific shape is formed on the silicon oxide film 2 (b). The silicon oxide film 2 is isotropically etched away to remove the silicon oxide film 2 in the region wherein the gate electrode 3 is not formed for side etching the silicon oxide film 2 beneath the ends of the gate electrode 3 (c). The p-type semiconductor substrate 1 is thermal oxidized to form silicon oxide films 14, 14 on the surface of the gate electrode 3 and the p-type semiconductor substrate 1 (d). Finally, n-type impurities are implanted in the surface of the p-type semiconductor substrate using the gate electrode 13 as a mask so as to form an n-source region 5 and an n-drain region 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a miniaturized MOS transistor.

[0002]

2. Description of the Related Art The degree of integration of semiconductor devices has improved year by year, and the performance / cost ratio thereof has improved. This has been achieved by improving the structure and circuit configuration of the element and miniaturizing the element and wiring. Among such integrated circuits, one of the integrated circuits for which the microfabrication technology is most advanced is the MOS integrated circuit. Since the MOS integrated circuit has a simple manufacturing process and does not require isolation between elements, the degree of integration can be increased.

FIG. 4 shows a sectional structure of a main part of a general MOS transistor. In FIG. 1A, the source region 102 and the drain region 103 are formed on the surface portion of the semiconductor substrate 101. Then, an oxide film 104 is formed on the surface of the semiconductor substrate 101 in which those regions are formed, and the source region 10 is formed on the surface of the oxide film 104.
The gate electrode 105 is provided above the region between the drain region 103 and the drain region 103.

In the configuration shown in FIG. 1B, the source region 10
2 and the drain region 103, a gate oxide film 111 is formed on the surface of the semiconductor substrate 101. The gate electrode 112 is provided on the gate oxide film 111. Further, an oxide film 113 is formed so as to cover the upper part and the side part of the gate electrode 112.

In order to increase the degree of integration of the MOS integrated circuit, it is effective to make each MOS transistor element as shown in FIG. 4 small. Then, as one of the methods for miniaturizing each element, the channel length L of each MOS transistor is reduced.

However, when the channel length L of the MOS transistor is reduced, the short channel effect occurs. Hereinafter, the short channel effect will be described with reference to FIG. As a general usage pattern of the nMOS transistor shown in FIG. 5, the source is grounded and a positive voltage is applied to the drain. When a current is passed between the source and drain, the threshold voltage V _{th of the} MOS transistor is
A gate voltage V _G higher than the above is applied to the gate electrode 125 and p between the source region 122 and the drain region 123 is applied.
The conductivity type near the surface of the region (p-type substrate 121) is inverted to the n-type semiconductor region to form a channel.

At this time, a reverse bias state is established between the drain region 123 and the p-type substrate 121, and the drain region 1
The depletion layer extending from 23 largely spreads in the p-type substrate 121. Then, due to the influence of the depletion layer, the threshold voltage V _th of the MOS transistor is lowered. Further, when the short channel effect becomes remarkable, the depletion layer extending from the drain region 123 reaches the source region 122, and "punch through" in which the drain current cannot be controlled by the gate voltage occurs.

Further, the channel length L of the MOS transistor
Becomes shorter, the electric field in the channel direction (direction connecting the source region 122 and the drain region 123) becomes stronger, and the electrons that have obtained high energy in the high electric field are drain regions 12.
Avalanche multiplication is performed at the end of 3. Electrons (hot electrons) generated by avalanche multiplication are drain region 1
23, and is further implanted into the oxide film 124 near the end of the drain region 123, as shown in FIG. Thus, when electrons (charges) enter the oxide film 124, MO
The threshold voltage V _th of the S transistor fluctuates, and the operation of the MOS transistor becomes unstable.

The fluctuation of the threshold voltage V _th is
The oxide film 124 becomes thicker as it becomes thinner. In other words, the thicker the oxide film 124, the smaller the fluctuation of the threshold voltage V _th . However, the oxide film 12
Reference numeral 4 denotes a gate insulating film. As the oxide film 124 is made thicker, it becomes difficult to invert the conductivity type of the channel region, that is, it is difficult to control ON / OFF of the MOS transistor. Therefore, the oxide film 124 is made thicker than a predetermined film thickness. It is not possible. Therefore, as a method for solving the above problem, for example, Japanese Patent Laid-Open No. 60-20580 proposes a structure as shown in FIG.

In the structure shown in FIG. 6, the first oxide film 131
A first gate electrode 133 is formed on top of the first
The second gate electrode 13 is connected to the upper surface of the gate electrode 133.
4 are formed. The end portion of the second gate electrode 134 extends to the outside of the first gate electrode 133, and in the region below the end portion of the second gate electrode 134, the first gate electrode 133 is not formed. , A second oxide film 132 is formed. Therefore, since the first oxide film 131 and the second oxide film 132 are formed in the vicinity of the end of the drain region 123 (similar to the source region 122), the oxide film is thick,
The fluctuation of the threshold voltage V _th of the MOS transistor due to the injected hot electrons becomes small.

Further, when the gate electrode is formed into the shape shown in FIG. 6, when the source region 122 and the drain region 123 are formed and the ion implantation is performed using the second gate electrode 134 as a mask (self-alignment), the following is performed. There are advantages. That is, the impurities implanted in the p-type substrate 121 are also diffused laterally in the p-type substrate 121 during the heat treatment. This lateral diffusion distance is p
It can be calculated by the impurity concentration of the mold substrate 121, the amount of ion implantation, the heat treatment condition, and the like. Then, if this distance is adjusted to the length of the second gate electrode 134 protruding from the first gate electrode 133, the “drain” of the drain region 123 (or the source region 122) to the lower portion of the first gate electrode 133 is achieved. And the short channel effect is reduced when elements are formed with the same size.

[0012]

However, when the gate electrode having the structure shown in FIG. 6 is formed, the manufacturing process thereof is complicated. An example of a method of manufacturing the gate electrode shown in FIG. 6 will be shown below. (1) A first oxide film 131 is formed on the surface of the p-type substrate 121. (2) Polysilicon or the like is uniformly formed on the first oxide film 131, and the polysilicon is etched to form the first gate electrode 133. (3) The second oxide film 132 is formed. (4) The second gate electrode 134 is formed. (5) Source region 12 is formed by ion implantation and heat treatment.
2 and the drain region 123 are formed.

Although the above steps are an example, in the conventional manufacturing method, when the gate electrode having the shape shown in FIG. 6 is formed, the first gate electrode 133 is formed and the second gate electrode 13 is formed.
4 was formed in a separate process. Therefore, the number of steps is increased, the manufacturing time is long, and the manufacturing cost is high.

The present invention solves the above problems,
It is an object of the present invention to provide a method for manufacturing a semiconductor device which realizes miniaturization of MOS transistors by a simple process.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of providing polysilicon having a predetermined shape on an oxide film on a surface of a semiconductor substrate, and isotropic with respect to the oxide film. It includes a step of etching, a step of thermally oxidizing the semiconductor substrate, and a step of implanting ions into the semiconductor substrate.

The method of manufacturing a semiconductor device according to a second aspect is based on the first aspect, and side-etches a predetermined amount of the oxide film formed under the end portion of the polysilicon in the etching step. To do.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of providing a gate electrode having a predetermined shape on an oxide film on a surface of a semiconductor substrate and isotropic etching of the oxide film are performed on the gate electrode. A step of removing a predetermined amount of the oxide film formed below the end of the semiconductor substrate, a step of thermally oxidizing the semiconductor substrate, an ion implantation is performed on the semiconductor substrate using the gate electrode as a mask, and a source region and And a step of forming a drain region.

[0018]

When the isotropic etching is performed on the oxide film on the surface of the semiconductor substrate after the polysilicon (gate electrode) having a predetermined shape is provided on the oxide film, a region where the polysilicon is not formed is formed. The oxide film is removed, and the oxide film formed under the end portion of the polysilicon is side-etched.

When the semiconductor substrate is thermally oxidized in this state, an oxide film grows on the surfaces of the polysilicon and the semiconductor substrate, and an oxide film is formed in the region below the end of the polysilicon. Further, in this thermal oxidation, an oxide film is formed by such surface growth, and at the same time, an oxide film that erodes inward of the polysilicon is formed. Here, the upper and side portions of the polysilicon are uniformly eroded (formed with an oxide film), but the lower portion thereof is eroded only from the portion where the oxide film is removed in the etching step.
For this reason, the polysilicon after thermal oxidation has a shape in which the lower portion of the end portion is shaved. In other words, the oxide film formed under the central portion of the polysilicon is thin, and the oxide film under the end portion of the polysilicon is thick.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a manufacturing process of a semiconductor device according to an embodiment of the present invention. Here, an nMOS transistor will be described as an example.

First, as shown in FIG. 1A, a silicon oxide film 2 is uniformly formed on the surface of a p semiconductor substrate 1. Since this silicon oxide film 2 serves as the gate insulating film of the nMOS transistor, it is formed with a film thickness in consideration of the threshold voltage and the like.

Next, as shown in FIG. 1B, a gate electrode 3 made of polysilicon is formed on the silicon oxide film 2. In this step, first, polysilicon is uniformly deposited on the surface of the silicon oxide film 2. Then, impurities such as phosphorus are diffused all over the surface of the polysilicon to reduce its resistance value. Then, the polysilicon is etched into a predetermined shape to form the gate electrode 3.

Next, as shown in FIG. 1C, the silicon oxide film 2 is etched. In this etching step, isotropic wet etching is performed using, for example, an HF (hydrofluoric acid) etching solution. In this isotropic etching, the silicon oxide film 2 in the region where the gate electrode 3 is not formed is removed, and the silicon oxide film 2 formed below the end portion (peripheral portion) of the gate electrode 3 is removed. Side etched. For this reason, a space "empty" is formed below the end portion of the gate electrode 3. Hereinafter, the silicon oxide film 2 remaining after this etching will be referred to as a gate oxide film 12.

Next, referring to FIG. 2, the oxidation step performed after the above etching step will be described in detail. Figure 2
(a) is an enlarged view of FIG. 1 (c). In FIG. 2A, the depth D of the silicon oxide film 2 removed by side etching is controlled by the etching time or the like.

In this state, the p semiconductor substrate 1 is thermally oxidized.
In this thermal oxidation, as shown in FIG. 2 (b), a silicon oxide film 4 (a shaded area in the upper right of FIG. 2 (b)) is formed on the surface of the p semiconductor substrate 1. Further, the silicon oxide film 4 is also formed on the surface (the region where the silicon oxide film 2 is removed on the upper surface, the side surface, and the lower surface) of the gate electrode 3. Here, since the gate electrode 3 is polysilicon containing a large amount of impurities and is acceleratedly oxidized during thermal oxidation, a silicon oxide film 4 thicker than the surface of the p semiconductor substrate 1 grows on the surface of the gate electrode 3. To do.

On the other hand, in this thermal oxidation step, the gate electrode 3
(The same applies to the p-semiconductor substrate 1, but the description thereof is omitted.) The silicon oxide film 4a (shown by the diagonal line to the lower right of FIG. 2B) is formed so as to erode the polysilicon toward the inside. Area) is formed. Here, the silicon oxide film 4a is uniformly formed on the upper and side portions of the gate electrode 3, but on the lower portion thereof, the silicon oxide film 4a is formed only from the portion where the silicon oxide film 2 is removed in the etching process. To be done. In other words, in the lower portion of the gate electrode 3, an oxidation reaction occurs only at the end portion thereof, and the polysilicon is “eroded” to become a silicon oxide film. That is, the gate electrode 3 after thermal oxidation has a shape in which the lower portion of the end portion is cut by the oxide film (hereinafter, the gate electrode having this shape is referred to as the gate electrode 13). As a result, a thin insulating film composed of the gate oxide film 12 is formed below the central portion of the gate electrode 13, and a thick insulating film composed of the silicon oxide film 4 and the silicon oxide film 4a is formed below the end portion of the gate electrode 13. (Hereinafter, the insulating film composed of the silicon oxide films 4 and 4a is referred to as the silicon oxide film 14).
In particular, the insulating film formed below the end portion of the gate electrode 13 is referred to as a silicon oxide film 14a). The configuration is shown in Fig. 2 (c).

Next, returning to FIG. 1, the steps after the thermal oxidation will be described. FIG. 1 (d) shows the same state as FIG. 2 (c). Following the state of FIG. 1D, ion implantation is performed to form the n source region 5 and the n drain region 6. Here, as n-type impurities, P, As,
Alternatively, Sb or the like is injected. In this ion implantation, the gate electrode 13 formed in the above process is used as a mask. That is, the n source region 5 and the n drain region 6 are formed by a self-alignment process.

After that, heat treatment is performed to activate the implanted impurities to form an n source region 5 and an n drain region 6 as shown in FIG. 1 (e). In this heat treatment, the impurities are diffused in all directions. Therefore, the implanted impurities diffuse to the lower side of the gate electrode 13, but do not reach the lower portion of the gate oxide film 12. Actually, the heat treatment conditions are set in advance at the designing stage, and it is known how much the impurities are diffused. Therefore, the silicon oxide film 2 is formed deeper than the diffusion range of the impurities to the lower side of the gate electrode 13. Etching.

The nMOS transistor is thus formed. In the above process, the gate electrode 3 is formed on the upper surface of the silicon oxide film 2 and, in that state, the silicon oxide film 2 is isotropically etched. By performing thermal oxidation, the gate electrode 13 having the shape as shown in FIG. 2 (c) is formed. This manufacturing method has a smaller number of steps, a shorter time, and lower cost than the conventional method.

Since the nMOS transistor formed by the above steps is intended for fine processing, the distance (channel length) between the n source region 5 and the n drain region 6 is formed as short as possible. Therefore, n
A high electric field state is established between the source region 5 and the n-drain region 6, and electrons having high energy are formed from the end of the n-drain region 6 to the upper side of the end of the n-drain region 6. It may be injected into the film 14a. However, since the silicon oxide film 14a is formed thicker than the gate oxide film 12, even if electrons (charges) enter there, the fluctuation of the threshold voltage _Vth of the nMOS transistor is small and the nMOS transistor has a small fluctuation. The characteristics are stable.

FIG. 3 shows the relationship between the channel length of the MOS transistor and the threshold voltage V _th . In the figure, the example shown as the prior art is a MOS transistor whose gate electrode has the configuration of FIG. In the conventional MOS transistor, as shown by the broken line in the figure, when the channel length becomes shorter, the threshold voltage V _th becomes smaller due to the short channel effect, and the value of the threshold voltage V _th fluctuates. The characteristics were unstable. On the other hand, in the MOS transistor of this embodiment,
When the channel length is shortened, the ratio of the area occupied by the silicon oxide film 14a to the insulating film under the gate electrode 13 increases, and the action of increasing the threshold voltage V _th works to prevent the short channel effect. Also, a thick insulating film Suresshuhorudo voltage V _th with respect to (the silicon oxide film 14a) is a thin insulating film (gate oxide film 12) higher than the Suresshuhorudo voltage V _th for, when the channel length is short silicon oxide film 14a The threshold voltage V _th of the MOS transistor becomes dominant, and the threshold voltage V _th of the MOS transistor has a substantially constant characteristic with respect to the channel length as shown by the solid line in FIG.

The present invention can also be applied to pMOS transistors.

[0033]

According to the manufacturing method of the present invention, the number of manufacturing steps for forming the oxide film below the end portion of the gate electrode of the MOS transistor to be thicker than the gate oxide film in other regions is reduced. M that can be miniaturized and have stable characteristics
The manufacturing time and manufacturing cost of the OS transistor are improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a thermal oxidation process in the manufacturing process of the above embodiment.

FIG. 3 is a diagram showing a relationship between a channel length of a MOS transistor and a threshold voltage.

FIG. 4 is a cross-sectional configuration diagram of a main part of a general MOS transistor.

FIG. 5 is a diagram illustrating a short channel effect in a MOS transistor.

FIG. 6 is a cross-sectional configuration diagram of a main part of a MOS transistor in which the shape of a gate electrode is devised.

[Explanation of symbols]

 1 p semiconductor substrate 2 silicon oxide film 3 gate electrode 4 silicon oxide film 4a silicon oxide film 5 n source region 6 n drain region 12 gate oxide film 13 gate electrode 14 silicon oxide film 14a silicon oxide film

Claims (3)

[Claims] 1. A step of providing polysilicon having a predetermined shape on an oxide film on a surface of a semiconductor substrate, a step of performing isotropic etching on the oxide film, a step of thermally oxidizing the semiconductor substrate, A method of manufacturing a semiconductor device, comprising the steps of: ion-implanting a semiconductor substrate. 2. The etching step comprises side etching a predetermined amount of the oxide film formed under the end portion of the polysilicon.
A method of manufacturing a semiconductor device according to item 1. 3. A step of providing a gate electrode of a predetermined shape on an oxide film on a surface of a semiconductor substrate, and isotropic etching of the oxide film to form a gate electrode below an end portion of the gate electrode. A step of removing a predetermined amount of the oxide film, a step of thermally oxidizing the semiconductor substrate, a step of ion-implanting the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region. A method of manufacturing a semiconductor device, comprising: