JPH02237121A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02237121A
JPH02237121A JP1056052A JP5605289A JPH02237121A JP H02237121 A JPH02237121 A JP H02237121A JP 1056052 A JP1056052 A JP 1056052A JP 5605289 A JP5605289 A JP 5605289A JP H02237121 A JPH02237121 A JP H02237121A
Authority
JP
Japan
Prior art keywords
silicon
semiconductor substrate
bonded
substrate
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1056052A
Other languages
Japanese (ja)
Inventor
Takaharu Nawata
名和田 隆治
Hitoshi Hasegawa
長谷川 斉
Hiroshi Kaneda
寛 金田
Ude Suzuki
腕 鈴木
Yoshimi Shirakawa
良美 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1056052A priority Critical patent/JPH02237121A/en
Publication of JPH02237121A publication Critical patent/JPH02237121A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures

Landscapes

  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To getter a crystal defect which is produced in a process to form a device on a bonded substrate by a method wherein parts connected directly by silicon are formed between silicon-on-insulator(SOI) bonded wafers. CONSTITUTION:An SiO2 film and an Si3N4 film as oxidation-resistant films are deposited one after another on a first silicon wafer 11; SiO2 layers 12 to be used as insulating layers are formed of them in a separated manner. Then, the surface is flattened; a second silicon wafer 13 as a CZ wafer of a high oxygen concentration is bonded; this assembly is heated; islands of the SiO2 layers 12 are formed between the silicon wafers 11, 13. Accordingly, the first and second semiconductor substrates are connected directly between the islands of the layers 12. Thereby, a detect of the second semiconductor substrate is gettered to the inside of a defect layer 14; the second semiconductor substrate becomes a defect free zone 15.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法、特に接着技術によるシリコン・
オン・インシュレータ(SO I )基板の製造方法に
関し、 従来の接着技術によるSOI基板にデバイスを形成する
プロセスにおいて発生する結晶欠陥をゲッタリングする
ことのできるSOI構造を形成する方法を提供すること
を目的とし、 第1の半導体基板に選択的に互いに分離した絶縁層を形
成する工程、第1の半導体基板の表面を平坦化し該基板
に埋め込まれた形状の該絶縁層の島を形成する工程、お
よび第1の半導体基板の表面に該絶縁層を介して第2の
半導体基板を接着し、絶縁層の島の上方の第2の半導体
基板に半導体デバイスを形成する工程を含むことを特徴
とす条半導体装置の製造方法を含み構成する。
[Detailed Description of the Invention] [Summary] A method for manufacturing semiconductor devices, especially silicon
The present invention relates to a method for manufacturing an on-insulator (SOI) substrate, and an object of the present invention is to provide a method for forming an SOI structure that can getter crystal defects that occur during the process of forming devices on an SOI substrate using conventional bonding techniques. forming insulating layers selectively separated from each other on a first semiconductor substrate; planarizing the surface of the first semiconductor substrate to form islands of the insulating layer embedded in the substrate; A method characterized by including the step of bonding a second semiconductor substrate to the surface of the first semiconductor substrate via the insulating layer, and forming a semiconductor device on the second semiconductor substrate above the island of the insulating layer. The present invention includes a method for manufacturing a semiconductor device.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法、特に接着技術によるシ
リコン・オン・インシュレータ(Sol)基板の製造方
法に関する. 〔従来の技術〕 接着技術によるSOT基板は、良好な結晶方位と界面特
性から、ラッチアップがなく、耐放射線能に優れ、デバ
イス作成層の薄膜化により高速LSI、VLSIに適し
たものとして着目されている。現在のLSIは高集積化
とともに高速性が強く要求されているもので、この要請
を満たすものとしてSolデバイスが提案され、これに
使用するSO1基板(ウエハ)を実現する有効な手段と
して接着技術によるSO1基板が研究されている。
The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a silicon-on-insulator (Sol) substrate using adhesive technology. [Conventional technology] SOT substrates made using adhesive technology are attracting attention as they are suitable for high-speed LSI and VLSI due to their good crystal orientation and interface characteristics, do not cause latch-up, have excellent radiation resistance, and have thin device fabrication layers. ing. Current LSIs are strongly required to have high integration and high speed, and the Sol device has been proposed as a device that satisfies this demand, and adhesive technology is an effective means of realizing the SO1 substrate (wafer) used for this device. SO1 substrates are being researched.

また上記した技術によると、デバイス領域を形成する半
導体層において薄膜化が行えるので、リーク電流の低減
化が実現され、高温動作時での性能向上が期待されてい
る。さらには、従来のLSIプロセス、デバイス技術が
ほとんどすべてそのま\使用することが可能であるとい
う利点もある。
Further, according to the above-mentioned technology, since the semiconductor layer forming the device region can be made thinner, leakage current can be reduced, and performance improvement during high-temperature operation is expected. Another advantage is that almost all conventional LSI processes and device technologies can be used as is.

なお、従来の接着によるSOI基板は、表面を酸化した
ウエハを単に接着することによって作られてきた. 第2図は従来の接着によるSOI基板の形成方法?説明
する断面図で、先ず、同図(a)に示されるように、第
1のシリコンウエハ31に、表面にSin2膜33が形
成された第2のシリコンウエハ32を、SiO■膜33
が第1のシリコンウエハ3lに接する状態で接着する。
Note that conventional bonded SOI substrates have been made by simply bonding wafers whose surfaces have been oxidized. Figure 2 shows the method of forming an SOI substrate using conventional adhesion. In the cross-sectional view to be explained, first, as shown in FIG.
is bonded in a state where it is in contact with the first silicon wafer 3l.

次に、同図(b)に示される如く第2のシリコンウエハ
32をSint膜33の形成されていない背面から研磨
して、例えば10μm程度の厚さのデバイス形成領域と
なるシリコン層34を残す。なお同図中、36は絶縁膜
である。
Next, as shown in FIG. 3B, the second silicon wafer 32 is polished from the back side where the Sint film 33 is not formed, leaving a silicon layer 34 that will become a device formation region with a thickness of, for example, about 10 μm. . Note that in the figure, 36 is an insulating film.

続いて、同図(C)に示される如くシリコン層34に所
望のデバイス35(例えばMOSトランジスタ)を形成
してきた。
Subsequently, a desired device 35 (for example, a MOS transistor) is formed on the silicon layer 34 as shown in FIG. 3C.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

現在、大規模なrcを製造するに際しては、材料のもつ
内因的な不純物、欠陥、さらにプロセス処理中に誘起、
導入される欠陥を効率良く除去しもしくは消去する必要
がある.これには、イントリンシックゲッタリング(I
G)と呼称される欠陥のゲッタリングが有効であり、ゲ
ッタリングは例えば熱処理によってなされている。
Currently, when manufacturing large-scale RC, it is necessary to avoid the inherent impurities and defects of the material, as well as the defects induced during the process.
It is necessary to efficiently remove or erase the introduced defects. This involves intrinsic gettering (I
Gettering of defects called G) is effective, and gettering is performed by heat treatment, for example.

従来技術によるSO1基板はデバイス領域の製作前に行
うため、結晶欠陥低減化すなわちゲッタリングはデバイ
ス製作前に行われる。そこで、デバイス製作途中での結
晶欠陥の発生があっても、第2図に示されるSin.膜
33がいわばバッファーとなってそれに対して有効なゲ
ッタリングが行えないために、か一る結晶欠陥がデバイ
ス特性の劣化をもたらす問題がある。
Since the SO1 substrate according to the prior art is performed before the device region is manufactured, crystal defect reduction, that is, gettering is performed before the device manufacturing. Therefore, even if crystal defects occur during device fabrication, the Sin. Since the film 33 acts as a so-called buffer and effective gettering cannot be performed on it, there is a problem in that some crystal defects cause deterioration of device characteristics.

再び第2図(C)を参照すると、デバイス形成領域であ
るシリコン層34は、下地のSin.膜33によって下
のシリコンウエハ31から完全に分離されている。
Referring again to FIG. 2(C), the silicon layer 34, which is the device formation region, is formed by the underlying Sin. It is completely separated from the underlying silicon wafer 31 by a membrane 33.

このため、デバイス形成時での結晶欠陥発生に対しては
、デバイス形成プロセス条件に制限された範囲でしかゲ
ッタリング処理が行えない。例えば、イントリンシック
ゲッタリング(IG)では、高温、長時間での熱処理が
必要で、デバイス形成プロセスとの釣合い(マッチング
)はとれない。この意味で、デバイス形成による結晶欠
陥発生に対しては、従来のSol構造では欠陥低減化が
困難であり、デバイス特性の劣化を招いている。
For this reason, for the occurrence of crystal defects during device formation, gettering processing can only be performed within a range limited by the device formation process conditions. For example, intrinsic gettering (IG) requires heat treatment at high temperatures and for a long period of time, which cannot be matched with the device formation process. In this sense, it is difficult to reduce crystal defects caused by device formation in the conventional Sol structure, leading to deterioration of device characteristics.

そこで本発明は、従来の接着技術によるSOIi板にデ
バイスを形成するプロセスにおいて発生する結晶欠陥を
ゲッタリングすることのできるSOI構造を形成する方
法を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for forming an SOI structure that can getter crystal defects that occur in the process of forming devices on an SOIi plate using conventional bonding techniques.

〔課題を解決するための手段] 上記課題は、第1の半導体基板に選択的に互いに分離し
た絶縁層を形成する工程、第1の半導体基板の表面を平
坦化し該基板に埋め込まれた形状の該絶縁層の島を形成
する工程、および第1の半導体基板の表面に該絶縁層を
介して第2の半導体基板を接着し、絶縁層の島の上方の
第2の半導体基板に半導体デバイスを形成する工程を含
むことを特徴とする半導体装置の製造方法によって解決
される。
[Means for Solving the Problems] The above problems include a step of forming selectively separated insulating layers on a first semiconductor substrate, a step of flattening the surface of the first semiconductor substrate, and forming a shape embedded in the substrate. forming an island of the insulating layer, bonding a second semiconductor substrate to the surface of the first semiconductor substrate via the insulating layer, and attaching a semiconductor device to the second semiconductor substrate above the island of the insulating layer; The problem is solved by a method for manufacturing a semiconductor device characterized by including a step of forming a semiconductor device.

〔作用] ICを製造する半導体基板の表面に内部の欠陥層?ゲッ
タリング効果を及ぼすには、部分的に上下の接着ウエハ
の間がシリコンでつながっているようにする必要がある
。そこで本発明では、選択酸化法(LOCOS法)の技
術を用いて埋め込みSiO■層を部分的に作り、これを
平坦化し、しかる後に上下のウエハを接着し、イントリ
ンシックゲッタリングを可能にする。
[Function] Is there an internal defect layer on the surface of the semiconductor substrate used to manufacture ICs? In order to produce a gettering effect, it is necessary to partially connect the upper and lower bonded wafers with silicon. Therefore, in the present invention, a buried SiO2 layer is partially formed using a selective oxidation method (LOCOS method), this is planarized, and the upper and lower wafers are then bonded to enable intrinsic gettering.

すなわち本発明では、SOI接着ウエハの間にシリコン
で直接につながっている部分を作ることにより、基板中
に形成されたシリコンの析出層がプロセス中ゲッタリン
グ効果を発揮するのである。
That is, in the present invention, by creating a directly connected portion with silicon between the SOI bonded wafers, the silicon precipitate layer formed in the substrate exhibits a gettering effect during the process.

〔実施例〕〔Example〕

以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

第1図は本発明の実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

第1図(a)参照: 例えば厚さ600〜700μmの第1の半導体基板(シ
リコンウエハ)1工上に耐酸化性膜として図示しない5
00〜1000人の膜厚のSin.膜と、1 , 00
0〜? , 500人の膜厚のSi3N.膜とを順に堆
積し、これらの膜をバターニングした後に例えばウエッ
ト酸化法で絶縁層となるSiO■N12を形成する。S
tOzN■2相互間の距離diは10μmに、SiOJ
I2のそれぞれの拡がりd2は20μmになるように前
記した耐酸化性膜をバターニングする。
Refer to FIG. 1(a): For example, an oxidation-resistant film (not shown) is formed on a first semiconductor substrate (silicon wafer) having a thickness of 600 to 700 μm.
00 to 1000 film thickness Sin. membrane and 1,00
0~? , 500-thick Si3N. After sequentially depositing these films and patterning these films, SiO2N12, which will become an insulating layer, is formed by, for example, a wet oxidation method. S
tOzN■ The distance di between the two is 10 μm, and the SiOJ
The above-mentioned oxidation-resistant film is buttered so that each extension d2 of I2 is 20 μm.

第2図Φ)参照: SiOzとほり同じ選択比をもつレジスト (図示せず
)を全面に塗布し、異方性エッチングを行ってレジスト
とSingをエッチングして表面を平坦化する. 第1図(C)参照: 高酸素濃度のCZウエハである第2の半導体基板(シリ
コンウエハ)13を接着し、加熱し、SiO■層12の
島(アイランド)をシリコン11と13との間に形成す
る.そのためには、第2のシリコンウエハとしては例え
ば200μmのウエハを用意し、それを30〜50μm
の厚さの第2のシリコン基板13が残るまで研磨する。
See Figure 2 Φ): Apply a resist (not shown) with the same selectivity as SiOz over the entire surface, and perform anisotropic etching to etch the resist and Sing to flatten the surface. Refer to FIG. 1(C): A second semiconductor substrate (silicon wafer) 13, which is a CZ wafer with a high oxygen concentration, is bonded and heated to form an island of SiO layer 12 between silicon 11 and silicon 13. Form into. To do this, for example, a 200 μm wafer is prepared as the second silicon wafer, and then a 30 to 50 μm wafer is prepared.
Polishing is performed until a second silicon substrate 13 with a thickness of .

第1図(d)参照: ?2のシリコン基板13のSiO■層の上部にSOIデ
バイスを形成するのであるが、第1図(C)の状態で熱
処理を行うとIGが行われ、第1のシリコン基板11に
はTG欠陥層14が形成され、第2のシリコン基板は欠
陥層のないデヌーデッド・ゾーン15となる。
See Figure 1(d): ? An SOI device is formed on the SiO2 layer of the silicon substrate 13 of No. 2. When heat treatment is performed in the state shown in FIG. 14 is formed, and the second silicon substrate becomes a denuded zone 15 free of defect layers.

すなわち、従来法では第1と第2のシリコンウエハの間
にSin2膜が存在し、第2のシリコンウエハにデバイ
スを形成する際に発生する欠陥層は第2のシリコンウエ
ハに残存したのであるが、第1図(d)に示す構造にお
いては、SiO■J’fil2の島の間では第1と第2
のシリコンウエハが直接つながっているので、第2のシ
リコンウエハの欠陥はI6欠陥層14内にゲッタリング
されて第2シリコンウエハは欠陥のないデヌーデッド・
ゾーン15となり、そこに形成されるデバイスの特性が
改良されるのである。
In other words, in the conventional method, a Sin2 film existed between the first and second silicon wafers, and the defect layer that occurred when forming devices on the second silicon wafer remained on the second silicon wafer. , In the structure shown in FIG. 1(d), between the islands of SiOJ'fil2, the first and second
Since the two silicon wafers are directly connected to each other, defects in the second silicon wafer are gettered into the I6 defect layer 14, and the second silicon wafer becomes a defect-free denuded silicon wafer.
zone 15, and the characteristics of devices formed there are improved.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、従来のSol接着ウエハ
においてrGの効果が発生し、IC形成プロセス中に作
られる欠陥、不純物(メタルなど)の除去が可能となる
のである。
As described above, according to the present invention, the rG effect occurs in the conventional Sol bonded wafer, and it becomes possible to remove defects and impurities (metal, etc.) created during the IC forming process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明実施例断面図、第2図(
a.)〜(C)は従来例断面図である。 図中、 11は第1のシリコン基板、 12はSiOz層、 13は第2のシリコン基板、 14はic欠陥層、 15はデヌーデッド・ゾーン を示す。
Figures 1 (a) to (d) are cross-sectional views of embodiments of the present invention, and Figure 2 (
a. ) to (C) are sectional views of conventional examples. In the figure, 11 is a first silicon substrate, 12 is a SiOz layer, 13 is a second silicon substrate, 14 is an IC defect layer, and 15 is a denuded zone.

Claims (1)

【特許請求の範囲】  第1の半導体基板(11)に選択的に互いに分離した
絶縁層(12)を形成する工程、 第1の半導体基板(11)の表面を平坦化し該基板(1
1)に埋め込まれた形状の該絶縁層(12)の島を形成
する工程、および 第1の半導体基板(11)の表面に該絶縁層(12)を
介して第2の半導体基板(13)を接着し、絶縁層(1
2)の島の上方の第2の半導体基板に半導体デバイスを
形成する工程を含むことを特徴とする半導体装置の製造
方法。
[Claims] A step of forming insulating layers (12) selectively separated from each other on a first semiconductor substrate (11), planarizing the surface of the first semiconductor substrate (11) and
1) forming an island of the insulating layer (12) embedded in the second semiconductor substrate (13) on the surface of the first semiconductor substrate (11) via the insulating layer (12); Glue the insulating layer (1
2) A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device on a second semiconductor substrate above the island.
JP1056052A 1989-03-10 1989-03-10 Manufacture of semiconductor device Pending JPH02237121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1056052A JPH02237121A (en) 1989-03-10 1989-03-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1056052A JPH02237121A (en) 1989-03-10 1989-03-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02237121A true JPH02237121A (en) 1990-09-19

Family

ID=13016312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1056052A Pending JPH02237121A (en) 1989-03-10 1989-03-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02237121A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443661A (en) * 1993-07-27 1995-08-22 Nec Corporation SOI (silicon on insulator) substrate with enhanced gettering effects
US5773152A (en) * 1994-10-13 1998-06-30 Nec Corporation SOI substrate having a high heavy metal gettering effect for semiconductor device
EP0710980A3 (en) * 1994-11-07 1998-09-30 Nec Corporation Soi substrate
WO2000010201A1 (en) * 1998-08-10 2000-02-24 Memc Electronic Materials, Inc. Process for metal gettering in soi substrates
WO2000010195A3 (en) * 1998-08-10 2000-05-18 Memc Electronic Materials Preparation of metal-precipitates permeable insulator for soi substrate
US6724408B1 (en) 1999-08-10 2004-04-20 International Business Machines Corporation Command line interface for a data processing system
JP2008091935A (en) * 2007-11-02 2008-04-17 Seiko Instruments Inc Integrated circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5443661A (en) * 1993-07-27 1995-08-22 Nec Corporation SOI (silicon on insulator) substrate with enhanced gettering effects
US5773152A (en) * 1994-10-13 1998-06-30 Nec Corporation SOI substrate having a high heavy metal gettering effect for semiconductor device
EP0710980A3 (en) * 1994-11-07 1998-09-30 Nec Corporation Soi substrate
WO2000010201A1 (en) * 1998-08-10 2000-02-24 Memc Electronic Materials, Inc. Process for metal gettering in soi substrates
WO2000010195A3 (en) * 1998-08-10 2000-05-18 Memc Electronic Materials Preparation of metal-precipitates permeable insulator for soi substrate
US6724408B1 (en) 1999-08-10 2004-04-20 International Business Machines Corporation Command line interface for a data processing system
JP2008091935A (en) * 2007-11-02 2008-04-17 Seiko Instruments Inc Integrated circuit

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