JPH0834366B2 - Impedance converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to an impedance converter for connecting microwave lines having different characteristic impedances. Hereinafter, the microwave line is a line for transmitting a signal having a frequency of approximately 1 GHz or higher, and refers to a coplanar line such as a coplanar line or a slot line, and a microstrip line.

[Prior Art] FIG. 6 is a plan view of an impedance conversion circuit for connecting between microstrip lines having different characteristic impedances. In the sixth figure, the output micro ground conductor on the lower surface on the upper surface of the dielectric substrate 10 (not shown) is formed, the input microstrip line 11 and the width l ₂ of the width l ₁ (> l ₁₎ A strip line 12 is formed, and a width l ₃ (l ₁ <l ₃ <l ₂ ) and a length of 1/4 wavelength are formed on the substrate 10 between the input microstrip line 11 and the output microstrip line 12. The matching microstrip line 13 has a line 11 and
Formed integrally with 12. Here, the characteristic impedances of the input / output microstrip lines 11 and 12 are respectively
Assuming Z ₀₁ and Z ₀₂ , the matching microstrip line 13
The characteristic impedance Z ₀₃ of By setting the width l ₃ so that the impedances between the input and output microstrip lines 11 and 12 can be matched.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional impedance conversion circuit, since the length of the matching microstrip line 13 needs to be at least 1/4 wavelength, the impedance conversion device should be miniaturized. I couldn't.

Further, since this conventional circuit is a reciprocal circuit, the electrical separation of the input and output cannot be obtained. For example, when there is a reflection from the circuit connected to the output line 12, the reflected wave is directly input to the input line 11. Will appear. There is a problem that an isolator must be further provided between the input and the output in order to remove this reflected wave.

An object of the present invention is to solve the above problems and to provide an impedance converter which can be downsized as compared with a conventional circuit and which has a good electrical isolation between the input and output microwave lines. is there.

[Means for Solving Problems] An impedance converter according to the present invention is an impedance converter for connecting an input microwave line and an output microwave line, wherein a source electrode is connected to the input microwave line. A first grounded first field effect transistor having a predetermined gate width, a gate electrode connected to the drain electrode of the first field effect transistor, and a source electrode connected to the output microwave line. , A drain-grounded second field-effect transistor having a predetermined gate width, and the characteristic impedance of the input microwave line is Z ₀₁
When the mutual conductance of the first field effect transistor is gm ₁ , the characteristic impedance of the output microwave line is Z _02, and the mutual conductance of the second field effect transistor is gm ₂ , then gm ₁ The gate width of the first field effect transistor and the gate width of the second field effect transformer are set so that Z ₀₁ = gm ₂ Z ₀₂ = 1.

[Operation] With the above configuration, the first gate grounding
And the drain-grounded second field-effect transistor are connected in series, where gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1 and the gate width of the first field-effect transistor The gate width of the second field effect transformer is set. At this time, the input end reflection coefficient S ₁₁ in the input microwave line and the output end reflection coefficient S ₂₂ in the output microwave line become zero.

Therefore, the characteristic impedances between the input microwave line and the output microwave line are matched by the two field effect transistor circuits connected in cascade.

[Embodiment] Basic Circuit FIG. 1 is a circuit diagram of a basic circuit of an impedance conversion circuit using a field effect transistor (hereinafter referred to as FET) according to an embodiment of the present invention. In FIG. ₁ , an input microwave line 21 having a characteristic impedance Z ₀₁ is connected to a source of a gate-grounded FET 22 having a mutual conductance gm ₁ , and a drain of the FET 22 is connected via a gain adjusting resistor 23 having a resistance value R. It is connected to ground and to the gate of a drain-grounded FET 24 having a transconductance gm ₂ . Further, the source of the FET 24 is connected to the output microwave line 25 having the characteristic impedance Z ₀₂ .

Here, considering that the FETs 22 and 24 are ideal FETs that can be described only by mutual conductance, the S parameter of the circuit of FIG. 1 is as follows.

S ₁₂ = 0 (2) Furthermore, when the gate widths of the gate-grounded FET 22 and the drain-grounded FET 24 are set so that gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1, the above-mentioned S parameters are as follows.

S ₁₁ = S ₁₂ = S ₂₂ = 0 (5) As described above, by cascade-connecting the gate-grounded FET 22 and the drain-grounded FET 24 in which gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1 is set, the following effects are obtained.

(1) Since the input end reflection coefficient S ₁₁ and the output end reflection coefficient S ₂₂ are zero, impedance matching between the input and output lines can be achieved.

(2) Since the backward transfer coefficient S ₁₂ becomes zero, it is possible to electrically separate the input and output lines.

(3) Since the forward transfer coefficient S ₂₁ can be expressed by the above equation (6), the amplification gain can be adjusted by changing the resistance value R of the resistor 23. The resistor 23 is provided for gain control and widening the band, and the resistance value R of the resistor 23 is set to infinity, that is, even if the resistor 23 is removed, the impedance conversion circuit still has the above (1) and (2). )
Have the effect of.

Furthermore, the space between the input and output microwave lines 21 and 25 is
Unlike the conventional example, it does not require the length of 1/4 wavelength,
In addition, the circuit composed of the resistor 23 can be generally downsized. In particular, if the circuit is monolithic, the impedance conversion circuit can be made much smaller than the conventional example.

First Embodiment FIG. 2 is a plan view of a hybrid integrated circuit for impedance conversion of an input / output microstrip line according to the first embodiment of the present invention, and is the same as FIG. 1 in FIG. Are denoted by the same reference numerals.

The in Figure 2, on the upper surface of the dielectric substrate 10 (not shown) are formed grounding conductor under the surface, the width l ₁ of the microstrip line 11 and the microstrip line 12 is the line 11 of width l ₂ , 12 are formed at a predetermined interval in the longitudinal direction. On the substrate 10 between the respective end portions 11a and 12a of the lines 11 and 12, substantially square conductors 15 and 17 are formed with a predetermined distance therebetween, and a direct current cutting chip capacitor 33 is provided between the conductors 15 and 17. Connected through. On the substrate 10 between the end 11a of the line 11 and the conductor 15, the FET 31 enclosed in the package
Board 1 between the conductor 17 and the end 12a of the line 12
The FET 32 enclosed in the package is placed on the 0.

The conductors 16 and 18 are formed on the substrate 10 on the lower side of the conductor 15 and the FET 32 in the drawing, respectively, and the ground conductor has the protruding portions 14a and 14b that protrude on the lower side of the FET 31 and the conductor 17 in the drawing.
14 is formed on the substrate 10 below the drawings of the FETs 31 and 32 and the conductors 16 and 18. The ground conductor 14 is connected to the ground conductor formed on the lower surface of the substrate 10 via a predetermined connecting wire (not shown). Further, drain bias supply terminals 38 and 39 are connected to the conductors 16 and 18, respectively.

The source terminal of the FET 31 is connected to the end 11a of the line 11, the drain terminal of the FET 31 is connected to the conductor 15, and the FET
The gate terminal of 31 is connected to the protruding portion 14a of the ground conductor 14. Conductor 15 is connected to conductor 16 via a chip resistor 36,
The conductor 16 is connected to the ground conductor 14 via the high frequency bypass chip capacitor 34. Further, the conductor 15 is connected to the conductor 17 via the DC cut chip capacitor 33. Further, the conductor 17 is connected to the protruding portion of the ground conductor 14 via the chip resistor 37.
The conductor 18 is connected to the ground conductor 14b via the high-frequency bypass chip capacitor 35.

The gate terminal of the FET 32 is connected to the conductor 17, and the FET
32 drain terminals are connected to the conductor 18, and the FET3
The second source terminal is connected to the end 12a of the line 12.

With the above configuration, the drain of the FET 31 is grounded in high frequency via the chip resistor 36 and the chip capacitor 34, and the drain of the FET 32 is grounded in high frequency via the chip capacitor 35. The signal input to the input microstrip line 11 is output via the FET 31, the chip capacitor 33, and the FET 32.
Output to 2. Here, the high frequency equivalent circuit of the hybrid integrated circuit of FIG. 2 is as shown in FIG. 1, and the mutual conductance of the FET 31 and FET 32 is gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1.
As described above, the impedance matching between the input / output lines 11 and 12 can be achieved, and the impedance conversion between the input / output lines 11 and 12 having different characteristic impedances can be performed as described above. Also, the input / output lines 11 and 12
Since a FET circuit consisting of two FETs 31 and 32, which allows signals to be transmitted in only one direction, is inserted between them, the input / output lines 11 and 1
An impedance conversion circuit having a good electrical isolation between the two can be obtained.

Further, since the distance between the input / output lines 11 and 12 in this circuit does not require the length of 1/4 wavelength as in the conventional example, it is composed of the FETs 31 and 32, the chip capacitor 33 and the conductors 15 and 17. By miniaturizing the circuit, the impedance conversion circuit can be miniaturized as compared with the conventional example.

In the present embodiment, the FET 31 and the FET 32 are arranged close to each other and are connected in a lumped constant manner, but they can be connected via a microwave line. This also applies to the following examples.

Second Embodiment FIG. 3 (A) is a plan view of a monolithic integrated circuit for impedance conversion between the input / output microstrip lines 11 and 12 according to the second embodiment of the present invention, and FIG. 3 (B).
Is a longitudinal sectional view taken along the line AA ′ of FIG. 3 (A), and FIG. 3 (C).
FIG. 4 is a vertical sectional view taken along the line BB ′ of FIG. 3 (A). In FIGS. 3A, 3B and 3C, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

In FIGS. 3A, 3B and 3C, the ground conductor 60 is formed on the lower surface of the rectangular semi-insulating GaAs semiconductor substrate 40. A metal-semiconductor field effect transistor (hereinafter, referred to as ME
It is called SFE. ) 41 is formed on the entire surface at the position where the impurity layer 41 is formed, and impurity ions are implanted from the upper surface of the semiconductor substrate 40 to form an operating layer 45. The gate electrode 42 of the MESFET 41 is integrally formed with the conductor 61 at a substantially central position of the operation layer 45. Here, the planar shape of the gate electrode 42 is such that two sides of a longitudinal gate width w ₁ and a gate length g ₁ are formed. It has a rectangular shape. Further, the source electrode 43 and the drain electrode 44 are separated from the gate electrode 42 by a predetermined distance with the gate electrode 42 in between, and the conductor 11 and the conductor of the input microstrip line are respectively provided on the operation layer 45. It is integrally formed with 62. Here, each of the source electrode 43 and the drain electrode 44 has a rectangular plan view, and the sides of the electrodes 43 and 44 in the longitudinal direction are parallel to the sides of the gate electrode 42 in the gate width w ₁ direction. .

The MESFET 41 is constituted by the gate electrode 42, the source electrode 43 and the drain electrode 44 which are formed on the operation layer 45 in the semiconductor substrate 40 by the known method as described above.

Further, the MESFET 51 including the gate electrode 52, the source electrode 53, and the drain electrode 54 is formed on the operation layer 55 of the semiconductor substrate 40 at the position on the lower right side of the MESFET 41 in the figure, similarly to the MESFET 41. Here, the planar shape of the gate electrode 52 is the longitudinal gate width.
It has a rectangular shape having two sides of w ₂ and gate length g ₂ , and the source electrode 53 and the drain electrode 54 are integrally formed with the conductor 12 and the conductor 66 of the output microstrip line on the operating layer 55.

Input conductor 11 of the microstrip line is formed the source electrode 43 integrally with the drawing the upper side of the source electrode 43 of MESFET41, the planar shape width l ₁ and the longitudinal side of the direction of the gate width w ₁ of the conductor 11 It has a rectangular shape. Where this conductor 11
_One side of the width l ₁ of the source electrode 43 is connected to the central portion of the side of the source electrode 43 in the gate width w ₁ direction. The ground conductor 61 includes the gate electrode 42 and the drain electrode 44 of the MESFET 41 on the left side and the lower side in the figure, and
The ground electrode 61 is formed integrally with the gate electrode 42 at the edge of the semiconductor substrate 40 below the drain electrode 54 of the MESFET 51.
Is connected to the ground conductor 60 via a predetermined connecting wire (not shown). Here, the ground conductor 61 and the ground conductor 60 may be connected via a conductor formed in a known via hole.

The conductor 62 is integrally formed with the drain electrode 44 on the semiconductor substrate 40 on the upper and lower sides of the drain electrode 44 and the lower right side of the figure.
The plane shape of this conductor 62 is L which is a combination of two rectangles.
It is a letter shape and is composed of a rectangular portion 62a on the MESFET 41 side having a width of the gate width w ₁ and a rectangular portion 62b on the MESFET 51 side.
An insulating layer 64 made of a rectangular dielectric is formed on the ground conductor 61 on the upper and lower sides of the rectangular portion 62a of the conductor 62 in the figure and on the semiconductor substrate 40 in the vicinity of the ground conductor 61.
The conductor 63 is formed on the semiconductor substrate 40 in the vicinity of the insulator layer 64 between the 64 and the rectangular portion 62a of the conductor 62, and on the insulator layer 64. The conductor 63, the insulator layer 64, and the ground conductor 61 constitute a metal-insulator-metal capacitor (hereinafter referred to as MIM capacitor) 68. The bias connection terminal 38 is connected to the conductor 63.

Impurity ions are preliminarily implanted into the semiconductor substrate 40 from the end portion 63a of the conductor 63 on the semiconductor substrate 40 to the upper and lower end portions 62aa of the rectangular portion 62a of the conductor 62 in the drawing, whereby the resistor 46 is formed. Therefore, the conductor 62 is connected to the ground conductor 61 via the resistor 46, the conductor 63, and the insulator layer 64.

A rectangular conductor 65 is provided on the semiconductor substrate 40 below the end of the rectangular portion 62b of the conductor 62, and the gate electrode 52 of the MESFET 51.
And the conductor 65 is connected to one side of the gate length g ₂ of the gate electrode 52. An insulator layer (not shown) made of a dielectric is formed between the conductor 65 and the rectangular portion 62b of the conductor 62, and the insulator layer, the conductors 62 and 65 form the insulator layer.
It constitutes the MIM capacitor 70. Therefore, the conductor 62 is connected to the conductor 65 via the insulating layer.

In the figure, the upper and lower ends 65a of the conductor 65 to the above end 6 of the grounding conductor 61.
Impurity ions are preliminarily implanted into the semiconductor substrate 40 up to the vicinity 61a on the 5a side, whereby the resistor 47 is formed. Therefore, the conductor 65 is connected to the ground conductor 61 via the resistor 47.

An insulator layer 67 made of a dielectric is formed on the ground conductor 61 on the upper and lower sides of the drain electrode 54 of the MESFET 51 and on the semiconductor substrate 40 between the ground conductor 61 and the drain electrode 54, and the gate width is further formed. A rectangular conductor 66 having w ₂ is integrally formed with the drain electrode 54 on this insulator layer 67. The conductor 66, the insulator layer 67, and the ground conductor 61 form the MIM capacitor 69, whereby the drain electrode 54 of the MESFET 51 is connected to the ground conductor 61 via the conductor 66 and the insulator layer 67. Further, a bias connection terminal 39 is connected to the conductor 66.
Is connected.

The conductor 12 of the output microstrip line is the source electrode.
Source electrodes on the semiconductor substrate 40 on the upper and upper right sides of the figure 53
It is formed integrally with 53. Here, the planar shape of the conductor 12 is a substantially rectangular shape having a width l ₂ in the gate length g ₂ direction, and a part of the side of the conductor 12 in the gate width w ₂ direction is connected to the source electrode 53, which is good. Conductor 12 to obtain good input / output electrical isolation
The portion on the conductor 11 side is cut so as to be separated from the conductor 11 as much as possible. Therefore, the conductor 12 is connected to the source electrode 53, and the conductor 12 having the width l ₂ is used as the output microstrip line of this impedance conversion circuit.

With the above configuration, an impedance conversion circuit between the input / output microstrip lines 11 and 12 having different characteristic impedances can be configured, and the high frequency equivalent circuit of the monolithic integrated circuit of the second embodiment is the first As shown in FIG. 1, the same effect as that of the above-mentioned first embodiment is obtained.

Third Embodiment FIG. 4 (A) is a plan view of a monolithic integrated circuit for impedance conversion of the input / output coplanar lines 71 and 72 according to the third embodiment of the present invention, and FIG. 4 (B). FIG. 4 is a vertical sectional view taken along the line CC ′ of FIG. 4 (A). The fourth
The vertical cross-sectional view taken along the line AA 'of FIG. 3A is the same as FIG. 3B except that the ground conductor 60 is not formed and the conductor 11 becomes the conductor 73. In FIGS. 4A and 4B, the same parts as those in the above-mentioned drawings are designated by the same reference numerals.

The circuit of the third embodiment differs from the circuit of the second embodiment in that (1) the input / output microstrip lines 11 and 12 are replaced by the input / output coplanar lines 71 and 72, and (2) the MESFET 51 is MESF having two gate electrodes 52a, 52b, two drain electrodes 54a, 54b and a source electrode 52a
(3) The conductor 11 was replaced by the conductor 73, the conductor 12 was replaced by the conductor 75, and the ground conductor 61 was replaced by the ground conductors 74a and 74b by the above (1), (4) The two drain electrodes 54a and 54b according to (2) above.
Two MIM capacitors 69a and 69b respectively connected to
(5) The ground conductor 60 is not formed on the lower surface of the semiconductor substrate 40. Hereinafter, the above differences will be described in detail.

The conductor 73 is integrally formed with the source electrode 43 on the semiconductor substrate 40 on the upper side of the source electrode 43 of the MESFET 41 in the figure, and the plane shape of the conductor 73 has a width l _{3 in the} gate width w ₁ direction and a long side. It has a rectangular shape. Here, one side of the width l ₃ of the conductor 73 is connected to the central portion of the side of the source electrode 43 in the gate width w ₁ direction. The ground conductor 74a is integrally formed with the gate electrode 42 and the ground conductor 74b on the left end edge of the semiconductor substrate 40 in the figure and the entire lower surface of the MESFETs 41 and 51a, and the conductors 73 and 75 and the ground conductor 74b.
Is formed in a coplanar relationship with. This ground conductor 74a is conductor 73
Are formed at a predetermined interval l ₄ and are connected to one side of the gate electrode 42 in the gate length g ₁ direction.

Further, similarly to FIG. 3 (B), the drain electrode of the MESFET 41
An insulating layer 64 is formed on the ground conductor 61 on the upper and lower sides of the drawing of FIG.
The conductor 63, the insulator layer 64, and the ground conductor 74a form a MIM capacitor 68.

Further, the ground conductor 74b is connected to the right side of the MESFET 41 in the figure and the MESFE.
It is formed on the semiconductor substrate 40 above the T51a integrally with the gate electrode 42 and the ground conductor 74a and in a coplanar relationship with the conductors 73 and 75 and the ground conductor 74a. The ground conductor 74b is formed apart from the conductor 73 by a predetermined distance l _4, and is connected to the other side of the gate electrode 42 in the gate length g ₁ direction. Here, the above-mentioned conductor 73 and the ground conductors 74a and 74b constitute the input coplanar line 71.

After forming the operating layer 55a by implanting impurity ions from the upper surface of the semiconductor substrate 40 at the same position as the position of the MESFET 51 of the second embodiment described above, the two gate electrodes 52a and 52b are
The conductor 6 is formed on the operating layer 55a at a predetermined distance from the substantially central position of the operating layer 55a where the source electrode 53a is formed.
Formed integrally with 5. Here, the gate electrodes 52a and 52b
Each planar shape is a rectangular shape having a long side of the gate width w _{2 and} a side of the gate length g ₂ , and the side of the gate width of the gate electrodes 52a and 52b is the long side of the conductor 75 of the output coplanar line 72. Each side of the gate electrodes 52a and 52b in the gate length g ₂ direction is connected to the conductor 65 described above.

Further, the source electrode 53a is replaced by the gate electrodes 52a and 52b.
The operation layer 55a is sandwiched between and separated by a predetermined distance.
It is integrally formed with the conductor 75 on the top. The planar shape of the source electrode 53a is rectangular, and the side in the longitudinal direction of the electrode 53a is parallel to the side in the gate width w ₂ direction of the gate electrodes 52a and 52b. Also, the two drain electrodes 54a and 54b are
The gate electrode 52a is formed on the outside of the gate electrodes 52a and 52b opposite to the side where the source electrode 53a is formed.
The conductors 66a and 66b are formed integrally with the conductors 66a and 66b on the operating layer 55a with a predetermined distance from the conductors a and 52b. The drain electrode
The planar shape of 54a, 54b is rectangular, and the electrodes 54a, 54b
Of the gate electrodes 52a and 52b are parallel to the sides of the gate electrodes 52a and 52b in the gate width w ₂ direction.

On the ground conductors 74a and 74b on the upper and lower sides of the drain electrode 54a of the MESFET 51a and on the upper side of the figure of 54b, and the ground conductor 74.
a, 74b and the drain electrode 54a, on the semiconductor substrate 40 between 54b, the insulating layers 67a and 67b respectively a dielectric material is formed, further, rectangular conductor 66a having the gate width w ₂
And 66b are integrally formed with the drain electrodes 54a and 54b on the insulator layers 67a and 67b, respectively. The conductor 66a, the insulator layer 67a, and the ground conductor 74a allow the MIM capacitor 69a to
The drain electrode 54a of the MESFET 51a is thereby connected to the ground conductor 74a via the conductor 66a and the insulator layer 67a. Similarly, the MIM capacitor 69b is formed, and the drain electrode 54b of the MESFET 51a is connected to the ground conductor 74b via the conductor 66b and the insulator layer 67b. The bias connection terminal 39 is connected to the conductor 66a.

Furthermore, the gate electrodes 52a and 52b, the drain electrode 54
a, 54b and the source electrode 53a on the conductor 66a and 66b in the gate width w ₂ direction substantially central portion and its vicinity, for example, SiO ₂ , Si
After forming the insulator layer 90 made of N or photoresist (in this case, removed later), the connection conductor 76 insulated from the gate electrodes 52a, 52b and the source electrode 53a via the insulator layer 90.
On the insulator layer 90 and the conductor layers 66a and 66b.
It is formed on the vicinity of 90, and the conductors 66a and 66b are electrically connected via the connection conductor 76.

As described above, the MESFET 51a is constituted by the drain electrodes 54a and 54b, the gate electrodes 52a and 52b, and the source electrode 53a which are formed on the operating layer 55a in the semiconductor substrate 40 by a known method.

The conductor 75 is formed integrally with the source electrode 53a and spaced apart from the ground conductors 74a and 74b by a predetermined distance l _{6 in a} coplanar relationship with the ground conductors 74a and 74b. The plane shape of the conductor 75 has a predetermined width l ₅
One side of the width of the conductor 75 in the gate length g ₂ direction is connected to the source electrode 53a. This conductor 75
And the ground conductors 74a and 74b, the output coplanar line 72
Is composed.

With the above configuration, an impedance conversion circuit between the input / output coplanar lines 71 and 72 having different characteristic impedances can be constructed, and the high frequency circuit of the monolithic integrated circuit according to the third embodiment is shown in FIG. Thus, the same effect as the first embodiment described above is obtained.

Fourth Embodiment FIG. 5 is a plan view of a monolithic integrated circuit for impedance conversion of the input / output slot lines 81 and 82 according to the fourth embodiment of the present invention. The same symbols are attached to the same components.

The circuit of the fourth embodiment differs from the circuit of the second embodiment in that (1) the input / output microstrip lines 11 and 12 are replaced by the input / output slot lines 81 and 82, and (2) the above ( According to 1), the conductor 11 is replaced by the conductor 83, the conductor 12 is replaced by the conductor 85, and the ground conductor 61 is replaced by the ground conductor 84, and (3) the ground conductor 60 is provided on the lower surface of the semiconductor substrate 40. It is not formed. Hereinafter, the above differences will be described in detail.

The conductor 83 is separated from the ground conductor 84 on the upper and upper left sides of the source electrode 43 of the MESFET 41 in the figure by a predetermined distance l ₇ , and is integral with the source electrode 43 and in a coplanar relationship with the ground conductor 84. It is formed. The planar shape of this conductor 83 is the above-mentioned interval l ₇
It is a substantially rectangular shape having a width in the direction of the gate length g ₁ that is sufficiently wider than that of the conductor 83 on the right side of the drawing so as to be as far as possible from the conductor 85 on the output side in order to obtain good input / output isolation. It is a shape that a part of is cut. The ground conductor 84 is formed in the same manner as the ground conductor 61 of the second embodiment, and is separated from the conductor 85 by a predetermined distance l ₈ at the edge portion of the semiconductor substrate 40 on the lower right side in the drawing. It is formed in a coplanar relationship with 85. The input slot line is formed by the conductor 83 and the ground conductor 84.
Make up 81.

Further, the conductor 85 is formed on the semiconductor substrate 40 on the upper side and the upper right side of the source electrode 53 in the figure, integrally with the source electrode 53 and in a coplanar relationship with the ground conductor 84. Here, the plane shape of the conductor 85 is a substantially rectangular shape having a width in the gate length g ₂ direction that is sufficiently wider than the width l _{8, and} a part of the side of the conductor 85 in the gate width w ₂ direction is the source electrode. In order to obtain good electrical input / output isolation, the portion of the conductor 85 on the conductor 83 side is cut so as to be separated from the conductor 83 as much as possible. The conductor 85 and the ground conductor 84 form an output slot line 82.

With the above structure, an impedance conversion circuit between the input / output slot lines 81 and 82 having different characteristic impedances can be formed, and the high frequency circuit of the monolithic integrated circuit of the fourth embodiment has the first structure.
As shown in the figure, the same effect as that of the above-described first embodiment is obtained.

In the above fourth embodiment, the output coplanar line 82
The conductor 85 of is formed on the upper side of the MSFET 51 in the figure, but not limited to this, in order to obtain better input / output electrical isolation,
Source electrode 53 and drain electrode 54 of MESFET 51 are gate electrodes
A ground conductor 84 connected to the drain electrode 54 via the MIM capacitor 69 is formed on the upper side of the MESFET 51 in the figure, while the source electrode is formed on the upper and lower sides of the MESFET 51 in the figure.
You may make it form the conductor 85 connected to 53.

Other Embodiments In the above embodiments, the MESFET is used as the active element that performs impedance conversion, but the present invention is not limited to this, and other types of FETs may be used. Further, although the microstrip line, the slot line, or the coplanar line is used as the input / output line, the present invention is not limited to this, and other microwave lines may be used.

Furthermore, in the above embodiments, the input / output line is
Although microwave lines having characteristic impedances different from each other are used, the present invention is not limited to this, and the impedance conversion circuit may be configured using input / output microwave lines having the same characteristic impedance, and the impedance conversion circuit may be used as, for example, an isolator. .

In the above embodiments, the input line and the output line use the same type of microwave line, but the present invention is not limited to this, and different types of microwave lines may be used.

[Effects of the Invention] As described in detail above, according to the present invention, the first field-effect transistor with grounded gate and the second field-effect transistor with grounded drain are connected in cascade, and the characteristics of the input microwave line are provided. Let Z ₀₁ be the impedance, the mutual conductance of the first field effect transistor be gm _1, and the characteristic impedance of the output microwave line be Z 1.
_02, and when the mutual conductance of the second field effect transistor is gm ₂ , gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1 and the gate width of the first field effect transistor and the The gate width of the field effect transformer 2 was set. As a result, it is possible to realize an impedance conversion circuit between the microwave lines in which impedance matching between the input and output microwave lines is achieved and the electrical isolation between the input and output is good. Further, the circuit of the present invention has a function as an isolator between the input and output and can be made extremely small as compared with the conventional example, so that it is extremely effective to be applied to various monolithic microwave / millimeter wave integrated circuits.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a basic circuit of an impedance conversion circuit using an FET, which is an embodiment of the present invention, and FIG. 2 is a first embodiment of the present invention, which shows impedance conversion between input and output microstrip lines. FIG. 3A is a plan view of a hybrid integrated circuit for the purpose of FIG. 3A, and FIG. 3B is a plan view of a monolithic integrated circuit for impedance conversion between the input and output microstrip lines according to the second embodiment of the present invention. ) Is a vertical sectional view taken along the line AA ′ of FIG. 3A, FIG. 3C is a vertical sectional view taken along the line BB ′ of FIG. 3A, and FIG. The top view of the monolithic integrated circuit for impedance conversion of the input / output coplanar line | wire which is the 3rd Example of this invention, FIG. 4 (B) is a longitudinal cross-sectional view of the CC 'line of FIG. 4 (A). FIG. 5 shows the impedance between the input and output slot lines according to the fourth embodiment of the present invention. FIG. 6 is a plan view of a monolithic integrated circuit for impedance conversion, and FIG. 6 is a plan view of a conventional impedance conversion circuit. 21 …… input microwave line, 22,24 …… field effect transistor (FET), 23 …… resistor, 25 …… output microwave line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masayoshi Aikawa, No. 5, Mihiratani, Shoji-cho, Seika-cho, Soraku-gun, Kyoto Pref. 56, ATR Optical and Radio Communications Research Institute (56) Reference JP-A-60-153602 (JP, A)

Claims (1)

[Claims] 1. An impedance converter for connecting an input microwave line and an output microwave line, wherein a source electrode is connected to the input microwave line, and a first gate-grounded gate having a predetermined gate width is provided. And a drain electrode of the first field effect transistor, a gate electrode of which is connected to the drain electrode of the first field effect transistor, and a source electrode of which is connected to the output microwave line. And the characteristic impedance of the input microwave line is Z ₀₁ , the mutual conductance of the first field effect transistor is gm ₁ , the characteristic impedance of the output microwave line is Z _02, and Gm ₁ Z ₀₁ = gm ₂ Z ₀₂ = 1 where gm ₂ is the mutual conductance of the field effect transistor of The impedance conversion device is characterized in that the gate width of the first field effect transistor and the gate width of the second field effect transformer are set so that