JPH0851539A - Drive circuit for recording element and recording head - Google Patents

Abstract

PURPOSE:To reduce a data transfer quantity and a transfer time by comparing image data having gradation latched by a parallel shift register and held in a parallel latch circuit with comparison data latched by the parallel shift register to control the drive of a recording element. CONSTITUTION:Image data P.DATA in 8-bit or the like having gradation are held by parallel latch circuits L1-L64 via parallel shift registers SR1-SR64 in a driver IC. The data are compared with comparison data C.DATA transferred sequentially depending on a clock period from parallel shift registers CD1-CD64 by comparator circuits C1-C64 and a recording element is driven depending on the result of comparison. Through the constitution that the gradation image data are directly transferred to the driver IC, the data transfer quantity is reduced considerably, the transfer time is reduced and the circuit configuration is simplified. Furthermore, the power application start time for each recording element is deviated and power consumption is reduced by transferring the comparison data sequentially synchronously with the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording element drive circuit for controlling a recording operation of a plurality of recording elements such as a thermal head, and a recording head.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional drive circuit composed of a semiconductor integrated circuit (hereinafter simply referred to as a driver IC).
FIG. 6 is a schematic diagram of a case where a line type thermal head of 150 dpi and A4 size is configured.

In the figure, the driver ICs 1 to 20 have the same specifications, and each IC has 64 as a recording element.
The individual heating resistors R1 to R64 can be driven, and the energization of a total of 1280 heating resistors is controlled. The operation of the driver IC will be described with reference to the driver IC 1, SR
1 to 64 are shift registers in which print data serially transferred from a head control circuit (not shown) is input to a data input terminal D and performs a shift operation in synchronization with a transfer clock input to a terminal CLK. L1 to 64 are latch circuits for holding the transferred print data by a latch signal input to the terminal LATCH, and DR1 to 64 are the print data held in this latch circuit and STROBE.
NAND with the strobe signal input to the terminal,
Heating resistors R1 to 6 connected to the corresponding DO terminals
4 is an energization control circuit for energizing No. 4.

The thermal head is heated by Joule heat by supplying a current to the heating resistor to perform recording.
Therefore, assuming that the current flowing through one heating resistor R is Id, in the case of collective driving in which all the resistors are energized simultaneously, 128
A current of 0 × Id flows. This requires a large output power supply device, which is large and costly. Therefore, a plurality of continuous heating resistors are set as one group (block), and the line type thermal head is set as a plurality of groups (20 groups in this embodiment).
The division drive is often used, which is configured by and the power distribution of each group is time-divided. Divided drive consumes less current than batch drive
/ It can be reduced to the number of divisions. However, there is a drawback that streak-like density unevenness occurs at the boundaries of the divided blocks.

In order to solve such a defect, Japanese Patent Publication No. 62-62
In the prior art disclosed in Japanese Patent Laid-Open No. 50011, density unevenness between blocks is reduced by overlapping the energization times of adjacent blocks as shown in FIG.
In the figure, the strobe signal STB1 is the heating resistor R.
1 to 64, the strobe signal STB2 is the heating resistor R6.
This is a signal for permitting the energization of 5 to 128, and the energization start time in the adjacent block is shifted by 1/2 hour from the strobe signal. Further, in the prior art disclosed in Japanese Patent Laid-Open No. 3-292163, as shown in FIG. 11, not a control for each block but a driving method for delaying the energization start time for each heating resistor is also known. In the figure, Dr1 to 4 are print data of the heating resistors Rn, and signal waveforms obtained by ANDing Dr1 to 4 and strobe signals are heating resistors R1 to Rn.
It becomes the electric current which flows to 4. The shorter the delay in the energization start time between the blocks or between the heating resistors, the more effective the reduction in the density unevenness is.

However, a driving method as shown in FIG. 11 in which the energization start time is made different for each heating resistor is shown in FIG.
However, there is a problem that the control time becomes longer and the transfer time becomes longer with the increase of the transfer amount of the print data in order to realize it with the existing driver IC.

FIG. 12 shows a timing chart when the above-mentioned driving method is performed by the thermal head shown in FIG. In this example, 256 gradations / dots are obtained by controlling the energization of each heating resistor in 256 stages of time. In the figure, Ir1 to 1280 are current waveforms flowing to the heating resistor,
The print data and the strobe signal are ANDed. In the print data group D1, it is necessary to validate only the data of the first gradation of the heating resistor R1, but since the circuit for receiving the print data is composed of the shift register as shown in FIG. Dummy data 0 must be transferred as print data as the data for the heating resistors R2 to 1280. Similarly, in the print data group D2, the heating resistor R
The dummy data 0 is transferred as the print data for the second gradation data of 1, the first gradation data of the resistor R2, and the resistors R3 to 1280.

The timing at the end of printing the first line is
In the print data group D1534, the 25th value of the resistor R1280
The data of the fifth gradation and the dummy data 0 for the resistors R1 to 1279 are transferred. By this time, the print data group is 15
It is necessary to transfer 34 times, and if the transfer clock is 4 MHz, 320 μs (1/4 MHz x 1 data group transfer)
1280 bits), and 1534 times requires 490 ms, which is not realistic. Actually, the method of increasing the number of signals of print data and ending the transfer time in a short time is adopted.
Even with this method, it takes about 25 ms even if the number of print data signals is 20. That is, in order to make the energization start time of each heating resistor different by using the existing driver IC, the amount of data transferred from the head control circuit to the thermal head becomes huge, the transfer time becomes long, and It will be complicated.

[0009]

DISCLOSURE OF THE INVENTION The present invention, as shown in the above-mentioned conventional example, provides a driving method for making the energization start time of each recording element different so as to reduce the uneven power density while reducing the power consumption. This problem has been solved in view of a problem that occurs when a conventional driver IC is used, that is, a long transfer time due to an increase in data transfer amount and a complicated head control circuit. It is an object of the present invention to provide a drive circuit having a function of directly fetching data and differentiating the energization start time of each recording element, and a recording head incorporating the same.

[0010]

A drive circuit according to claim 1 of the present invention is a drive circuit for controlling a recording operation for a plurality of recording elements, and has a gradation composed of a plurality of bits. A plurality of bits of parallel shift registers that take in image data for each of the plurality of recording elements, a latch circuit that is connected to each of the shift registers and holds the image data, and a comparison target of the image data held in the latch circuit And a comparator for comparing the comparison data with the image data held in each of the latch circuits. The comparison data is synchronized with the comparison data transfer clock. Then, the data is taken into the comparator and the shift operation is performed, and the comparison is performed by the comparator. And controlling the.

A recording head according to a second aspect of the present invention is characterized by including the drive circuit and a plurality of recording element groups which are divided into blocks for each drive circuit unit.

[0012]

With such a configuration, it is possible to directly transfer image data having gradations to the drive circuit (driver IC), so that the data transfer amount is extremely reduced and the transfer time can be shortened. The circuit configuration can be simplified. Furthermore, by transferring the comparison data to be compared with the image data in synchronization with the comparison data transfer clock, the energization start time of each recording element can be made to differ by this clock cycle, while reducing power consumption. It is possible to obtain a high-definition image with no division density unevenness.

[0013]

1 is a block diagram of a thermal head (recording head) equipped with an embodiment of a drive circuit according to the present invention. 2 and 3 are timing charts for explaining the basic operation of the drive circuit (driver IC) shown in FIG. The operation of one embodiment of the drive circuit of the present invention will be described below with reference to FIGS.

In FIG. 1, the inside of the frame shown by the broken line corresponds to one driver IC. SR1 to SR64 are 8-bit parallel image data shift registers, L1 to 64 are 8-bit parallel image data latch circuits, CD1 to 64 are 8-bit parallel image comparison data shift registers, and C1 to C6.
Reference numeral 4 is a comparator that determines the magnitude relationship between 8-bit parallel image data and 8-bit parallel image comparison data.
R1 to 64 are data output terminals DO1 to 6 of the driver IC
4 is a heat-generating resistor connected to 4.

The operation sequence will be described with reference to FIG. 2. First, by supplying a comparison data set signal and a reset signal to the SETcd terminal and the RESET terminal of the driver IC, the CDs 1 to 64 in this IC are given. The output of each of the bits is "H" and indicates 255 (FFH), and the output of each of SR1 to 64 and L1 to 64 is "L" and indicates 0. Next, the image data is transferred. Image data input terminal P. DATAin has an 8-bit bus as described above, and can provide 8-bit image data to one heating resistor, and as a result, an image of 256 gradations / pixel can be obtained. By inputting this image data in synchronization with the image data clock given to the terminal CLKpd, SR1 to SR2, SR2
From 8 to SR3, 8-bit parallel image data is shifted, and the first (first) image data is transferred to SR64 and the last (64th) by a total of 64 clock inputs.
The image data transferred to (th) is given to SR1. By adding a latch signal after the transfer of the image data, the image data output to the shift registers SR1 to 64 are held in the corresponding latch circuits L1 to L64, respectively. After the completion of the latch operation, it is possible to accept the transfer of the image data of the next line. By this latch operation, 8-bit parallel image data is transferred to the latch circuit L.
It is output from 1 to 64 and given to the input terminal Q of the comparators C1 to 64.

Next, the comparison data is transferred from the external head control circuit to the terminal C. Transfer to DATAin is performed in synchronization with the comparison data clock given to the terminal CLKcd. This comparison data is data to be compared with the input image data, and if 256 gradations / pixel are to be expressed,
This comparison data is input in increments of 1 from 0 to 255. Since the comparison data is received by the comparison data 8-bit parallel shift register, the comparison data flow is the same as that of the image data shift register described above from CD1 to CD2 and CD2 to CD.
3, the shift operation is performed in synchronization with the comparison data clock. First (first) data of comparison data ”
Taking "0" as an example, the output of the shift register CD1 becomes "0" by the first pulse of the comparison data clock,
The shift operation is performed such that the output of the shift register CD2 becomes "0" by the second pulse of the comparison data clock.

The comparison data shift registers CD1 to CD1
The output of 64 is given to the input terminal P of the said comparator C1-64. Image data is given to the other input terminal Q of the comparator as described above, and the data out terminal DOn corresponding to the case of Q> P is activated by the comparator.

By thus shifting the comparison data by the 8-bit parallel shift register, the comparison data to be compared with the image data held in each of the latch circuits L1 to L64 at any time is not necessarily equal. Therefore, DO1 to 64 (DO4 to DO62) in FIG.
Is omitted), the energization start timing of the adjacent heating resistors can be shifted by the time corresponding to the cycle of the comparison data clock by the enable signal from the output enable terminal OE. .

FIG. 3 is a timing chart at the end of energization for one line. Taking the DO3 output that determines the energization time to the heating resistor R3 as an example, the gradation of the image data is set to 25.
3 (FDH), CD3 output is 253 (FDH)
When it changes to, that is, 2 of the comparison data clock
The DO3 output becomes non-active in synchronization with the 56th pulse (3 + 253). In the case of DO64, 255 (FFH) corresponding to the maximum density of the image data is added, and the 319th pulse of the comparison data clock (64 + 2)
It becomes non-active in synchronism with 55), and printing of image data for one line is completed. At the time when 319 pulses of the comparison data clock are output, CD1 to CD1
Are all 255 (FFH), and it is not necessary to give a comparison data set signal to the terminal SETcd prior to printing the next line.

Next, this driver IC is A4 size, 1
An example mounted on a 50 dpi line thermal head is shown. FIG. 4 is a schematic view of this thermal head. Since a print width of 210 mm or more is required to perform A4 size printing, 20 of these driver ICs are mounted and 1280 do
heating resistor R1 to 1280 (print width is about 216.7)
mm) of each energization is controlled. In FIG. 4, since both the SETcd terminal and the RESET terminal of this driver IC are terminals used for the initial operation of the IC, they are connected in the thermal head and used as RESET terminals for external connection.

Here, the specifications of a thermal printer using this thermal head will be described. The drive method that starts the energization of an arbitrary heating resistor (group) before the energization of the adjacent heating resistor (group) is finished is such that divided driving is performed while reducing the maximum power consumption as compared with collective heat generation. As described above, there is an advantage in that no uneven division density occurs. In this embodiment, the energization time of each heating resistor was set to 10 ms, and the maximum power consumption was set to 62.5% of the batch heat generation. That is, the maximum consumption in the case of solid printing (maximum density of all dots) is set by setting the energization of the heating resistor R801 to start immediately after the maximum density is obtained in the heating resistor R1 (energization of 10 ms). Power reduction is (800/1280) x 100 =
It becomes 62.5%. Further, since the start of energization of each heating resistor is delayed in synchronization with the comparison data clock, the cycle of the comparison data clock is 10 ms / 800 = 12.5 μ.
s (80 KHz), and 800 clocks are energized to obtain the maximum concentration.

Before explaining the operation of the thermal head of FIG. 4, the relationship between the energization time and the print density in the sublimation printer will be mentioned. FIG. 5 is a graph showing the relationship between energization time and print density of a sublimation printer. As can be seen from the figure, the relationship between the energization time and the print density is not linear, the slope is low in the low density and high density regions, and steep in the medium density region. In other words, in order to obtain linear gradation in the print output, it is necessary to give the energization time corresponding to each gradation. Therefore, in this embodiment, the control is performed according to the table of the number of gradations and the number of energizing pulses as shown in FIG. To print the density of the first gradation, 84 gradations of the image comparison data clock, 110 clocks for the second gradation, ... To be However, it goes without saying that the curve of the energization time and the print density in FIG. 5 changes depending on the temperature inside the printer, the heat storage state of the thermal head substrate, the power supplied to the heating resistor, and the recording medium such as an ink sheet.

7 and 8 are timing charts for explaining the operation of the embodiment shown in FIG. In both figures, the gradation of the heating resistors R1 and R2 is one level, and the heating resistor R1
279 is an operation when image data of 254 level and the heating resistor R1280 gives 255 level of image data corresponding to the maximum density, and the current waveform flowing through the heating resistor Rn is indicated by Irn. The signal waveform of the CDn output (1 ≦ n ≦ 1280) is the output value of the comparison data shift register in the driver IC corresponding to the heating resistor Rn of the thermal head.

In FIG. 7, the transfer of the image data of the first line and the timing of starting the energization of the heating resistor will be described. A reset signal is given prior to the transfer of the first line. With this signal, the driver ICs 1 to 20
The outputs of the shift registers CD1 to 1280 are set to 255 (FFH), and the shift registers SR1 to 128 are set.
0 and the outputs of the latch circuits L1 to 1280 are reset to 0. This signal may be given once when the thermal head is powered on.

Next, the image data is transferred in synchronization with the image data clock signal. Since the image data transfers 8-bit gradation data in parallel, 1280 is used in this embodiment.
It suffices to transfer dots, that is, 1280 bytes of data, and 320 μs if the transfer clock is 4 MHz.
Then, the transfer of the image data for one line is completed. By giving a latch signal after the transfer of the image data, the image data is held in the latch circuits L1 to 1280.

Next, by setting the comparison data to 0 and applying the first pulse of the comparison data clock signal, the output of CD1 changes from 255 to 0, and the comparator C1 outputs C
The output 0 of D1 is compared with the value of the latch circuit L1 holding the image data for the heating resistor R1. Now, assuming that the image data for the heating resistor R1 has a gradation of 1, the comparison result shows that the image data is larger, so that energization to the heating resistor R1 is started. Next, the second comparison data clock
By giving the pulse number, the output of CD2 becomes 0 and the heating resistor R2 starts to be energized. Similarly, the energization of each heating resistor is started with a delay of one pulse with the input of the comparison data clock, and the heating resistor R127
The energization of No. 9 starts at the 1279th pulse of this clock, and the energization of the heating resistor R1280 starts at the 1280th pulse of this clock.

As shown in the relationship between the number of gradations and the number of energizing pulses in FIG. 6, the comparison data requires 84 clock cycles to obtain the density of the first gradation. 0 is continuously transferred until 84 pulses of the comparison data clock are input and incremented to 1 before the 85th pulse. As a result, at the 85th pulse of this clock, the output of CD1 changes from 0 to 1 and becomes equal to the image data, the output of the comparator C1 becomes "L", and the power supply to the heating resistor R1 is stopped. In this way, the output of the comparator C1 continuously outputs "H" until it becomes equal to the value of the image data.

FIG. 8 shows the timing at the end of printing the first line, and assuming that the image data is 254 (FEH) at the end of energization of the heating resistor R1279, it is the 2072 pulse of the comparison data clock. (1279 (the number of pulses required to start energization by transfer) +793 (the number of pulses corresponding to the gradation 254 in FIG. 6)). Further, when the energization of the heating resistor R1280 ends, the image data has the maximum gradation of 25.
2 of this clock to be able to energize up to 5 (FFH)
It becomes the 080th pulse (1280 + 800).

In the drive circuit of the present invention, the heating resistor is used as the recording element in the above embodiment, but the present invention is not limited to this, and it is possible to record image data having gradation by controlling the energization time. It is applicable to recording elements.

[0030]

According to the present invention, since it has a function of holding image data having a gradation consisting of a plurality of bits per pixel and shifting the image comparison data transferred from the outside, It is possible to shorten the data transfer time, reduce the load on the circuit that controls the printing elements, and further delay the energization start time of multiple printing elements connected to the drive circuit individually. It is possible to obtain an image with no division density unevenness while reducing power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a thermal head equipped with an embodiment of a drive circuit of the present invention.

FIG. 2 is a timing chart showing the operation of the drive circuit of FIG. 1 at the start of energization for one line.

3 is a timing chart showing the operation of the drive circuit of FIG. 1 at the end of energization for one line.

FIG. 4 is a schematic diagram when the drive circuit of FIG. 1 is mounted on a thermal head which is an example of the recording head of the present invention.

FIG. 5 is a graph showing the relationship between energization time and print density in a sublimation printer.

FIG. 6 is a table showing the relationship between the number of gradations and the number of energizing pulses in a sublimation printer.

7 is a timing chart showing the operation of the thermal head of FIG. 4 at the start of energization for one line.

8 is a timing chart showing the operation of the thermal head of FIG. 4 at the end of energization for one line.

FIG. 9 is a schematic diagram of a thermal head equipped with a conventional drive circuit (driver IC).

FIG. 10 is a timing chart for explaining a conventional thermal head driving method.

FIG. 11 is a timing chart for explaining a conventional thermal head driving method.

FIG. 12 is a timing chart when the energization start time of each heating resistor is made different by using a conventional drive circuit (driver IC).

[Explanation of symbols]

 C1 to 64: Comparator CD1 to 64: Image comparison data shift register L1 to 64: Image data latch circuit R1 to 1280: Heating resistor SR1 to 64: Image data shift register

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[Procedure amendment]

[Submission date] September 20, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

In FIG. 1, the inside of the frame shown by the broken line corresponds to one driver IC. SR1 to SR64 are 8-bit parallel image data shift registers, L1 to 64 are 8-bit parallel image data latch circuits, CD1 to 64 are 8-bit parallel image comparison data shift registers, and C1 to C6.
Reference numeral 4 is a comparator that determines the magnitude relationship between 8-bit parallel image data and 8-bit parallel image comparison data.
R1 to 64 are data output terminals DO1 of the driver IC
~ 64 is a heating resistor connected.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

The comparison data shift registers CD1 to CD1
The output of 64 is given to the input terminal P of the said comparator C1-64. Image data is applied to the other input terminal Q of the comparator as described above, and the data out terminal inversion DOn corresponding to the case of Q> P is activated by the comparator.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

By thus shifting the comparison data by the 8-bit parallel shift register, the comparison data to be compared with the image data held in each of the latch circuits L1 to L64 at any time is not necessarily equal. Therefore, the inversion DO1 to 64 (inversion DO4 to FIG.
As shown in (DO 62 is omitted), the energization start timing of the adjacent heating resistor can be shifted by the time corresponding to the cycle of the comparison data clock by the enable signal from the output enable terminal OE. Is.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

FIG. 3 is a timing chart at the end of energization for one line. Taking the inverted DO3 output that determines the energization time to the heating resistor R3 as an example, when the gradation of the image data is 253 (FDH), the CD3 output is 253 (FD
H), that is, inversion D in synchronization with the 256th pulse (3 + 253) of the comparison data clock.
The O3 output becomes non-active. In the case of the inverted DO64, 255 (FFH) corresponding to the maximum density of the image data is added, and the image data becomes non-active in synchronization with the 319th pulse (64 + 255) of the comparison data clock,
Printing of the image data for one line is completed. At the time when 319 pulses of the comparison data clock are output,
The outputs of CD1 to 64 are all 255 (FFH), and the comparison data set signal is output to the terminal SE before printing the next line.
There is no need to give it to Tcd.

Front Page Continuation (72) Inventor Ma ▲ Fuchi ▼ Koji 2-5-5 Keihan Hon-dori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A drive circuit for controlling a recording operation for a plurality of recording elements, wherein a plurality of bits are arranged in parallel for capturing image data having a gradation composed of a plurality of bits for each of the plurality of recording elements. A shift register; a latch circuit connected to each of the shift registers for holding the image data; a parallel shift register of a plurality of bits for fetching comparison data to be compared with the image data held in the latch circuit; A comparator for comparing the image data held in each of the latch circuits with the comparison data, wherein the comparison data is loaded into the comparator and shifted in synchronization with the comparison data transfer clock; A printing element drive circuit characterized by comparing and controlling the drive of each printing element based on the comparison result. 2. A recording head comprising: the drive circuit according to claim 1; and a plurality of recording element groups divided into blocks for each drive circuit unit.