JPH0858132A - Driving circuit of recording element and recording head - Google Patents

Abstract

PURPOSE: To obtain a drive circuit having function differentiating the current supply start times of individual recording elements by controlling the driving of the respective recording elements on the basis of the comparison result of a comparator and a recording head having the driving circuit incorporated therein. CONSTITUTION: Comparison data is set to '0' and shift operation is performed so that an image comparison data shift register CD1-Q becomes '0' from '55' by applying the first pulse of a comparison data clock and an image comparison data shift register CD2-Q becomes '0' from '255' by applying the second pulse of the comparison data clock. Therefore, CD1279-Q and CD1280-Q change to '0' from '255' by the 1279-th and 1280-th pulses of the comparison data clock. The outputs of image comparison data shift registers CD1-64 are applied to the input terminals of comparators C1-C1280.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording element drive circuit for controlling a recording operation of a plurality of recording elements such as a thermal head, and a recording head.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional drive circuit composed of a semiconductor integrated circuit (hereinafter, simply referred to as a driver IC).
FIG. 6 is a schematic diagram of a case where a line type thermal head of 150 dpi and A4 size is configured.

In the figure, the driver ICs 1 to 20 have the same specifications, and each IC has 64 as a recording element.
The individual heating resistors R1 to R64 can be driven, and the energization of a total of 1280 heating resistors is controlled. The operation of the driver IC will be described with reference to the driver IC 1, SR
Reference numerals 1 to 64 denote shift registers in which image data serially transferred from a head control circuit (not shown) is input to a data input terminal D and performs a shift operation in synchronization with a transfer clock input to a terminal CLK. L1 to 64 are latch circuits for holding the transferred image data by a latch signal input to the terminal LATCH, and DR1 to 64 are the image data held in this latch circuit and STROBE.
NAND with the strobe signal input to the terminal,
Heating resistor R1 connected to the corresponding inverted DO terminal
It is an energization control circuit that energizes to 64.

The thermal head is heated by Joule heat by supplying a current to the heating resistor to perform recording.
Therefore, assuming that the current flowing through one heating resistor R is Id, in the case of collective driving in which all the resistors are energized simultaneously, 128
A current of 0 × Id flows. This requires a large output power supply device, which is large and costly. Therefore, a plurality of continuous heating resistors are set as one group (block), and the line type thermal head is set as a plurality of groups (20 groups in this embodiment).
The division drive is often used, which is configured by and the power distribution of each group is time-divided. Divided drive consumes less current than batch drive
/ It can be reduced to the number of divisions. However, there is a drawback that streak-like density unevenness occurs at the boundaries of the divided blocks.

In order to solve such a defect, Japanese Patent Publication No. 62-62
In the prior art disclosed in Japanese Patent Publication No. 50011, as shown in FIG. 7, the density nonuniformity between blocks is reduced by overlapping the energization times of adjacent blocks. In the figure, the strobe signal STB1 is the heating resistor R1.
~ 64, the strobe signal STB2 is the heating resistor R65.
This is a signal for permitting energization of up to 128, and the energization start time in the adjacent block is shifted by 1/2 hour of the strobe signal. Further, in the prior art disclosed in Japanese Patent Laid-Open No. 3-292163, as shown in FIG. 8, not a control for each block but also a driving method for delaying the energization start time for each heating resistor is known. In the figure, Dr1 to 4 are image data of the heating resistors Rn, and the signal waveform obtained by ANDing the Dr1 to 4 and the strobe signal is the current flowing to the heating resistors R1 to R4. The shorter the delay in the energization start time between the blocks or between the heating resistors, the more effective the reduction in the density unevenness is.

However, in order to realize the driving method shown in FIG. 8 in which the energization start time is different for each heating resistor with the existing driver IC of FIG. 6, the control becomes complicated and the transfer amount of image data increases. Accordingly, there is a problem that the transfer time becomes long.

FIG. 9 shows a timing chart when the above-mentioned driving method is performed by the thermal head shown in FIG. In this example, 256 gradations / dots are obtained by controlling the energization of each heating resistor in 256 stages of time. I in the figure
r1 to 1280 are current waveforms flowing to the heating resistor, and are obtained by ANDing the image data and the strobe signal. In the image data group D1, it is necessary to validate only the data of the first gradation of the heating resistor R1, but the circuit for receiving the image data is composed of the shift register as shown in FIG. Dummy data 0 must be transferred as image data as data for the heating resistors R2 to 1280. Similarly, in the image data group D2, the heating resistor R
The dummy data 0 is transferred as image data for the second gradation data of 1, the first gradation data of the resistor R2, and the resistors R3 to 1280.

The timing at the end of printing the first line is
In the image data group D1534, the 25th value of the resistor R1280
The data of the fifth gradation and the dummy data 0 for the resistors R1 to 1279 are transferred. By this point, the image data group is 15
It is necessary to transfer 34 times, and if the transfer clock is 4 MHz, 320 μs (1/4 MHz x 1 data group transfer)
1280 bits), and 1534 times requires 490 ms, which is not realistic. Actually, a method of increasing the number of image data signals and ending the transfer time in a short time is adopted.
Even with this method, it takes about 25 ms even if the number of image data signals is 20. That is, in order to make the energization start time of each heating resistor different by using the existing driver IC, the amount of data transferred from the head control circuit to the thermal head becomes enormous, the transfer time becomes long, and the head control circuit becomes longer. Will be complicated.

[0009]

DISCLOSURE OF THE INVENTION The present invention, as shown in the above-mentioned conventional example, provides a driving method for making the energization start time of each recording element different so as to reduce the uneven power density while reducing the power consumption. This problem has been solved in view of a problem that occurs when a conventional driver IC is used, that is, a long transfer time due to an increase in data transfer amount and a complicated head control circuit. It is an object of the present invention to provide a drive circuit having a function of directly fetching data and differentiating the energization start time of each recording element, and a recording head incorporating the same.

[0010]

A drive circuit according to claim 1 of the present invention is a drive circuit for controlling a recording operation for a plurality of recording elements, and has a gradation composed of a plurality of bits. A multi-bit parallel shift register for taking in image data, a first latch circuit for holding the image data at a stage subsequent to the shift register, another stage after the latch circuit and another stage after the latch circuit. A second latch circuit, a 1-bit shift register that instructs the second latch circuit to perform a latch operation, and comparison data to be compared with the image data held in the second latch circuit are fetched. A shift register having a plurality of bits in parallel; and a comparator for comparing the image data held in each of the second latch circuits with the comparison data, The capturing to the pallet and the shift operation, and the latch instruction to the second latch circuit are executed in synchronization with the comparison data transfer clock, and the comparison is performed by the comparator, and each recording element is driven based on the comparison result. It is characterized by controlling.

A recording head according to a second aspect of the present invention is characterized by including the drive circuit and a plurality of recording element groups which are divided into blocks for each drive circuit unit.

[0012]

With such a configuration, it is possible to directly transfer image data having gradations to the drive circuit (driver IC), so that the data transfer amount is extremely reduced and the transfer time can be shortened. The circuit configuration can be simplified. Furthermore, by transferring the comparison data to be compared with the image data in synchronization with the comparison data transfer clock, the energization start time of each recording element can be made to differ by this clock cycle, while reducing power consumption. It is possible to obtain a high-definition image with no division density unevenness.

[0013]

1 is a block diagram of a thermal head (recording head) equipped with an embodiment of a drive circuit according to the present invention.

In FIG. 1, the inside of the frame shown by the broken line corresponds to one driver IC. SR1 to SR64 are 8-bit parallel image data shift registers, L1A to L64A
And L1B to L64B are 8-bit parallel first and second image data latch circuits, SL1 to SL64 are 1-bit shift registers for giving a latch instruction to the second image data latch circuits L1B to L64B, CD1-C
D64 is an 8-bit parallel image comparison data shift register, C1 to C64 are comparators that determine the magnitude relationship between 8-bit parallel image data and 8-bit parallel image comparison data, and G1 to G64 are gate circuits. R1 to R6
Reference numeral 4 is a data output terminal inversion DO1 to inversion D of the driver IC
It is a heating resistor connected to O64.

The RESET terminal includes image data shift registers SR1 to SR64 and a first image data latch circuit L.
1A to L64A, second image data latch circuit L1B to
Output Q of L64B and shift registers SL1 to SL64
Reset terminal for inputting a signal to set "L" to SE
Tcd terminals are image comparison data shift registers CD1 to C
A set terminal for inputting a signal for setting the output of D64 to "H", P. The DATAin terminal is an image input data terminal for inputting 8-bit image data having a gradation in parallel, and the image data is synchronized with the image data clock input to the CLKpd terminal and each of the image data shift registers SR1 to SR1.
Input to SR64.

The LATCH A terminal is a terminal for giving an instruction to latch the image data transferred to the image data shift registers SR1 to SR64 in the first image data latch circuits L1A to L64A. The DATAin terminal is a comparison data input terminal for inputting comparison data which is a comparison target for comparing the magnitude relationship with the image data. The comparison data is CLK.
The data is input to the image comparison data shift registers CD1 to CD64 in synchronization with the comparison data clock input to the cd terminal.

The LATCH Bin terminal is a signal input terminal for latching the image data held in the first image data latch circuits L1A to L64A into the second image data latch circuits L1B to L64B, and the shift registers SL1 to SL1.
It is connected to the input terminal D of SL64. Since the CLK terminals of the shift registers SL1 to SL64 are connected to the CLKcd terminal, the shift registers SL1 to S
L64 operates in synchronization with the comparison data clock.
C. DATAout terminal, LATCH Bout terminal and P.P.
The DATAout terminals are connected to the output terminals Q of the last image comparison data shift register CD64, the shift register SL64, and the image data shift register SR64. The OE terminal is an out enable terminal that gives an enable signal to one of the gate circuits G1 to G64.

FIG. 2 shows the 64-bit driver IC
Use 0 (driver ICs 3 to 19 are not shown)
FIG. 3 is a schematic diagram of a line type thermal head having a resolution of 150 dpi and a print width of 216.7 mm. In the figure, the SETcd terminal of the driver IC and RESET
Since both terminals are used for the initial operation of the IC, they are connected in the thermal head and used as RESET terminals for external connection. Further, the driver IC 1 C.I.
DATA out terminal, LATCH Bout terminal, P. DAT
The Aout terminal is the C.I. of the driver IC2. DATAin terminal,
LATCH Bin terminal, P. The driver IC 2 and the driver IC 20 are similarly connected to the DAT Ain terminal, respectively. The out of the driver IC 20
Regarding the terminals, only the LATCH Bout terminal is provided as an external connection terminal.

The specifications for constructing a sublimation printer using such a thermal head will be described below.
The driving method that starts energization to any heating resistor before the energization of the adjacent heating resistor is finished, reduces the maximum power consumption compared to batch heat generation, and does not cause division unevenness such as division driving. As mentioned above, there are advantages. In this embodiment, the maximum energization time of each heating resistor is set to 10 ms, and the maximum power consumption is set to 62.5% of the batch heat generation. That is,
Maximum concentration was obtained with heating resistor R1 (10 ms energization)
By setting the energization of the heating resistor R801 to start immediately after that, the maximum power consumption reduction in the case of solid printing (maximum density of all dots) is (800/1280) × 100.
= 62.5%. As will be described later, the delay of the energization start time of each heating resistor is synchronized with the comparison data clock, so that the cycle of the comparison data clock is 1
0ms / 800 = 12.5μs (80KHz),
In order to obtain the maximum density, electricity is supplied for 800 clocks.

Before explaining the operation of the thermal head of FIG. 2, the relation between the energization time and the print density in the sublimation printer will be mentioned. The relationship between the energization time and the print density of a sublimation printer is generally not linear, and the slope is low in the low and high density regions and steep in the medium density region. In other words, in order to obtain linear gradation in the print output, it is necessary to give the energization time corresponding to each gradation. Therefore, in this embodiment, the control is performed according to the table of the number of gradations and the number of energizing pulses as shown in FIG. That is, in order to print the density of the first gradation, a linear gradation property is obtained by giving an energization time of 84 clocks of the image comparison data clock, 110 clocks of the second gradation, and so on. Is obtained. However, it goes without saying that the relationship between the gradation and the number of energizing pulses in FIG. 5 varies depending on the temperature inside the printer, the heat storage state of the thermal head substrate, the power supplied to the heating resistor, and the recording medium such as an ink sheet.

3 to 4 are timing charts for explaining the operation of this embodiment. In these figures, CDn
_Terminal name, LnB_Terminal name means heating resistor Rn (1 ≤ n
≤ 1280), the signal waveform of the terminal represented by the terminal name of the image comparison data shift register element CDn and the second image data latch circuit LnB is shown, and Irn is the current waveform flowing in the heating resistor Rn. ing. Also, the first
In the image data of the line, the gradation of the heating resistors R1 and R2 is 1 level, the gradation of the heating resistors R1279 and R1280 is 255 level which is the maximum density, and the image data of the second line is the heating resistor R1. , R2, R1279, R
Both 1280 have 10 levels of gradation.

First, by applying a reset signal to the RESET terminal of the thermal head prior to the transfer of the image data of the first line, the output Q of the image comparison data shift registers CD1 to CD1280 becomes "H" in all bits, 255 (FFH), the image data shift registers SR1 to SR1280, the first image data latch circuits L1A to L1280A, the second image data latch circuits L1B to L1280B, and the shift registers SL1 to SL1.
The output Q of 280 is "L" for all bits and indicates 0.
This signal may be given once when the thermal head is powered on.

Next, the image data is transferred. Image data input terminal P. As described above, DATAin forms an 8-bit bus, and 8-bit image data can be given to one heating resistor, resulting in an image of 256 gradations / pixel. This image data is the terminal CLK
By inputting in synchronization with the image data clock given to pd, the image data shift registers SR1 to S1
8-bit parallel image data such as R2 and SR2 to SR3 are shifted, and the first (first) transferred image data is transferred to the image data shift register SR1280 and the last (first) by a total of 1280 clock inputs. 1280
The image data transferred to (th) is given to the image data shift register SR1. The transfer amount of image data for one line is 1280 bytes, and the transfer time is 4
When it is set to MHz, it ends in 320 μs. After the transfer of the image data is completed, the latch signal A is added, whereby the image data output to the shift register image data shift register SR1 to image data shift register SR1280 is latch circuit first image data latch circuit L1A. ~ L1280A. After the completion of the latch operation, the image data of the next line is transferred to the image data shift register SR1 to image data shift register SR12.
It is possible to transfer to 80.

Next, the comparison data is transferred from the external head control circuit to the terminal C. The data is transferred to DATA in synchronization with the comparison data clock given to the terminal CLKcd. This comparison data is data to be compared with the input image data, and if 256 gradations / pixels are to be expressed, the comparison data is incremented from 0 to 255 in 1 steps. Since this comparison data is received by the comparison data 8-bit parallel shift register, the comparison data flow is similar to that of the image data shift register described above.
2, the shift operation is performed in synchronization with the comparison data clock, such as CD2 to CD3.

This operation will be described in detail.
0 "and the first pulse of the comparison data clock is applied to the CD of the image comparison data shift register.
1_Q changes from "255" to "0", and the shift operation is performed so that the image comparison data shift register CD2_Q changes from "255" to "0" by the second pulse of the comparison data clock. Therefore, CD1279_Q and CD
The reason why 1280_Q changes from "255" to "0" is
The 1279th pulse of the comparison data clock,
This is the 1280th pulse. The outputs Q of the image comparison data shift registers CD1 to CD64 are given to the input terminals P of the comparators C1 to C1280.

Next, the latch signal B will be described.
As shown in FIG. 3, the latch signal B which becomes "H" only at the first pulse of the comparison data clock of the first line is supplied from the external head control circuit to the LATCH Bin of the thermal head.
Shift registers SL1 to SL
Latch circuit connected to the output Q of 1280 and C of the second image data latch circuits L1B to L1280B
The signal at the LK terminal shifts in synchronization with the comparison data clock as shown in FIG. That is, the second image data latch circuit L1B_CLK is output at the first pulse of this clock, and L2B_CLK is output at the second pulse of this clock. Thereafter, the signals are sequentially output in this manner up to L1280CLK.

From the second image data latch circuit L1B to
The CLK signal of L1280B is firstly set by the latch signal A.
Of the image data held in the image data latch circuits L1A to L1280A of the second image data latch circuit L1.
B to L1280B are signals to be held. The operation at the end of the first line will be described. The image data of L1280A is held in L1280B by the 1280th pulse of the comparison data clock.

By this operation, the image data of the first line are all second image data latch circuits L1B to L1280.
Since the holding is completed in B, the image data shift register SR1 to the image data shift register SR12
The image data of the second line which has been transferred to 80 is transferred to the first image data latch circuits L1A to L1 by the latch signal A.
Hold at 280A. Furthermore, the comparison data is 128
After the clock of the 0th pulse, it is changed to "0" and is incremented from "0" to "255" as in the first line. Also, the clock of L1280B is output from the LATCH Bout terminal of the thermal head,
By applying this signal to the LATCH Bin terminal, the second image data latch circuit L1B_CLK can be activated in synchronization with the first pulse of the comparison data clock on the second line.

FIG. 4 is a timing chart for explaining the energizing operation to the heat generating resistor, and the time zone is the same as in FIG. 3 and is the beginning part of the first line and the second line. In the figure, L1B_Q to L1280B_Q are L1B in FIG.
_CLK to L1280B_CLK represent the image data latched. The second image data latch circuit L
The outputs Q of 1B to L1280B are the comparators C1 to C1.
It is connected to the input terminal Q of 280. As described above, the image comparison data from the output terminals Q of the image comparison data shift registers CD1 to CD1280 is applied to the other input terminal Q of this comparator, and when the comparator is Q> P, that is, When the image data is larger than the comparison data, the output terminal O becomes "H".
When the output terminal O is "H" and the output enable terminal OE of the driver IC is also "H", the corresponding energization control circuit DRn is turned on to energize the heating resistor. Is done.

Taking the heating resistor R1 as an example, the comparison data is "0" from the output Q of the CD1 and the image data is the second image data by the first pulse of the comparison data clock on the first line. Since "1" is given from the output Q of the latch circuit L1B and the image data is larger than the comparison data, I
Energization starts as indicated by r1. Also, the comparison data is "1" at the 85th pulse of the comparison data clock.
Then, it becomes equal to the image data, and the energization to the heating resistor R1 is completed. Similarly for the second line, "0" is added to the comparison data by the first pulse of the comparison data clock.
"10" is given to the image data, and energization to the heating resistor R1 is started.

As described above, by using the present driver IC, the energization start time to the plurality of heating resistors provided in parallel on the line type thermal head is changed from the resistor located at the end to the other. It is possible to delay the energization start time for each of the resistors located at the end.

In the drive circuit of the present invention, the heating resistor is used as the recording element in the above embodiment, but the present invention is not limited to this, and it is possible to record image data having gradation by controlling the energization time. It is applicable to recording elements.

[0033]

According to the present invention, since it has a function of holding image data having a gradation consisting of a plurality of bits per pixel and shifting the image comparison data transferred from the outside, It is possible to shorten the data transfer time, reduce the load on the circuit that controls the printing elements, and further delay the energization start time of multiple printing elements connected to the drive circuit individually. It is possible to obtain an image with no division density unevenness while reducing power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a thermal head equipped with an embodiment of a drive circuit of the present invention.

FIG. 2 is a schematic diagram when the drive circuit of FIG. 1 is mounted on a thermal head which is an example of a recording head of the present invention.

FIG. 3 is a timing chart showing the operation of the drive circuit of FIG. 1 at the start of energization for one line.

4 is a timing chart showing the operation of the drive circuit of FIG. 1 at the end of energization for one line.

FIG. 5 is a table showing the relationship between the number of gradations and the number of energizing pulses in a sublimation printer.

FIG. 6 is a schematic diagram of a thermal head equipped with a conventional drive circuit (driver IC).

FIG. 7 is a timing chart for explaining a conventional thermal head driving method.

FIG. 8 is a timing chart for explaining a conventional thermal head driving method.

FIG. 9 is a timing chart in the case of using a conventional drive circuit (driver IC) to make the energization start time of each heating resistor different.

[Explanation of symbols]

 C1 to 64: Comparator CD1 to 64: Shift register for image comparison data L1A to 64A: First image data latch circuit L1B to 64B: Second image data latch circuit R1 to 1280: Heating resistor SL1 to 64: 1 bit Shift registers SR1 to 64: shift registers for image data

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Ma ▲ Fuchi ▼ Koji 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A drive circuit for controlling a printing operation for a plurality of printing elements, comprising a plurality of bit parallel shift registers for taking in image data having a gradation composed of a plurality of bits, and the shift register. A first latch circuit for holding the image data in the subsequent stage, another latch circuit in the second stage for the latch circuit, and a 1-bit shift for instructing the second latch circuit to perform a latch operation. A register, a parallel shift register of a plurality of bits for fetching comparison data to be compared with the image data held in the second latch circuit, image data held in each of the second latch circuits, and A comparator for comparing the comparison data with each other, and the comparator for fetching the comparison data into the comparator and the shift operation and the latch instruction to the second latch circuit are compared with each other. A recording element drive circuit, which is executed in synchronization with a data transfer clock, is compared by the comparator, and controls the drive of each recording element based on the comparison result. 2. A recording head comprising: the drive circuit according to claim 1; and a plurality of recording element groups divided into blocks for each drive circuit unit.