JPH086540A - Clock reproduction method of video signal for display device having pixels - Google Patents

Abstract

(57) [Summary] [Purpose] Displays the dot clock with the same phase as the dot clock used on the video signal creation side, even when the LCD panel or plasma display of personal computers and workstations is installed separately from the control unit. Provided is a dot clock reproduction method in which each dot of a video signal is surely associated with each pixel of a display device by accurately reproducing the dot on the device side. In a display video signal interface 3 between a control unit 1 having pixels and a display device 2, the control unit 1 creates a video signal, and a video signal creating means 1A.
And a dot clock generating means 1B for generating a clock signal that is the same as the dot clock used for generating the video signal or that is a clock signal divided by n (n is an arbitrary natural number) of the dot clock. It is configured to include means for reproducing the dot clock from a clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot clock reproducing system for reliably capturing display data even when a display device having pixels is installed separately from a control unit. For details, when using a liquid crystal panel or plasma panel as a display device of a personal computer and a workstation separately from the control unit, in order to make each dot of the video signal correspond to each pixel of the display device, the video signal creation side A method for accurately reproducing a dot clock having the same phase as the used dot clock on the display device side.

[0002]

2. Description of the Related Art In recent years, personal computers and workstations have become very popular. There are various known display devices such as personal computers and their installation methods. Generally, a CRT is used for these display devices, and a separate control unit and display device are used. Are connected by a CRT video signal interface. In this CRT, the positions of the dots to be displayed are not predetermined, so the dot clock used by the control unit, that is, the side that creates the video signal must be sent to the display device through the video signal interface. Absent. However, if a liquid crystal panel or a plasma display is used instead of this CRT display, it is necessary to make the dots of the video signal correspond exactly to each pixel dot of the display device. Therefore, in a control unit such as a personal computer and a workstation. It is necessary to reproduce a dot clock having the same phase as the used dot clock on the display device side. As a technique for this purpose, the technique described in Japanese Patent Application Laid-Open No. 4-113391 is conventionally known. The description of this publication uses a video signal interface consisting of RGB (red, green, blue) signals as video signals and a synchronization signal. Next, referring to FIG. The outline will be described.

In the method shown in FIG. 10, the video signal and the synchronizing signal generated by the video signal generating means in the control unit 41 are displayed on the display device 42 as the video signal interface 4.
3 is sent as a composite sync signal. On the other hand, in the display device 42, there is a large amount of PLL (phase-locked loop).
44 and the video signal sampling unit 45 further include the PLL 4
4, a phase comparator 44a, a low-pass filter 44b,
Voltage-controlled oscillator 44c, internal horizontal synchronization signal generator 44d
Also, a counter 44e is provided, and the display dot clock generated through the PLL 44 is fed back to newly generate an internal horizontal synchronizing signal. In this way, the composite synchronizing signal sent from the control unit 41 is synchronously separated in the PLL 44, and the rising or falling of the horizontal synchronizing signal (separate horizontal synchronizing signal) is compared with the internal horizontal synchronizing signal and the phase comparator. The phases are compared at 44a, and the period of the display dot clock is continuously adjusted. Using this display dot clock, one dot of the video signal corresponds to one dot of the liquid crystal panel or the plasma display.

[0004]

However, when the dot clock is reproduced from the horizontal synchronizing signal in this way,
Since the phase comparison in the PLL loop can be performed only once in one horizontal cycle, there are problems that it takes a long time for the PLL loop to stabilize, and that the reproduced clock has a lot of jitter.

The present invention has been made to solve this problem, and was used on the video signal producing side even when the liquid crystal panel or plasma display of personal computers and workstations is installed separately from the control unit. A dot clock reproduction system for a video signal for a display device in which a dot clock having the same phase as the dot clock is accurately reproduced on the display device side so that each dot of the video signal corresponds to each pixel of the display device is provided. To aim.

[0006]

In order to achieve the above-mentioned object, a clock reproduction system of a video signal for a display device having a pixel according to the present invention is controlled as shown in the principle diagram of FIG. In the display video signal interface (3) between the section (1) and the display device (2) having pixels, the control section (1) creates a video signal by a video signal creating means (1A) and the video. The display device (2) has a clock signal generating means (1B) for generating a clock signal that is the same as the dot clock used for signal generation or that is a frequency division of the dot clock by n (n is any natural number). It comprises means for reproducing the dot clock from the clock signal.

Here, the clock signal may be a signal added to a video signal interface (3) connecting the control unit (1) and the display device (2), or the clock signal of the video signal. It is superposed on a blanking portion, superposed on a part or all of the video signal at a frequency higher than a required band of the video signal, or at an operation signal level of a TTL circuit included in the display device (2). It may be superposed on a part or the whole of the synchronization signal generated by the control unit (1) at a low level which is not sufficient.

In addition to the above, the display device (2)
As a dot clock reproducing means (4) for reproducing the dot clock, an oscillator (4A) for generating a signal having the same frequency as the dot clock, and the oscillator (4A)
(4B) for delaying the output of each of the oscillators by a minute time interval to obtain an oscillator output of a plurality of different phases, and comparing the clock signal with each of the oscillator outputs of the plurality of different phases to obtain the clock signal. It may have a comparison and selection means (4C) for selecting oscillator outputs of the same phase or the closest phase. With this configuration, the optimum phase is selected for each horizontal period, and the dot clock for reproduction can be easily obtained.

[0009]

In the present invention, the video signal and the clock signal generated by the control unit (1) are typically sent to the display device (2) through the video signal interface (3).
This clock signal is created as the same as the dot clock used for creating the video signal or as a frequency divided by n (n is an arbitrary natural number) of the dot clock. Also,
The video signal sampling unit provided in the display device (2) allocates the video signal to individual display pixels based on the dot clock. This dot clock is output from the dot clock reproducing means (4), but its cycle and phase are controlled by the clock signal sent from the control unit (1) through the video signal interface (3). It is what is done.

With such a configuration of the present invention, the dot clock having the same phase as the dot clock used on the control section (1) side is accurately reproduced on the display device (2) side to ensure each dot of the video signal. Can correspond to each pixel of the display device.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A concrete embodiment of a clock reproduction system for a video signal for a display device having pixels according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 2 shows an embodiment of the present invention. In the present embodiment, the control unit 21 creates a clock signal that is the same as the display dot clock or is divided by n (n is a natural number), and the dot clock reproduction means 24 in the display device 22 keeps the same signal through the video signal interface 23. Transmitted in the form. Here, the dot clock reproduction means 24 includes a phase comparator 26, a low-pass filter 27,
A PLL including a voltage controlled oscillator 28, which reproduces a dot clock from the clock signal transmitted from the control unit 21 and sends the dot clock to the video signal sampling unit 25.

(Second Embodiment) FIG. 3 shows another embodiment of the present invention. In FIG. 3, parts that are the same as or correspond to those in FIG. 2 are given the same numbers. In this embodiment, the clock signal generated by the control unit 21 is superposed on the blanking portion of the video signal, transmitted to the display device 22 by the video signal interface, and then extracted from the video signal by using the synchronizing signal. Be done. After that, it is sent to the PLL 24 and used for dot clock reproduction as in the first embodiment.

(Third Embodiment) FIG. 4 shows another embodiment of the present invention. In FIG. 4, parts that are the same as or correspond to those in FIGS. 2 and 3 are given the same numbers. In the present embodiment, the clock signal generated by the control unit 21 has a frequency equal to or higher than the required band of the video signal, and is superimposed on a part or the whole of the video signal to display the display device 22.
Be transmitted to. A low-pass filter 29 and a high-pass filter 30 are provided in the display device 22, and each of these filters 29 and 30 separates and extracts a video signal and a clock signal. The extracted video signal is directly converted into a dot clock by the PLL 24, and the clock signal is sent to the video signal sampling unit 25.

(Fourth Embodiment) FIG. 5 shows another embodiment of the present invention. In FIG. 5, parts that are the same as or correspond to those in FIGS. 2 to 4 are given the same numbers.
In this embodiment, the clock signal generated by the control unit 21 is superposed on a part or all of the synchronization signal generated by the control unit 21 at a low level that is lower than the operation signal level of the TTL circuit included in the display device 22. Are transmitted to the display device 22. On the side of the display device 22, the clock signal is taken out by using the comparator 31, and the dot clock is reproduced as in the first to third embodiments.

(Fifth Embodiment) FIG. 6 shows another embodiment of the present invention. In FIG. 6, the same numbers are assigned to the same or corresponding parts as in FIGS.
In this embodiment, an oscillator 32 and a delay line 33 having the same frequency as the dot clock are built in the display device 22, and the signal generated by the oscillator 32 is delayed by the delay line 33 by a minute time interval and the dot clock is delayed. A plurality of signals having the same frequency are generated with different phases and input to the buffer 34. Further, similarly to any of the first to fifth embodiments, the clock signal created in the control unit 21 is reproduced in the display device 22 and the signal of the same phase or the closest phase is selected. The comparison / selection means 35 for selecting an oscillator output having the same phase as or the closest phase to this clock signal is a flip-flop 35a and a register 35.
b, a priority encoder 35c, a multiplexer 35d, and the like. Note that the portion indicated by a in FIG. 6 is the reproduction portion of the clock signal created in the control unit 21, but the transmission method from the generation portion in the control unit 21 to the a is shown in FIGS. Any of the methods described in 1. may be used. In each of these FIGS. 2 to 5, the position of the reproduction portion a of the corresponding clock signal is described. On the other hand, FIG. 7 shows an example of the timing of comparing the respective phases of the signals DL1 to 5 delayed from the oscillator output with the synchronization signal. At this time, the signal encoded based on the data for the priority encoder 35c is the multiplexer 3
FIG. 8 shows a correspondence example of data when any one of DL1 to DL4 is selected according to the clock signal input to 5d and reproduced. Further, the signal DL5 may be directly connected to the register 35b in place of the circuit 35e that guides the phase comparison gate. In this case, the respective phases of the signals DL1 to 5 obtained by delaying the oscillator output are, for example, at the timing of FIG. , And the dot clock, any one of DL1 to DL4 is selected depending on the correspondence of the data as shown in FIG. Further, as the signal for giving the data latch timing of the flip-flop 35a, the synchronizing signal or the clock signal is given from the control unit 21 according to the embodiment.

In each of the above first to fifth embodiments, the control unit 21, the display device 22, the video signal interface 23, the PLL 24, and the video signal sampling unit 2 are used.
Reference numeral 5 respectively corresponds to the control unit (1), the display device (2), the video signal interface (3), the dot clock reproducing means (4) and the video signal sampling unit (5) in the present invention.

[0018]

As described above, according to the present invention, it is possible to compare the phases of video signals in the display device over the entire horizontal period. Further, this phase comparison may be performed a plurality of times within one horizontal period, so that a PLL loop incorporated in a display device having a pixel such as a liquid crystal panel or a plasma display can be pulled in early and a reproduction clock signal can be stabilized. The low jitter is achieved and the display quality is greatly improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of an invention showing a principle configuration of a clock reproduction system of a video signal for a display device having a pixel according to the present invention.

FIG. 2 is a configuration diagram of a main part of a clock reproduction system of a video signal for a display device having pixels according to a first embodiment of the present invention.

FIG. 3 is a configuration diagram of a main part of a clock reproduction system of a video signal for a display device having pixels according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a main part of a clock reproduction system of a video signal for a display device having pixels according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram of a main part of a clock reproduction system of a video signal for a display device having pixels according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram of a main part of a clock reproduction system of a video signal for a display device having pixels according to a fifth embodiment of the present invention.

FIG. 7 compares the phase of a synchronizing signal and the output of an oscillator provided with a plurality of delayed outputs in a clock reproduction system of a video signal for a display device having pixels according to a fifth embodiment of the present invention. It is a timing example.

FIG. 8 is a correspondence diagram between encoded data in a multiplexer and a reproduced clock signal in a clock reproduction system of a video signal for a display device having pixels according to a fifth embodiment of the present invention.

FIG. 9 compares the phases of a dot clock and an oscillator output provided with a plurality of delay outputs in a clock reproduction system of a video signal for a display device having pixels according to a fifth embodiment of the present invention. It is a timing example.

FIG. 10 is a configuration diagram of a main part of a conventional video signal clock reproduction system.

[Explanation of symbols]

1, 21, 41 Control unit 2, 22, 42 Display device 3, 23, 43 Video signal interface 4, 24, 44 Dot clock reproducing means (PLL (pha
se-locked loop)) 5, 25, 45 Video signal sampling unit 26 Phase comparator 27, 29 Low pass filter (LPF) 28 Voltage controlled oscillator (VCO) 30 High pass filter (HPF) 31 Comparator 32 Oscillator 33 Delay line 34 Buffer 35 Comparison / selection means for selecting an oscillator output in phase with or closest to the clock signal

Claims (6)

[Claims] 1. In a display video signal interface (3) between a control unit (1) and a display device (2) having pixels, the control unit (1) creates a video signal by a video signal generating means. 1A) and a clock signal creating means (1B) for creating a clock signal that is the same as the dot clock used to create the video signal or that is divided by n (n is any natural number) of the dot clock. A clock reproduction system for a video signal, wherein the device (2) comprises a clock reproduction means (4) for reproducing the dot clock from the clock signal. 2. The clock signal is supplied to the control unit (1).
The video signal clock recovery system according to claim 1, wherein the clock signal is a signal added to a video signal interface (3) for coupling the display device (2) with the display device (2). 3. The clock reproduction method for a video signal according to claim 1, wherein the clock signal is superimposed on a blanking portion of the video signal. 4. The clock signal reproducing method according to claim 1, wherein the clock signal is superimposed on a part or all of the video signal at a frequency equal to or higher than a required band of the video signal. 5. The clock signal is superposed on a part or all of a synchronization signal generated by the control unit (1) at a low level which is lower than an operation signal level of a TTL circuit included in the display device (2). A clock signal reproducing method for a video signal according to claim 1. 6. An oscillator (4A) for causing the display device (2) to generate a signal having the same frequency as the dot clock as dot clock reproduction means (4) for reproducing the dot clock, and the oscillator (4A). A delay means (4B) for delaying the output by a minute time interval to obtain a plurality of oscillator outputs of different phases, and comparing the clock signal with each of the oscillator outputs of the plurality of different phases, and comparing the same with the clock signal. A clock recovery system for a video signal according to claim 1, further comprising a comparison / selection means (4C) for selecting an oscillator output having a phase or a phase closest thereto.