JPH0865754A - Amplifier circuit for single-acting input signal - Google Patents

Amplifier circuit for single-acting input signal

Info

Publication number
JPH0865754A
JPH0865754A JP19168294A JP19168294A JPH0865754A JP H0865754 A JPH0865754 A JP H0865754A JP 19168294 A JP19168294 A JP 19168294A JP 19168294 A JP19168294 A JP 19168294A JP H0865754 A JPH0865754 A JP H0865754A
Authority
JP
Japan
Prior art keywords
logic
circuit
signal
input
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP19168294A
Other languages
Japanese (ja)
Inventor
Masato Matsushita
真人 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP19168294A priority Critical patent/JPH0865754A/en
Publication of JPH0865754A publication Critical patent/JPH0865754A/en
Withdrawn legal-status Critical Current

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  • Selective Calling Equipment (AREA)

Abstract

PURPOSE: To provide an amplifier circuit unifying signal amplification and logic conversion and with inexpensive constitution. CONSTITUTION: Photocouplers 21 to 2n are turned on/off corresponding to a no-voltage on/off signal inputted from the outside to input terminals 11 to 1n, and a logic signal based on a DC of 5V is outputted to an internal circuit. On the other hand, the no-voltage on/off signal is inputted by branching to an OR logic part 7 via diodes 5 to 5n for signal current sneak prevention. The OR logic part 7 generates plural patterns of OR logic arbitrarily by the strap wiring of a circuit, and introduces the output to an AND logic part 10 via MOS relays 81 to 8n. The AND logic part 10 generates plural patterns of AND logic arbitrarily by the strap wiring. and outputs them to an external circuit via output terminals 111 to 11n.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、遠方監視制御装置のよ
うな電気制御回路を有する装置に用いられる単動入力信
号用増幅回路に関し、特に外部から取り込んだ単動入力
信号を制御監視用の内部回路及び他の外部回路に転送す
る機能と単動入力信号の増幅論理変換機能とを併有する
単動入力信号用増幅回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-acting input signal amplifying circuit used in a device having an electric control circuit such as a remote monitoring control device, and more particularly to a single-acting input signal for controlling and monitoring a single-acting input signal. The present invention relates to a single-acting input signal amplifier circuit having both a function of transferring to an internal circuit and another external circuit and a function of amplifying and converting a single-acting input signal.

【0002】[0002]

【従来の技術】電気制御回路を有する遠方監視制御装置
において、外部から取り込んだ単動入力信号を制御監視
用の内部回路や他の外部回路に導く際に、単動入力信号
の増幅論理変換を要する場合がある。従来のこの種の装
置では、増幅論理変換を行うための信号増幅部と論理変
換部は各々別々のユニットに分けて構成されており、論
理変換自体も殆ど固定的で、容易に変更できる構成にな
っていない(特開平2−70243号公報参照)。
2. Description of the Related Art In a remote monitoring control device having an electric control circuit, when a single-action input signal fetched from the outside is guided to an internal circuit for control and monitoring or another external circuit, amplification and logical conversion of the single-action input signal is performed. It may cost. In the conventional device of this type, the signal amplification unit for performing the amplification logic conversion and the logic conversion unit are configured by being divided into separate units, respectively, and the logic conversion itself is almost fixed and can be easily changed. However, this is not the case (see JP-A-2-70243).

【0003】[0003]

【発明が解決しようとする課題】上述のように、従来は
信号増幅部と論理変換部が別々のユニットにて構成され
ているため、遠方監視制御装置等における実装スペース
やコストの節約が図れず、しかも論理変換が固定的であ
ることからその都度論理の組み替えが必要となり、汎用
性に欠ける問題があった。
As described above, since the signal amplifying section and the logic converting section are conventionally constituted by separate units, it is not possible to save the mounting space and cost in the distant monitoring control device or the like. Moreover, since the logic conversion is fixed, it is necessary to rearrange the logic each time, and there is a problem of lacking versatility.

【0004】本発明は、かかる問題点に鑑み、信号増幅
及び論理変換を統合し、且つ論理変換が容易な構成の単
動入力信号用増幅回路を提供することにある。
In view of the above problems, the present invention provides a single-acting input signal amplifying circuit that integrates signal amplification and logic conversion and is easy to perform logic conversion.

【0005】[0005]

【課題を解決するための手段】本発明の単動入力信号用
増幅回路は、n(自然数)個の単動入力信号を並列に取
り込む入力端子と、入力端子から取り込んだ前記単動入
力信号を各々電気的にアイソレーションして内部回路に
導くn個のアイソレーション素子と、入力端子から取り
込んだ単動入力信号を各々分岐入力してm(≦n)個の
第1の論理信号を生成し、これを並列に出力する第1の
論理回路と、この第1の論理回路の出力信号を各々電気
的にアイソレーションして並列出力する半導体リレー回
路と、この半導体リレー回路の出力信号に基づいて前記
第1の論理信号と異なる論理のk(≦m)個の第2の論
理信号を生成し、これを並列出力する第2の論理回路
と、この第2の論理回路の出力信号を外部回路に並列出
力する出力端子とを有し、信号増幅と論理変換機能とを
統合したことを特徴とする。
A single-acting input signal amplifying circuit according to the present invention has an input terminal for taking n (natural number) single-acting input signals in parallel and the single-acting input signal taken from the input terminals. The n isolation elements that are electrically isolated from each other and lead to the internal circuit, and the single-action input signals input from the input terminals are branched and input to generate m (≦ n) first logic signals. A first logic circuit that outputs the signals in parallel, a semiconductor relay circuit that electrically isolates the output signals of the first logic circuit and outputs the signals in parallel, and based on the output signal of the semiconductor relay circuit A second logic circuit that generates k (≦ m) second logic signals having a logic different from that of the first logic signal and outputs the second logic signals in parallel, and an output signal of the second logic circuit as an external circuit. Output terminals for parallel output to And, characterized in that the integration of the signal amplification and the logic conversion function.

【0006】上記構成において、前記半導体リレー回路
は、例えば前記第1の論理信号を入力してこれを選択的
に出力する複数のMOS(metal oxide semiconductor
)リーを含んで成るものであり、これにより、簡易に
信号増幅を行うことが可能となる。また、前記第1の論
理回路及び第2の論理回路は、前段回路から導かれた信
号をストラップ配線により任意に組み合わせて論理信号
を生成出力する構成であり、これにより論理変換を容易
に変更することが可能となる。
In the above structure, the semiconductor relay circuit receives, for example, the first logic signal and selectively outputs a plurality of MOS (metal oxide semiconductor).
), The signal amplification can be easily performed. Further, the first logic circuit and the second logic circuit are configured to generate and output a logic signal by arbitrarily combining the signals introduced from the previous stage circuit by the strap wiring, thereby easily changing the logic conversion. It becomes possible.

【0007】[0007]

【実施例】以下、図面を参照して本発明の実施例を説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0008】図1は、本発明の一実施例に係る単動入力
信号用増幅回路の構成図であり、アイソレーション素子
としてフォトカプラを用いるとともに、半導体リレー回
路をMOSリレーを含んで構成した場合の例を示す。
FIG. 1 is a block diagram of an amplifier circuit for a single acting input signal according to an embodiment of the present invention. In the case where a photocoupler is used as an isolation element and a semiconductor relay circuit includes a MOS relay. For example:

【0009】図1において、11〜1nは入力端子、2
1〜2nはフォトカプラ、31〜3nはフォトカプラ入
力電流制限用抵抗器、41〜4nはフォトカプラ出力プ
ルアップ用抵抗器、51〜5nは信号電流回り込み防止
用ダイオード、6は外部出力部、7はOR論理部、81
〜8nはMOSリレー、91〜9nはMOSリレー入力
電流制限用抵抗器、10はAND論理部、111〜11
nは出力端子である。
In FIG. 1, 11 to 1n are input terminals and 2
1 to 2n are photocouplers, 31 to 3n are photocoupler input current limiting resistors, 41 to 4n are photocoupler output pull-up resistors, 51 to 5n are signal current sneak prevention diodes, and 6 is an external output unit. 7 is an OR logic part, 81
8n is a MOS relay, 91-9n is a MOS relay input current limiting resistor, 10 is an AND logic unit, 111-11
n is an output terminal.

【0010】n個の入力端子11〜1nには、各々フォ
トカプラ21〜2n、フォトカプラ入力電流制限用抵抗
器31〜3nを介して第1の直流電圧(DC24V)が
接続されており、無電圧ON信号入力時に当該入力端子
につながるフォトカプラがONとなってその二次側(出
力側)が導通し、他方、無電圧OFF信号入力時に当該
フォトカプラがOFFとなってフォトカプラが遮断する
ようになっている。
A first DC voltage (DC24V) is connected to the n input terminals 11 to 1n via photocouplers 21 to 2n and photocoupler input current limiting resistors 31 to 3n, respectively. When a voltage ON signal is input, the photocoupler connected to the input terminal is ON, and the secondary side (output side) is conductive, while when a no-voltage OFF signal is input, the photocoupler is OFF and the photocoupler is cut off. It is like this.

【0011】フォトカプラ21〜2nの二次側には、各
々フォトカプラ出力プルアップ用抵抗器41〜4nを介
して第2の直流電圧(DC5V)が接続されており、二
次側が導通状態のときに論理”1”、遮断状態のときに
論理”0”の信号が内部回路に導かれるようになってい
る。
A second DC voltage (DC5V) is connected to the secondary sides of the photocouplers 21 to 2n via photocoupler output pull-up resistors 41 to 4n, respectively, and the secondary sides are in a conductive state. A signal of logic "1" is sometimes led to the internal circuit when it is in the cutoff state.

【0012】このような構成の単動入力信号増幅回路で
は、外部から入力端子11〜1nに並列入力された無電
圧ON/OFF信号(単動入力信号)により、該当する
フォトカプラ21〜2nがON/OFFし、これら単動
入力信号に対応する論理信号が監視用内部回路へ導かれ
る。これら単動入力信号は、信号電流回り込み防止用ダ
イオード51〜5nを介して外部出力部6にも分岐入力
されており、ここで増幅論理変換されて出力端子111
〜11nに出力される。
In the single-acting input signal amplifying circuit having such a configuration, the corresponding photocouplers 21-2n are driven by the non-voltage ON / OFF signal (single-acting input signal) externally input in parallel to the input terminals 11-1n. It is turned on / off and a logic signal corresponding to these single-action input signals is introduced to the monitoring internal circuit. These single-acting input signals are also branched and input to the external output section 6 via the signal current sneak-preventing diodes 51 to 5n, where they are amplified and logically converted and output terminal 111.
To 11n.

【0013】外部出力部6の初段のOR論理部7は、回
路のストラップ配線により任意に複数のOR論理を生成
できるもので、その出力端が各々MOSリレー81〜8
nの一次側の一端に接続されている。図示の破線は、O
R論理の一例を示すものである。各MOSリレー81〜
8nの一次側の他端には前述の第1の直流電圧が接続さ
れており、無電圧信号がONとなる入力端子につながる
OR論理出力と導通するMOSリレーのみがONして論
理”1”の信号を後段のAND論理部10に出力するよ
うになっている。
The first stage OR logic unit 7 of the external output unit 6 is capable of arbitrarily generating a plurality of OR logics by the strap wiring of the circuit, and its output terminals are MOS relays 81 to 8 respectively.
n is connected to one end on the primary side. The broken line in the figure is O
It is an example of R logic. Each MOS relay 81 ~
The above-mentioned first DC voltage is connected to the other end of the primary side of 8n, and only the MOS relay that is in conduction with the OR logic output connected to the input terminal where the no-voltage signal is ON is turned on and the logic "1" is output. Is output to the AND logic unit 10 in the subsequent stage.

【0014】AND論理部10は、回路のストラップ配
線により任意に複数のAND論理を生成できるものであ
る。図示の破線は、AND論理の一例を示すもので、こ
の論理信号が出力端子111〜11nを介して外部回路
に導かれる。
The AND logic unit 10 is capable of arbitrarily generating a plurality of AND logics by strap wiring of the circuit. The broken line in the figure shows an example of AND logic, and this logic signal is guided to the external circuit via the output terminals 111 to 11n.

【0015】このように、本実施例の単動入力信号用増
幅回路は、外部より入力された無電圧ON/0FF信号
を、内部回路用と外部回路用にそれぞれ電気的にアイソ
レーションされた信号増幅を行うと共に、回路のストラ
ップ配線により容易に変更可能なOR論理部7とAND
論理部10を有することにより、信号増幅及び論理変換
機能を統合した安価な回路を実現することができる。
As described above, in the single-action input signal amplifier circuit of this embodiment, the non-voltage ON / 0FF signal input from the outside is electrically isolated for the internal circuit and the external circuit. Amplifies and AND with AND logic unit 7 that can be easily changed by strap wiring of the circuit
By having the logic unit 10, it is possible to realize an inexpensive circuit that integrates signal amplification and logic conversion functions.

【0016】なお、本実施例では、MOSリレー81〜
8nの前段にOR論理部7を配し、後段にAND論理部
10を配した例について説明したが、これら論理部を逆
にすることもできる。また、本実施例では、入力端子1
1〜1n、フォトカプラ21〜2n、MOSリレー81
〜8n、出力端子111〜11nをそれぞれn個ずつ配
した例について説明したが、これらの数は必ずしも同一
でなくとも良い。
In this embodiment, the MOS relays 81-
The example in which the OR logic unit 7 is arranged in the previous stage of 8n and the AND logic unit 10 is arranged in the latter stage has been described, but these logic units can be reversed. Further, in this embodiment, the input terminal 1
1-1n, photocouplers 21-2n, MOS relay 81
.About.8n and n output terminals 111 to 11n have been described, but the numbers are not necessarily the same.

【0017】[0017]

【発明の効果】以上の説明から明かなように、本発明の
単動入力信号用増幅回路は、MOSリレーのような半導
体リレーを用いて外部入力信号を内部回路用と外部回路
用にそれぞれ電気的にアイソレーションされた信号増幅
を行うと共に、回路のストラップ配線により容易に変更
可能な第1の論理部と第2の論理部を有するので、信号
増幅及び論理変換機能が統合され、遠方監視制御装置等
の実装スペースの有効活用が図れる効果がある。また、
論理変換を容易に変更できるため、汎用性に富む単動信
号用増幅回路を実現することができる。
As is apparent from the above description, the single-acting input signal amplifier circuit of the present invention uses a semiconductor relay such as a MOS relay to electrically supply an external input signal to an internal circuit and an external circuit, respectively. Has a first logic part and a second logic part that can be easily changed by strap wiring of the circuit, as well as amplifying the isolated signal, so that the signal amplification and logic conversion functions are integrated and remote monitoring control is performed. This has the effect of effectively utilizing the mounting space for devices and the like. Also,
Since the logic conversion can be changed easily, it is possible to realize a versatile single-acting signal amplifier circuit.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る単動入力信号用増幅回
路の構成図である。
FIG. 1 is a configuration diagram of a single-action input signal amplifier circuit according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11〜1n 入力端子 21〜2n フォトカプラ 31〜3n フォトカプラ入力電流制限抵抗器 41〜4n フォトカプラ出力電流制限抵抗器 51〜5n 信号電流回り込み防止ダイオード 6 外部出力部 7 OR論理部 81〜8n MOSリレー 91〜9n MOSリレー入力電流制限抵抗 10 AND論理部 111〜11n 出力端子 11-1n Input terminal 21-2n Photocoupler 31-3n Photocoupler input current limiting resistor 41-4n Photocoupler output current limiting resistor 51-5n Signal current sneak prevention diode 6 External output section 7 OR logic section 81-8n MOS Relay 91-9n MOS relay input current limiting resistor 10 AND logic part 111-11n output terminal

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 n(自然数)個の単動入力信号を並列に
取り込む入力端子と、入力端子から取り込んだ前記単動
入力信号を各々電気的にアイソレーションして内部回路
に導くn個のアイソレーション素子と、入力端子から取
り込んだ単動入力信号を各々分岐入力してm(≦n)個
の第1の論理信号を生成し、これを並列に出力する第1
の論理回路と、この第1の論理回路の出力信号を各々電
気的にアイソレーションして並列出力する半導体リレー
回路と、この半導体リレー回路の出力信号に基づいて前
記第1の論理信号と異なる論理のk(≦m)個の第2の
論理信号を生成し、これを並列出力する第2の論理回路
と、この第2の論理回路の出力信号を外部回路に並列出
力する出力端子と、を有することを特徴とする単動入力
信号用増幅回路。
1. An input terminal for taking in n (natural number) single-action input signals in parallel, and n isolator for electrically isolating the single-action input signals taken in from the input terminals and leading them to an internal circuit. The first operation signal is generated by branching and inputting the single-action input signal input from the input element and the single-action input signal from the input terminal to generate m (≦ n) first logic signals, and outputting these in parallel.
Logic circuit, a semiconductor relay circuit that electrically isolates the output signals of the first logic circuit and outputs the signals in parallel, and a logic different from the first logic signal based on the output signal of the semiconductor relay circuit. A second logic circuit that generates k (≦ m) second logic signals and outputs the second logic signals in parallel, and an output terminal that outputs the output signal of the second logic circuit to an external circuit in parallel. An amplifier circuit for a single-acting input signal having.
【請求項2】 前記半導体リレー回路は、前記第1の論
理信号を入力してこれを選択的に出力する複数のMOS
リレーを含んで成ることを特徴とする単動入力信号用増
幅回路。
2. The semiconductor relay circuit comprises a plurality of MOSs for inputting the first logic signal and selectively outputting the first logic signal.
A single-acting input signal amplifier circuit comprising a relay.
【請求項3】 前記第1の論理回路及び第2の論理回路
は、前段回路から導かれた信号をストラップ配線により
任意に組み合わせて論理信号を生成出力する構成である
ことを特徴とする単動入力信号用増幅回路。
3. The single-acting circuit is characterized in that the first logic circuit and the second logic circuit are configured to generate and output a logic signal by arbitrarily combining the signals introduced from the preceding circuit by strap wiring. Amplifier circuit for input signal.
JP19168294A 1994-08-16 1994-08-16 Amplifier circuit for single-acting input signal Withdrawn JPH0865754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19168294A JPH0865754A (en) 1994-08-16 1994-08-16 Amplifier circuit for single-acting input signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19168294A JPH0865754A (en) 1994-08-16 1994-08-16 Amplifier circuit for single-acting input signal

Publications (1)

Publication Number Publication Date
JPH0865754A true JPH0865754A (en) 1996-03-08

Family

ID=16278707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19168294A Withdrawn JPH0865754A (en) 1994-08-16 1994-08-16 Amplifier circuit for single-acting input signal

Country Status (1)

Country Link
JP (1) JPH0865754A (en)

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