JPH087570B2 - Image display device address calculation circuit - Google Patents

Description

The present invention relates to an address calculation circuit used in an image display device that synthesizes and displays image data read from a plurality of display memories of the same type, and relates to each line with a small amount of hardware. The first latch circuit group for latching the display start address information on each display memory and the line provided in association with the display memory for the purpose of calculating the address information of the display start position of A first multiplexer that receives a line start register group including a start register, a holding value of the first latch circuit group, and a holding value of the line start register group, and selectively outputs one of the input values. And a second latch circuit group for latching line memory width information on each display memory, and holding of the second latch circuit group A second multiplexer that selectively outputs one of the values and outputs a zero value when neither holding value is selected; an adder that adds the output values of the first and second multiplexers; And controlling the second multiplexer to control the adder to calculate the start address information on each line of each display memory, and to store the calculated start address information in the corresponding line start register. And a control circuit for controlling the holding.

[Industrial application field]

The present invention is used in an image display device that synthesizes and displays image data read from a plurality of display memories of the same type, and calculates address information for accessing the display memory. More particularly, the present invention relates to an address calculation circuit of an image display device that enables calculation of address information of a display start position on each line with a small amount of hardware.

In a data processing device such as a personal computer, a process of superposing texts such as characters and graphics such as figures and synthesizing them and outputting them is performed. The image data display function of such a data processing device also improves the practicability of the data processing device.
It is necessary to realize it with a small amount of hardware.

[Conventional technology]

In the image data display function of the conventional data processing device, text is processed so as to generate image data by generating a character font pattern according to a code. Then, by superimposing the text image data thus generated and the graphic image data read from the bitmap memory,
The processing was performed so that the text and graphic were combined.

[Problems to be Solved by the Invention] However, in the method of generating text image data according to a code, there is a problem in that the size and type of characters are limited and a desired composite image cannot be displayed. .

As one method to solve such a problem,
It is conceivable that the text may be expanded in the bitmap memory and the text and the graphic expanded in the bitmap memories may be directly combined. However,
If such a method is simply adopted, the configuration of the address calculation circuit prepared for calculating the address information for accessing the bitmap memory becomes complicated, and the amount of hardware increases. Problems will come up. In other words, if you explain concretely,
The adder for calculating the display start address on each line necessary for accessing the bit map memory is required for the number of bit map memories, so that the amount of hardware increases.

The present invention has been made in view of such circumstances,
An object of the present invention is to provide an address calculation circuit of a new image display device that enables calculation of a display start position on a line required when accessing a plurality of display memories of the same type with a small amount of hardware. It is a thing.

[Means for solving the problem]

 FIG. 1 is a block diagram showing the principle of the present invention.

In the figure, 1 is an address calculation circuit constructed according to the present invention, and 2-i (i = 1 to n) are display memories provided in plural according to the same type. This address calculation circuit 1
Performs processing so that address information for accessing each display memory 2-i is calculated and given to the display memory 2-i.

The address calculation circuit 1 of the present invention is a display start register 10-i (i = 1 to n) for latching display start address information (designating a display start position of a display area) on each display memory 2-i. And a holding value of the first latch circuit group 11 and a holding value of a line start register group 30 which will be described later (specify a display start position on the line of the display area) The first multiplex 12 that selects and outputs any one of the input values by inputting and, and the line memory width information (specifying the display width information of the display area) on each display memory 2-i. A second latch circuit group 14 composed of line memory width mediators 13-i (i = 1 to n) to be latched, and any one of the held values of the second latch circuit group 14 are selected and output. , Select any retention value If not, a second multiplexer 15 that outputs a zero value, an adder 16 that adds and outputs the output value of the first multiplexer 12 and the output value of the second multiplexer 15, and a display memory 2-i compatible Line start register 17-i (i = 1 to
n) and line start register group 30 for holding the start address information on the line calculated as the added value of the adder 16 and the display memory 2-i. A display address counter 18-i (i = 1 to n) which counts up the count value each time the display clock is input from the holding value of i as a starting point and gives it to the corresponding display memory 2-i, First and second multiplexers 12, 15 and line start register 17
-I and the control circuit 19 for controlling the display address counter 18-i. Here, the display start address information set in the display start register 10-i and the line memory width information set in the line memory width register 13-i are set to fixed values or written from the CPU. The value to be set will be set.

[Action]

According to the present invention, the control circuit 19 first controls the first multiplexer 12 to access the i-th line of the n display memories 2-i. By outputting the line start address information held by the first line start register 17-1 and controlling the second multiplexer 15, the second multiplexer 15 controls the first latch of the first latch circuit group 14. The line memory width information held by the line memory width register 13-1 is output. And the first
By sending a latch signal to the th line start register 17-1, the added value of the output values of the first and second multiplexers 12 and 15 obtained by the addition processing of the adder 16 The line start address information latched in the first display address counter 18-1 is sent to the first display address counter 18-1, and the line start address information latched in the first line start register 17-1 is transferred to the first display address counter 18-1. The process of making the second display address counter 18-1 latch is executed.

Here, in this process, when the i-th line is the display start position of the display area, the control circuit 19
By controlling the multiplexer 12 of the first multiplexer 12, the display start address information held in the first display start register 10-1 of the first latch circuit group 11 is output from the first multiplexer 12 and the second multiplexer 15 The control is performed so that the second multiplexer 15 outputs a zero value.

Thereafter, the control circuit 19 executes the series of control processes in correspondence with the n line memory width registers 13-i, and thereby the n display address counters 18 are provided.
The process of setting the line start address information of the i-th line of the display area to be combined in -i is executed. In this way, when the line start address information is set, each display address counter 18-i sequentially counts up the count value in accordance with the input display clock, so that the display memory 2-i stores it. On the other hand, processing is performed so as to give address information for accessing the i-th line of the display area. Then, when the display address counter 18-i completes the address generation processing of the i-th line, the control circuit 19 causes the first and second multiplexers.
By controlling 12 and 15, the processing is started so as to enter the processing of the next (i + 1) th line.

As described above, according to the present invention, the address information necessary for accessing the plurality of display memories 2-i can be calculated with one adder 16.

〔Example〕

 Hereinafter, the present invention will be described in detail according to examples.

FIG. 2 shows an embodiment of the present invention. First in the figure
The same components as those described in the figures are denoted by the same symbols. Here, in this embodiment, the display memory 2-
Since two bitmap memory for text and bitmap memory for graphic are assumed as i, display start register 10-i, line memory width register 13-i, line start register 17-i and display address. Two counters 18-i are also provided.

Reference numeral 3 is a display data synthesizing processing unit, which synthesizes image data read from the two display memories 2-i and outputs the synthesized image data to the display device. Reference numeral 20 is a common line start register which is used by the adder 16. A display clock generation circuit 21 temporarily latches the addition result. The display clock generation circuit 21 is controlled by the control circuit 19 to generate a predetermined number of display clocks and give them to the display address counter 18-i. Here, in the configuration of this embodiment, the common line start register 20 and the line start register 17-i can be configured by using a D-type flip-flop circuit, but in order to reduce the number of gates. It is preferable to use a latch element for the above. Although omitted in FIG. 1, signals such as a horizontal synchronizing signal, a display line signal, and a timing generation clock are input to the control circuit 19 in order to execute control processing.

Next, with reference to the time chart shown in FIG. 3, the operation processing of the present embodiment configured in this way will be described.

When accessing the first line of the display area, the control circuit 19 first sends the first multiplexer 12 first the first multiplexer 12 as shown in the left column of the time chart of FIG.
The display start address information held by the second display start register 10-1 is controlled to be output to the adder 16, and next, the second display start register 10-2 is displayed.
The display start address information held by is output to the adder 16. On the other hand, the second multiplexer 15 is controlled so as not to select any of the line memory width registers 13-i when the first multiplexer 12 is outputting the display start address information. Is output to the adder 16.

In response to this control processing, the adder 16 sequentially outputs the display start address information designating the display start position of the display area to be combined shown in FIG. The 19 sends the latch signal (LTCOM in FIG. 3) to the common line start register 20 to sequentially latch this display start address information. Then, the control circuit 19 sends a latch signal (fourth signal) to the first line start register 17-1.
By sending LT1) in the figure, the display start address information of the first display start register 10-1 held in the common line start register 20 is latched and the second line start register 17-2
To the common line start register 20 by sending a latch signal (LT2 in FIG. 4) to
The display start address information of the second display start register 10-2 is latched.

In this way, the two line start registers 17-i
After setting the display start address information to,
The control circuit 19 controls the display clock generation circuit 21 so that the display address counter 18-i counts up the count value starting from the display start address information latched in the line start register 17-i. The control is performed so as to generate the address information for accessing the image data of the first line of the display area expanded on the display memory 2-i. -I is accessed according to the generated address information, and performs processing to send the image data to be combined to the display data combination processing unit 3.

When the control circuit 19 finishes generating the address information for accessing the first line of the display area and then accesses the second line of the display area, as shown in the right column of the time chart of FIG. The first multiplexer 12
For the first, the first light start register
The display start address information held in 17-1 is added to the adder 16
The display start address information held in the second line start register 17-2 is controlled to be output to the adder 16. on the other hand,
When the first multiplexer 12 outputs the display start address information of the first line start register 17-1 to the second multiplexer 15, the first line memory width register 13-1 of the first line memory width register 13-1 is output. When the first multiplexer 12 outputs the display start address information of the second line start register 17-2 while controlling the output of the held line memory width information to the adder 16, the second line start register 17-2 Line memory width register
The line memory width information held in 13-2 is controlled to be output to the adder 16.

In response to this control processing, the adder 16 sequentially outputs the line start address information indicating the display start position of the second line of the display area to be combined shown in FIG. 4 as an added value. The control circuit 19 causes the first line start register 17-1 to latch the corresponding line start address information of the second line by performing the same process as the control process of the first line. The second line start register 17-2
The corresponding line start address information of the second line is latched. And the display clock generation circuit
By controlling 21, the address information for accessing the image data of the second line of the display area developed on the display memory 2-i is controlled to be generated.

After that, the control circuit 19 repeats the series of control processes performed on the second and subsequent lines in the display area to expand the lines on the display memory 2-i. Control is performed so as to generate address information for accessing the image data of the second and subsequent lines of the display area.

As described above, according to the present invention, line start address information (determined by the addition value of the line start address information of the previous line and the line memory width information) required when accessing a plurality of prepared display memories 2-i. )
Can be calculated by one adder 16.

〔The invention's effect〕

As described above, according to the present invention, it becomes possible to calculate the address information necessary for accessing a plurality of display memories with one adder. From now on, when adopting the image processing method of directly synthesizing the text and the graphic developed in the bit map memories, this can be realized with a small amount of hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an embodiment of the present invention, FIG. 3 is a time chart of operation processing of the embodiment of FIG. 2, and FIG. 4 is an explanatory diagram of a display area. . In the figure, 1 is an address calculation circuit, 2 is a display memory, 3 is a display data composition processing unit, 10 is a display start register, and 11 is a display start register.
Is a first latch circuit group, 12 is a first multiplexer, 13
Is a line memory width register, 14 is a second latch circuit group,
Reference numeral 15 is a second multiplexer, 16 is an adder, 17 is a line start register, 18 is a display address counter, 19 is a control circuit, 20 is a common line start register, and 21 is a display clock generation circuit.

Claims (1)

[Claims] 1. An address of an image display device, which is used in an image display device for synthesizing and displaying image data read from a plurality of display memories of the same type, and which calculates address information for accessing the display memory. Computation circuit comprising a first latch circuit group (11) for latching display start address information on each display memory, and a line start register (17) provided in association with the display memory The line start register group (30), the holding value of the first latch circuit group (11), and the holding value of the line start register group (30) are input, and one of the input values is input. A first multiplexer (12) for selectively outputting, a second latch circuit group (14) for latching line memory width information on each display memory, and the second latch circuit group A second multiplexer (15) which outputs any one of the holding values of (14) and outputs a zero value when none of the holding values is selected.
By controlling the adder (16) for adding the output values of the first and second multiplexers (12,15) and the first and second multiplexers (12,15), (1
The control circuit 6) controls so as to calculate the start address information on each line of each display memory, and holds the calculated start address information in the corresponding line start register (17). (19) An address calculation circuit for an image display device, comprising: