JPH087602B2 - Multiplex controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Industrial field of application) The present invention relates to a multiplexing controller suitable for synchronizing between multiplexed controllers for process control.

(Prior Art) In recent years, control devices used for process control requiring high reliability are often multiplexed. The output of the multiplexed control device is selected by the selection circuit and output to the process as a control output. In this selection circuit, the multiplexed outputs of the control devices must be output in synchronization, and when the arithmetic operations of the control devices are controlled by a clock, the synchronization circuits link the multiplexed control devices. Conventionally, a method of synchronizing the arithmetic operation of the control device has been used.

FIG. 4 shows a conventional configuration of such a multiplexing control device. Control operations are performed by the operation circuits 2a and 2b of the duplicated control devices 1a and 1b, and the results are output to the selection circuit 3 as the control device outputs _S1a and _S2b . In the selection circuit 3, a process 4 in which one of the control device outputs is a control target
Is output to. At this time, when the control device outputs S _1a and S _1b output to the selection circuit 3 need to be synchronized, such as pulse output, a synchronization circuit 5 that generates a common clock is provided,
Between the control devices 1a and 1b in which the generated synchronization clock S ₂ is multiplexed
Is being applied to. The control outputs S _1a and S _1b are controlled by controlling the operations of the arithmetic circuits 2a and 2b with the synchronous clock S ₂ .
We are trying to synchronize.

(Problems to be Solved by the Invention) However, in the above-described conventional multiplexing control device, the synchronizing circuit is a complicated circuit including a clock oscillator, a frequency dividing circuit, and the like. For this reason, a failure is likely to occur in the synchronizing circuit, and even if the bending angle control device is multiplexed to improve the reliability, the complicated synchronizing circuit causes a problem in reliability.

Further, in the conventional multiplexing control device, a complete set of synchronization circuits must be added when the control devices are multiplexed,
It was not an easy task to multiplex the control device as needed.

Therefore, it is an object of the present invention to provide a multiplexing control device capable of achieving synchronization among the control devices with an extremely simple structure.

[Configuration of the Invention] (Means for Solving the Problem) The present invention provides a logic circuit that inverts and outputs a signal level input to each control device, and outputs the output of the logic circuit provided in one control device. As an input of a logic circuit provided in the other control device, the entire logic circuit between the control devices constitutes an oscillation circuit, and each control device uses the output of the logic circuit as a synchronous clock.

(Function) By forming an oscillator circuit by combining logic circuits between the multiplexed control devices and using the output thereof as a synchronization clock, the outputs of the respective control devices can be synchronized without using a complicated synchronization circuit or the like. it can. That is, with a simple configuration in which a logic circuit is added to one control device, the control device can be multiplexed.

(Embodiment) FIG. 1 is a block diagram of a multiplexing control device showing an embodiment of the present invention, and here is shown an example of duplication. 4th in the figure
The same reference numerals as those in the figure indicate the same or corresponding portions, and the difference from the configuration of FIG. 4 is that instead of the synchronization circuit 5, each control device 1a, 1b
The exclusive OR circuit (hereinafter abbreviated as EXOR) 6
The point is that a and 6b and frequency dividing circuits 7a and 7b are provided. That EXO
The "H" level signal is input to one input terminal of R 6a, and the output signal S _3b of EXOR 6b is input to the other input terminal. The "L" level signal is input to one input terminal of EXOR 6b, and the output signal S _3a of EXOR 6a is input to the other input terminal. Therefore, these two EXOR 6a, 6
An astable multivibrator is constructed at b. The output signals S _3a and S _3b of the EXORs 6a and 6b are frequency-divided by the frequency dividing circuits 7a and 7b, respectively, and then applied to the arithmetic circuits 2a and 2b as synchronous clocks S _2a and S _2b .

The control devices 1a and 1b each have an internal clock and operate at independent sampling times, but these internal clocks are assumed to be in a substantially synchronized state.

Now, as shown in FIG. 2 (a), the sampling time by the internal clock of the control device 1a is t _b1 , t _a2 , t _a3 , t _a4.
On the other hand, it is set in the control device 1b as t _b1 , t _b2 , t _b3 ...
And Further, it is assumed that the internal clocks of the two control devices 1a and 1b are substantially synchronized with the illustrated phase difference.
In this state, E at the sampling time t _a1 on the control device 1a side
When the output signal S _3a of the XOR 6a rises to "H", this output signal S _3a becomes the input of the EXOR 6b, is taken into the EXOR 6b at the sampling time t _b1 on the side of the control device 1b, and the other input signal " An exclusive OR operation with "L" is performed. As a result, the output signal S _3b at the next sampling time t _b2 is rises to "H". This signal S _3b becomes the input of EXOR 6a, is taken into the inside of EXOR 6a at the sampling time t _a3 on the control device 1a side, and the exclusive OR operation with the other input “H” is executed. As a result, the sampling time t _a4
Then, the output signal S _3a falls to "L". Similarly, the signal level of the EXOR 6a output signal S _3a changes, the EXOR 6a output signal level changes, and the result is reflected again in the EXOR 6a output signal level change. Be done. In this way, from each EXOR 6a, 6b,
At a cycle T determined by the internal clock at that time, "H",
Clock signals S _3a and S _3b whose level changes to “L” are obtained.

The period T of the clock signals S _3a and S _3b is determined by each control device 1
If the internal clock cycles of a and 1b are both F, then T = 6F. On the other hand, the case where both internal clocks have no phase shift and are completely synchronized is the largest, and T = 8F. That is, the cycle T of the clock signals S _3a and S _3b is T ≦ 8F (1).

By the way, these clock signals S _3a and S _3b are synchronized with a certain phase difference as shown in FIG. This phase difference _divides the clock signals S _3a and S _3b by the frequency dividing circuit 7
It can be made relatively small by dividing through a and 7b. For example, if the frequency dividing circuits 7a and 7b are 1/4 frequency _dividing circuits, the phase difference between the clock signals S _3a and S _3b is changed from about π / 2 to π / 16 as shown in FIG. 2 (b). Decrease. Therefore, by using the outputs S _2a and S _2b of the frequency dividing circuits 7a and 7b as the synchronization clock, the control device outputs S _1a and S _1b synchronized with the selection circuit 3 can be taken out from the respective control devices 1a and 1b. . Of course, if the phase difference between the clock signals S _3a and S _3b is acceptable, it goes without saying that the frequency dividing circuits 7a and 7b can be omitted.

In this way, each controller 1a, 1b is connected to EXOR 6a, 6b respectively.
The control devices 1a and 1b can be synchronized with each other with a very simple configuration in which the output of each is returned to the input side of each other to form the astable multivibrator. Therefore, this configuration eliminates the need for a complicated synchronizing circuit that was required in the past, and can significantly reduce the number of elements compared to the conventional configuration.
The failure rate can be reduced and the reliability can be greatly improved.

Further, according to the configuration of this embodiment, the outputs of the EXORs 6a and 6b are preceded by the side inputting "H" to one input and "L".
The side that inputs will follow the former. This also enables priority control such that the arithmetic output of the control device preceding the EXOR output, which is a clock, is the regular side, and the arithmetic output of the control device of the following clock is the standby side.

Further, in the present embodiment, an example in which EXOR is used as the logic circuit is shown, but the gate output “H” of another control device,
The effect is the same if it is a logic circuit in which the output is inverted between "H" and "L" according to "L".
It can also be realized by using a ND) circuit and a NOR (NOR) circuit. Further, although the present embodiment has described the duplex configuration,
The same method can be combined, for example, EXOR provided in each control device can be connected in a ring shape, and can be applied to a multiplexing configuration of triple or more.

Further, by simply incorporating EXOR in each control device in advance, it is possible to easily change to a multiplexing configuration later.

By the way, according to the above embodiment, when one side of the duplicated control device fails and the EXOR output is not updated, the EXOR output of the control device of the other normal system is also not updated, and accordingly, the one-sided failure occurs. At times, there is a problem that a normal control device cannot be used. Therefore, FIG. 3 shows an embodiment in which such an inconvenience is removed and the EXOR output can be used as a clock in a normal control device even when the control device of the 1-system is abnormal. In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and in the figure, only the part for generating the synchronous clock on the side of one control device 1a is shown. In this figure, EXOR 6
The point that the output S _3b of the EXOR 6b of the other control device 1b is input to one input of a and the output S _{3a of the} EXOR 6a is output to the other control device 1b is the same as in the embodiment shown in FIG. Further, in this figure, the output S _4a of the output monitoring circuit 8a is input where “H” or “L” was input to one input of EXOR in FIG. This output monitoring circuit 8a is usually
Outputs a fixed value of "H" or "L", but EX
Inputs the output S _{3a of} OR 6a and outputs "L" if it is "H" for a certain time or more, and "H" if output S _3a is "L" for a certain time or more. -Can be composed of a timer and a gate circuit. That is, the other control device has failed,
When the EXOR output S _3b of the other control device becomes “L” and the normal output of the output monitoring circuit 8a is “H”, the EXOR output S _3a becomes “H”.
However, if this “H” continues for a certain time or longer, the output monitoring circuit output S _4a becomes “L”, so EXOR 6a
The output S _{3a of this} becomes "L". Similarly, EXOR 6a output S
When _3a continues at "L", the output S _4a of the output monitoring circuit 8a returns to "H", the output S _3a of EXOR 6a becomes "H". By setting the fixed time period monitored by the output monitoring circuit 8a to be 1/2 or more of the maximum value of the clock cycle F shown in the equation (1),
Even if one system of the duplicated control device becomes abnormal, it is possible to obtain a clock with substantially the same period only by the normal control device 1 system.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a multiplexing control device that requires synchronization by adding an extremely simple circuit. As a result, the reliability and efficiency of the multiplexing control device can be increased by increasing the reliability of the synchronization circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexing controller showing an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of a clock section of the multiplexing controller, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a configuration diagram of a main part of a multiplexing control device showing an example, and FIG. 4 is a configuration diagram of a conventional multiplexing control device. 1a, 1b ... Control device, 2a, 2b ... Arithmetic circuit, 3 ... Selection circuit, 4
… Process, 6a, 6b… EXOR, 7a, 7b… divider circuit, 8a… output monitoring circuit.

Claims (2)

[Claims] 1. A multiplexing control device for synchronizing each control output by applying a synchronous clock to each arithmetic circuit of a plurality of control devices, wherein each control device responds to the inversion of a signal level input thereto. A logic circuit that inverts the level of the output signal in synchronization with the internal clock of the control device is provided, and the output side of the logic circuit provided in one control device is the input side of the logic circuit provided in another control device. By sequentially connecting to each other, the entire logic circuit provided in each control device is connected in a ring shape, while each control device is configured to use the output of the logic circuit as a synchronous clock. . 2. The logic circuit output is constantly monitored, and when it is detected that the output does not change for a predetermined time or longer, the signal level of the logic circuit output is forcibly inverted. The multiplexing control device according to claim 1.