JPH087731A - Resistance/temperature fuse for board - Google Patents

Resistance/temperature fuse for board

Info

Publication number
JPH087731A
JPH087731A JP16590194A JP16590194A JPH087731A JP H087731 A JPH087731 A JP H087731A JP 16590194 A JP16590194 A JP 16590194A JP 16590194 A JP16590194 A JP 16590194A JP H087731 A JPH087731 A JP H087731A
Authority
JP
Japan
Prior art keywords
glass layer
resistance
film
film resistor
trimming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16590194A
Other languages
Japanese (ja)
Inventor
Mitsuaki Uemura
充明 植村
Toshihiko Kawamoto
敏彦 川元
Kazuo Ariyama
和男 有山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Uchihashi Estec Co Ltd
Original Assignee
Uchihashi Estec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Uchihashi Estec Co Ltd filed Critical Uchihashi Estec Co Ltd
Priority to JP16590194A priority Critical patent/JPH087731A/en
Publication of JPH087731A publication Critical patent/JPH087731A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To keep the resistance value of a film constant even though the current impression is put on and off repeatedly by covering the film resistor formed on a board with the first glass layer, adjusting the resistance value with laser trimming, and then putting a covering of a second glass layer. CONSTITUTION:A low melting point metal piece 4 is connected between a pair of film electrodes 2, 2 formed on one surface of a ceramic base board 1, and flux 5 is applied to the metal piece 4. An electrode part 21 for a gap is furnished on the way of one of the film electrodes 2. and a film resistor 6 is connected to this electrode part 21. A resistance paste is screen printed on this film resistor 6 in such a way as straddling the electrode parts 21, 21 of the film electrodes 2, followed by a baking process so that a film resistor 60 is accomplished. The film resistor 60 is covered with the first glass layer 61. and the resistance value is adjusted to the specified value by means of laser, trimming. Then a covering of a second glass layer 62 is put, and a cut slit 63 in the trimming is filled with the glass material of the second glass layer 62. When the film resistance beated by an eddy current in the circuit, the metal piece 4 melts.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、セラミック基板上に温
度ヒュ−ズエレメント(低融点金属体)と膜抵抗とを設
けた基板型抵抗・温度ヒュ−ズに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate type resistance / temperature fuse in which a temperature fuse element (low melting point metal body) and a film resistor are provided on a ceramic substrate.

【0002】[0002]

【従来の技術】基板型抵抗・温度ヒュ−ズにおいては、
セラミック基板上に低融点金属体と膜抵抗とを設け、こ
れらを絶縁材でオ−バコ−トした構成であり、被保護機
器の回路に膜抵抗を挿入し、同回路の入力側に低融点金
属体を挿入し、回路の過電流により膜抵抗が発熱する
と、その発生熱で低融点金属体を溶断作動させて、回路
への通電を遮断し、被保護機器の異常発熱を未然に防止
している。
2. Description of the Related Art In a substrate type resistance / temperature fuse,
A low melting point metal body and a film resistor are provided on a ceramic substrate, and these are over-coated with an insulating material.The film resistor is inserted in the circuit of the protected equipment, and the low melting point is applied to the input side of the circuit. When a metal body is inserted and the membrane resistance heats up due to an overcurrent in the circuit, the heat generated causes the low-melting metal body to melt and cut off the power supply to the circuit, preventing abnormal heat generation of protected equipment. ing.

【0003】この場合、低融点金属体にフラックスを塗
布しておき、膜抵抗からの発生熱により溶融された低融
点金属を既に溶融されているフラックスとの共存下、フ
ラックスの活性により低融点金属の酸化物を溶解しつ
つ、スム−ズに球状化分断させて、作動迅速性を保証し
ている。
In this case, the low melting point metal body is coated with a flux, and the low melting point metal melted by the heat generated from the film resistance coexists with the already melted flux. While dissolving the oxide of No. 1, while smoothing, the particles are divided into spheroids to ensure quick operation.

【0004】上記基板型抵抗・温度ヒュ−ズにおける膜
抵抗の形成には、セラミック基板上に抵抗ペ−ストの印
刷・焼付けにより膜抵抗体を設け、この膜抵抗体をレ−
ザ−トリミングで抵抗値調整することにより所定の抵抗
値に設定している。上記基板型抵抗・温度ヒュ−ズにお
いては、膜抵抗の抵抗値がフラックスとの接触により変
動することのないように、膜抵抗上に保護層を被覆する
ことが安全であり、この保護層には、通常、ガラス層が
使用されている。
To form a film resistor in the above-mentioned substrate type resistance / temperature fuse, a film resistor is provided on a ceramic substrate by printing / baking a resistance paste, and this film resistor is mounted.
A predetermined resistance value is set by adjusting the resistance value by the trimming. In the above-mentioned substrate type resistance / temperature fuse, it is safe to coat a protective layer on the film resistance so that the resistance value of the film resistance does not change due to contact with the flux. A glass layer is usually used.

【0005】而るに、膜抵抗体のトリミング後に、膜抵
抗体上にガラス層を形成すると、すなわち、ガラスフリ
ットを塗布・焼成すると、トリミングにより調整した抵
抗値がその焼成時の加熱により変動される畏れがあるの
で、トリミング前に膜抵抗体上にガラス層を被覆し、し
かるのち、トリミングを行っている。
However, if a glass layer is formed on the film resistor after trimming the film resistor, that is, if a glass frit is applied and fired, the resistance value adjusted by trimming is changed by the heating during firing. Since there is some fear, the film resistor is covered with a glass layer before trimming, and then trimming is performed.

【0006】従来、チップ抵抗器においては、セラミッ
ク基板に抵抗ペ−ストの印刷・焼付けにより膜抵抗体を
設け、この上にガラスフリットを塗布・焼成し、レ−ザ
−トリミングにより抵抗値を所定値に設定し、しかるの
ち、ガラスフリットの塗布・焼成によりオ−バコ−トを
施すことが公知である(特公昭64−4325号公報、
特公平6−18121号公報、特開昭59−8302号
公報)。
Conventionally, in a chip resistor, a film resistor is provided on a ceramic substrate by printing / baking a resistance paste, glass frit is applied / baked on the film resistor, and a resistance value is predetermined by laser trimming. It is known that the value is set, and then, the glass frit is applied and fired to carry out an overcoat (Japanese Patent Publication No. 64-4325).
JP-B-6-18121 and JP-A-59-8302).

【0007】[0007]

【発明が解決しようとする課題】これに対し、上記基板
型抵抗・温度ヒュ−ズにおいては、温度ヒュ−ズエレメ
ントである低融点金属体を備えているので、オ−バコ−
トにガラスフリットの塗布・焼成を使用することは不可
であり(焼成の加熱で低融点金属体が溶融してしま
う)、低融点金属体の融点よりも充分に低い温度でオ−
バコ−トできるものに限られ、通常、エポキシ樹脂の常
温硬化によるオ−バコ−トが使用されている。
On the other hand, in the above-mentioned substrate type resistance / temperature fuse, since the low melting point metal body, which is the temperature fuse element, is provided, the over-heat resistance is reduced.
It is not possible to use the coating and firing of glass frit on the glass (the low-melting metal body is melted by the heating of the firing), and the temperature is sufficiently lower than the melting point of the low-melting metal body.
The overcoat is limited to those that can be baked, and usually an overcoat made by room temperature curing of an epoxy resin is used.

【0008】しかしながら、かかる基板型抵抗・温度ヒ
ュ−ズについての本発明者等の実験結果によれば、課電
のオン,オフを繰り返すと、例えば、当該基板型抵抗・
温度ヒュ−ズをスイッチング電源の突入電源制限素子と
して使用すると、かなりの抵抗値変動が避けられない。
However, according to the results of experiments conducted by the inventors of the present invention with respect to such substrate type resistance / temperature fuses, if the on / off of voltage application is repeated, for example, the substrate type resistance / temperature fuse
If the temperature fuse is used as an inrush power supply limiting element of a switching power supply, a considerable resistance value fluctuation cannot be avoided.

【0009】そこで、本発明者等においては、この原因
を究明するために、種々実験を行ったところ、上記のス
イッチオン,オフのたびに、膜抵抗のトリミングの切削
スリットに放電が発生していることを観察し、その抵抗
値変動の原因は、この放電の繰返しにより、トリミング
の切削スリットが侵食され、あたかも、更にトリミング
が進行されるようになる結果、膜抵抗の抵抗値が変動す
ることと推定される。
Therefore, the inventors of the present invention conducted various experiments in order to investigate the cause, and found that discharge was generated in the cutting slit for trimming the film resistance every time the switch was turned on and off. It is observed that the resistance value fluctuates because the cutting slit for trimming is eroded by repeating this discharge, and as if the trimming progresses further, the resistance value of the membrane resistance fluctuates. It is estimated to be.

【0010】本発明の目的は、トリミングにより調整し
た膜抵抗の抵抗値を、課電のオン,オフを繰り返して
も、充分一定に保持できる基板型抵抗・温度ヒュ−ズを
提供することにある。
An object of the present invention is to provide a substrate type resistance / temperature fuse capable of keeping the resistance value of the film resistance adjusted by trimming sufficiently constant even when the power is repeatedly turned on and off. .

【0011】[0011]

【課題を解決するための手段】本発明に係る基板型抵抗
・温度ヒュ−ズは、セラミック基板上に低融点金属体と
膜抵抗とを設け、該膜抵抗は、抵抗ぺ−ストの印刷・焼
付けにより形成した膜抵抗体を第1のガラス層で被覆し
たのち、レ−ザ−トリミングで抵抗値調整することによ
り設け、この膜抵抗上に第2のガラス層を設け、該膜抵
抗と上記の低融点金属体とを覆って上記セラミック基板
に樹脂を被覆したことを特徴とする構成であり、第1の
ガラス層と第2のガラス層とを同材質とすることが好ま
しい。
A substrate type resistance / temperature fuse according to the present invention is provided with a low melting point metal body and a film resistor on a ceramic substrate, and the film resistor is used for printing a resistance paste. The film resistor formed by baking is provided by coating the first glass layer and then adjusting the resistance value by laser trimming, and the second glass layer is provided on this film resistor. It is preferable that the ceramic substrate is covered with a resin so as to cover the low melting point metal body, and the first glass layer and the second glass layer are made of the same material.

【0012】以下、図面を参照しつつ本発明の構成を説
明する。図1の(イ)は本発明に係る基板型抵抗・温度
ヒュ−ズの一例の平面説明図を、図1の(ロ)は、図1
の(イ)におけるロ−ロ断面図をそれぞれ示している。
図1の(イ)並びに図1の(ロ)において、1はセラミ
ック基板である。2,2はセラミック基板1の片面に設
けた一対の膜電極、3,3は各膜電極2,2に接続した
リ−ド線である。4は膜電極間の先端に接続した低融点
金属体、5は低融点金属体4上に塗布したフラックスで
あり、このフラックスの一部を低融点金属体4と基板1
との間に侵入させることもできる。21は一方の膜電極
の途中に設けたギャップ用電極部、6はギャップ用電極
部21に接続した膜抵抗である。
The structure of the present invention will be described below with reference to the drawings. 1A is a plan explanatory view of an example of the substrate type resistance / temperature fuse according to the present invention, and FIG.
The cross-sectional views along line (a) of FIG.
In FIG. 1A and FIG. 1B, 1 is a ceramic substrate. Reference numerals 2 and 2 are a pair of membrane electrodes provided on one surface of the ceramic substrate 1, and 3 and 3 are lead wires connected to the respective membrane electrodes 2 and 2. Reference numeral 4 is a low-melting metal body connected to the tip between the membrane electrodes, and 5 is a flux applied on the low-melting metal body 4, and a part of this flux is applied to the low-melting metal body 4 and the substrate 1.
It can be invaded between and. Reference numeral 21 is a gap electrode portion provided in the middle of one of the membrane electrodes, and 6 is a membrane resistance connected to the gap electrode portion 21.

【0013】この膜抵抗6においては、図2に示すよう
に、上記膜電極のギャップ用電極部21,21間に跨っ
て抵抗ペ−ストをスクリ−ン印刷し、これを焼成して膜
抵抗体60を設け、この膜抵抗体60上に第1のガラス
層61をガラスフリットの塗布・焼成により被覆し、次
いで、レ−ザ−トリミングにより抵抗値を調整して所定
の抵抗値に設定し、しかるのち、第2のガラス層62を
ガラスフリットの塗布・焼成により被覆して、トリミン
グの切削スリット63を第2ガラス層62のガラスで充
填している。
In the membrane resistor 6, as shown in FIG. 2, a resistance paste is screen-printed across the gap electrode portions 21 and 21 of the membrane electrode, and is fired to burn the membrane resistor 6. A body 60 is provided, a first glass layer 61 is coated on the film resistor 60 by coating and baking glass frit, and then the resistance value is adjusted by laser trimming to set a predetermined resistance value. After that, the second glass layer 62 is covered by coating and baking glass frit, and the trimming cutting slit 63 is filled with the glass of the second glass layer 62.

【0014】この第1のガラス層61と第2のガラス層
62には、異なるガラスフリットの使用も可能である
が、両ガラスの一体化、フリット塗布装置の共通化、フ
リット配合管理の単一化等からして、同一のガラスフリ
ットを使用することが好ましい。
Different glass frits can be used for the first glass layer 61 and the second glass layer 62, but both glasses are integrated, a frit coating device is commonly used, and frit mixture management is performed in a single manner. It is preferable to use the same glass frit in terms of chemical conversion.

【0015】図1の(イ)並びに図1の(ロ)におい
て、7は絶縁樹脂のオ−バ−コ−トであり、エポキシ樹
脂液を滴下塗布し、常温で硬化させるものを使用するこ
とが好ましい。
1 (a) and 1 (b), 7 is an overcoat of an insulating resin, and an epoxy resin liquid is applied dropwise to the insulating resin and cured at room temperature. Is preferred.

【0016】上記基板型抵抗・温度ヒュ−ズにおいて
は、被保護機器の回路に膜抵抗が挿入され、同回路の入
力側に低融点金属体が挿入されることにより使用され、
回路の過電流により膜抵抗が発熱すると、その発生熱で
低融点金属体が溶断作動される。
The board type resistance / temperature fuse is used by inserting a film resistor into the circuit of the protected equipment and inserting a low melting point metal body into the input side of the circuit,
When the film resistance generates heat due to the overcurrent of the circuit, the heat generated causes the low melting point metal body to melt and operate.

【0017】図3の(イ)は、本発明に係る基板型抵抗
・温度ヒュ−ズの別例の平面説明図を、図3の(ロ)は
同じく底面説明図を、図3の(ハ)は図3の(イ)にお
けるハ−ハ断面図を、図3の(ニ)は図3の(ロ)にお
けるニ−ニ断面図をそれぞれ示している。図3の(イ)
乃至図3の(ニ)において、1はセラミック基板であ
る。2a,2aはセラミック基板の片面に設けた一対の
膜電極であり、リ−ド線取付部201と低融点金属体取
付部202とを備えている。3a,3aは各膜電極2
a,2aに接続したリ−ド線である。4は膜電極2a,
2a間に溶接または臘接により接続した低融点金属体、
5は低融点金属体4に塗布したフラックスである。
FIG. 3A is a plan view of another example of the substrate type resistance / temperature fuse according to the present invention, FIG. 3B is a bottom view of the same, and FIG. 3A is a sectional view taken along the line of FIG. 3A, and FIG. 3D is a sectional view taken along the line II of FIG. (A) of FIG.
3 (d), 1 is a ceramic substrate. Reference numerals 2a and 2a denote a pair of membrane electrodes provided on one surface of the ceramic substrate, and include a lead wire attachment portion 201 and a low melting point metal body attachment portion 202. 3a and 3a are each membrane electrode 2
It is a lead wire connected to a and 2a. 4 is the membrane electrode 2a,
A low melting point metal body connected by welding or welding between 2a,
5 is a flux applied to the low melting point metal body 4.

【0018】2b,2bはセラミック基板1の他面に、
左右対称に設けた2対の膜電極であり、一端にリ−ド線
取付部203を有する帯状膜電極204を、リ−ド線取
付部203をセラミック基板1の左右両端側に位置させ
るように配設してある。
2b and 2b are on the other surface of the ceramic substrate 1,
There are two pairs of symmetrically provided membrane electrodes, and strip-shaped membrane electrodes 204 each having a lead wire attachment portion 203 at one end are arranged so that the lead wire attachment portions 203 are located at both left and right ends of the ceramic substrate 1. It is provided.

【0019】6は各一対の膜電極2b,2b間に跨り、
セラミック基板1の他面に設けた膜抵抗であり、図2に
示すように、抵抗ペ−ストの各一対の膜電極204,2
04間に跨っての印刷・焼成による各膜抵抗体60の形
成、ガラスフリットの塗布・焼成による第1ガラス層6
1の形成〔図3の(ロ)に示すように、通常、左右の両
膜抵抗体に跨って被覆してもよく、または、個々の膜抵
抗体上に被覆してもよい〕、第1ガラス層面からのレ−
ザ−トリミングによる各膜抵抗体の抵抗値調整による所
定抵抗値の設定、トリミング後での第1ガラス層61上
へのガラスフリットの塗布・焼成による第2ガラス層6
2〔第1ガラス層61と同様、通常、左右の両膜抵抗体
に跨って被覆してもよく、または、個々の膜抵抗体上に
被覆してもよい〕の形成により設けてある。
A reference numeral 6 extends between each pair of membrane electrodes 2b, 2b,
It is a film resistance provided on the other surface of the ceramic substrate 1. As shown in FIG. 2, each pair of film electrodes 204, 2 of the resistance paste.
Forming each film resistor 60 by printing and firing across 04, and applying the glass frit and firing the first glass layer 6
Formation of 1 (as shown in (b) of FIG. 3), it may be generally covered over both the left and right membrane resistors, or may be coated on each of the membrane resistors], 1st Rays from the glass layer side
Setting of a predetermined resistance value by adjusting the resistance value of each film resistor by the trimming, application of the glass frit on the first glass layer 61 after trimming, and firing of the second glass layer 6
2 [similarly to the first glass layer 61, it may be covered over both the left and right film resistors, or may be covered over the individual film resistors].

【0020】図3の(イ)乃至図3の(ニ)において、
3bは各膜電極2bに溶接または臘接により接続したリ
−ド線である。7はセラミック基板1の両面に低融点金
属体4並びに膜抵抗6を覆って設けた樹脂のオ−バ−コ
−トであり、エポキシ樹脂液を浸漬法により塗布し、常
温で硬化させるものを使用することが好ましい。
In FIG. 3 (a) to FIG. 3 (d),
Reference numeral 3b is a lead wire connected to each of the membrane electrodes 2b by welding or welding. A resin overcoat 7 is provided on both sides of the ceramic substrate 1 so as to cover the low melting point metal body 4 and the film resistor 6, and is coated with an epoxy resin solution by a dipping method and cured at room temperature. Preference is given to using.

【0021】図3の(イ)乃至図3の(ニ)に示した基
板型抵抗・温度ヒュ−ズにおいては、保護すべき電気回
路に対し、一方の膜抵抗が回路のある部分に、他方の膜
抵抗が同回路の他部分にそれぞれ挿入接続され、低融点
金属体が同回路の入力端に挿入接続されることによって
使用され、何れか一方の膜抵抗に過電流が流れて当該膜
抵抗体が発熱すると、その発生熱で低融点金属体が溶断
され、回路の通電が遮断される。
In the substrate type resistance / temperature fuse shown in FIGS. 3 (a) to 3 (d), one membrane resistance is provided in a portion where the circuit is present and the other is provided in the electric circuit to be protected. Are used by inserting and connecting the membrane resistance of each of the other to the other part of the same circuit, and inserting and connecting the low melting point metal body to the input end of the same circuit. When the body heats up, the generated heat melts the low melting point metal body to cut off the power supply to the circuit.

【0022】上記の各基板型抵抗・温度ヒュ−ズにおい
て、膜電極2,2a,2bの形成には、導電性粒子(例
えば、Ag−Pd系金属、Ag−Pt系金属、Ag系金
属、Cu系金属)とガラスフリットとを混合して成る導
電ペ−ストをスクリ−ン印刷し、これを焼成する方法を
使用でき、膜抵抗体60の形成には、抵抗体粒子〔例え
ば、酸化ルテニウム、ランタンボライド(LaB6)、
ド−プされた酸化スズ〕とガラスフリットとを混合して
成る抵抗ペ−ストをスクリ−ン印刷し、これを焼成する
方法を使用できる。
In each of the above substrate type resistance / temperature fuses, conductive particles (eg, Ag-Pd based metal, Ag-Pt based metal, Ag based metal, etc.) are used to form the membrane electrodes 2, 2a and 2b. A method of screen-printing a conductive paste formed by mixing a Cu-based metal) and a glass frit and firing the conductive paste can be used. For forming the film resistor 60, resistor particles (eg ruthenium oxide) are used. , Lanthanide boride (LaB 6 ),
A method of screen-printing a resistance paste formed by mixing doped tin oxide] and a glass frit and firing the same can be used.

【0023】上記において、低融点金属体4には、錫、
鉛、インジュウム、ビスマス、ガドミウム等の2種以上
を成分とする所定温度の共晶合金を使用することが好ま
しい。フラックス5には、ロジンを主成分とし、活性剤
(有機塩化物、有機臭化物等)を添加したものを使用で
きる。
In the above, the low melting point metal body 4 is made of tin,
It is preferable to use a eutectic alloy of two or more kinds such as lead, indium, bismuth, and cadmium at a predetermined temperature. The flux 5 may be rosin as a main component and an activator (organic chloride, organic bromide, etc.) added thereto.

【0024】上記において、セラミック基板1には、優
れた熱伝導性が要求され、通常、アルミナが使用される
が、SIC、AIN等の使用も可能である。上記基板型
抵抗・温度ヒュ−ズにおいては、第1ガラス層を被覆し
た膜抵抗体をトリミングし、第2ガラス層を被覆した
後、低融点金属体を膜電極間に溶接、臘接等により接続
する作業順序で製造される。また、第2ガラス層は、第
1ガラス層の全面に被覆してあるが、トリミングの切削
スリットをガラスで充填し得るものであれば、必ずし
も、第1ガラス層の全面に被覆する必要はない。
In the above, the ceramic substrate 1 is required to have excellent thermal conductivity, and alumina is usually used, but SIC, AIN, etc. can also be used. In the above-mentioned substrate type resistance / temperature fuse, the film resistor coated with the first glass layer is trimmed, the second glass layer is coated, and then the low-melting metal body is welded between the film electrodes, by contact bonding or the like. Manufactured in the connecting work sequence. Further, the second glass layer covers the entire surface of the first glass layer, but it is not always necessary to cover the entire surface of the first glass layer as long as the cutting slit for trimming can be filled with glass. .

【0025】上記において、樹脂のオ−バ−コ−ト(通
常、黒色)の表面には、定格等の所定の表示(通常、
白、黄、オレンジ)が印刷される。
In the above, the surface of the resin overcoat (usually black) has a predetermined indication such as rating (usually, black).
(White, yellow, orange) is printed.

【0026】[0026]

【作用】レ−ザ−トリミングにより第1ガラス層から膜
抵抗体に切り込まれた切削スリットが第2ガラス層のガ
ラスで充填され、膜抵抗の切削エッジがガラスで覆われ
ているから、課電のオン,オフを繰り返しても、トリミ
ングの切削スリットでの放電を充分に防止できる。
The cutting slit cut from the first glass layer into the film resistor by laser trimming is filled with the glass of the second glass layer, and the cutting edge of the film resistance is covered with the glass. Even if the power is turned on and off repeatedly, it is possible to sufficiently prevent the discharge at the trimming cutting slit.

【0027】また、第2ガラス層の焼成熱の膜抵抗体へ
の伝導に対し、第1ガラス層が熱抵抗として作用し、第
2ガラス層の焼成時での膜抵抗体の加熱変形を充分に防
止できる。
Further, the first glass layer acts as a thermal resistance against the conduction of the heat of firing of the second glass layer to the film resistor, so that the film resistor is sufficiently heated and deformed when the second glass layer is fired. Can be prevented.

【0028】従って、トリミングにより設定した膜抵抗
の抵抗値を、膜抵抗体の放電侵食や加熱変形をよく排除
して充分一定に保持でき、基板型抵抗・温度ヒュ−ズの
抵抗値変動による作動不良を排除できる。このことは、
次ぎに述べる実施例と比較例との対比から明らかであ
る。
Therefore, the resistance value of the film resistance set by trimming can be kept sufficiently constant by well eliminating the discharge erosion and the heat deformation of the film resistor, and the operation can be performed by the fluctuation of the resistance value of the substrate type resistance / temperature fuse. You can eliminate defects. This is
It is clear from the comparison between the example and the comparative example described below.

【0029】[0029]

【実施例】【Example】

〔実施例〕図3の(イ)乃至図3の(ニ)並びに図2で
説明した構成の基板型抵抗・温度ヒュ−ズである。セラ
ミック基板には、厚さ0.6mm、縦9mm、横14m
mのアルミナ基板を使用し、先ず、全ての膜電極を銀ペ
−ストの印刷・焼付けにより厚み25μmで形成した。
[Embodiment] A substrate-type resistance / temperature fuse having the configuration described in FIGS. 3 (A) to 3 (D) and FIG. The ceramic substrate has a thickness of 0.6 mm, a length of 9 mm, and a width of 14 m.
First, all the membrane electrodes were formed with a thickness of 25 μm by printing and baking with silver paste.

【0030】更に、膜抵抗体を抵抗ペ−スト(酸化ルテ
ニウム粉末とガラスフリットとの混合物)の厚み20μ
mの印刷・焼付け(焼付け温度900℃)により形成
し、第1ガラス層を低融点ガラスフリットの厚み40μ
mの塗布・焼付け(焼付け温度500℃)により設け、
両膜抵抗体の抵抗値をトリミングにより共に1000Ω
に調整した。このトリミング後、第2ガラス層を低融点
ガラスフリットの厚み40μmの塗布・焼付け(焼付け
温度500℃)により設けた。
Further, the film resistor is provided with a resistance paste (a mixture of ruthenium oxide powder and glass frit) having a thickness of 20 μm.
m by printing and baking (baking temperature 900 ° C.), and the first glass layer has a low melting point glass frit thickness of 40 μm.
It is provided by applying and baking m (baking temperature 500 ° C).
Trimming the resistance value of both film resistors to 1000Ω
Adjusted to. After this trimming, the second glass layer was formed by applying and baking a low melting point glass frit with a thickness of 40 μm (baking temperature 500 ° C.).

【0031】次いで、各膜電極に直径0.6mmの銅リ
−ド線を接続した。更に、直径0.5mm、液相温度9
6℃の低融点金属線を接続し、該低融点可溶合金線上
に、ロジンを主成分とするフラックスを塗布した。最後
に、セラミック基板全体にエポキシ樹脂液(粘度200
00cps〜50000cps程度)を浸漬法により塗布し、
常温で硬化した。
Next, a copper lead wire having a diameter of 0.6 mm was connected to each membrane electrode. Furthermore, diameter 0.5mm, liquidus temperature 9
A low melting point metal wire at 6 ° C. was connected, and a flux containing rosin as a main component was applied onto the low melting point fusible alloy wire. Finally, epoxy resin liquid (viscosity 200
00 cps to 50000 cps) is applied by the dipping method,
Cured at room temperature.

【0032】〔比較例〕実施例に対し、第2ガラス層の
被覆を省略した以外、実施例に同じとした。
Comparative Example The same as the example except that the coating of the second glass layer was omitted.

【0033】これらの実施例品並びに比較例品(各試料
数50個)のそれぞれにつき、一の各膜抵抗と低融点金
属体とをそれぞれ直列に接続し、500ボルトを30μ
秒オン,10秒オフで繰返し課電し、100サイクル経
過時での各膜抵抗の抵抗値を測定したところ、実施例で
は、全て±5%以内の抵抗値変動であった。これに対
し、比較例では全て±10%以上の抵抗値変動であり、
セラミック基板を剥離し、第2ガラス層を露出し、トリ
ミング跡を拡大鏡で観察したところ、放電の痕跡が観ら
れた。
For each of these example products and comparative example products (the number of each sample is 50), one film resistance and one low melting point metal body are connected in series, and 500 V is 30 μm.
When the resistance value of each film resistance was measured after 100 cycles had elapsed by repeatedly applying electricity for 2 seconds on and 10 seconds off, all of the examples showed a resistance value variation of within ± 5%. On the other hand, in the comparative examples, the resistance value variation is ± 10% or more,
When the ceramic substrate was peeled off, the second glass layer was exposed, and the trimming trace was observed with a magnifying glass, traces of discharge were found.

【0034】[0034]

【発明の効果】本発明に係る基板型抵抗・温度ヒュ−ズ
においては、レ−ザ−トリミングにより抵抗値を調整し
た第1ガラス層被覆膜抵抗体の切削スリットを第2ガラ
ス層のガラスで充填しているから、その切削スリットで
の放電をよく防止でき、使用中での抵抗値変動を充分に
回避できる。この場合、オ−バ−コ−トを樹脂で行い、
第2ガラス層の被覆を膜抵抗上のみに限っているから、
低融点金属体に悪影響を及ぼすこと無く、その放電防止
を達成できる。
In the substrate type resistance / temperature fuse according to the present invention, the cutting slit of the first glass layer coating film resistor whose resistance value is adjusted by laser trimming is used as the glass of the second glass layer. Since it is filled with, the discharge at the cutting slit can be well prevented, and the fluctuation of the resistance value during use can be sufficiently avoided. In this case, the overcoat is performed with resin,
Since the coating of the second glass layer is limited only to the film resistance,
The discharge can be prevented without adversely affecting the low melting point metal body.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1の(イ)は本発明に係る基板型抵抗・温度
ヒュ−ズの一例を示す平面説明図、図1の(ロ)は図1
の(イ)におけるロ−ロ断面図である。
1 (a) is a plan explanatory view showing an example of a substrate type resistance / temperature fuse according to the present invention, and FIG. 1 (b) is FIG.
It is a sectional view taken along line (a) of FIG.

【図2】本発明において使用する膜抵抗の構成を示す断
面説明図である。
FIG. 2 is a cross-sectional explanatory view showing a structure of a film resistor used in the present invention.

【図3】図3の(イ)は、本発明に係る基板型抵抗・温
度ヒュ−ズの別例の平面説明図、図3の(ロ)は同じく
底面説明図、図3の(ハ)は図3の(イ)におけるハ−
ハ断面図、図3の(ニ)は図3の(ロ)におけるニ−ニ
断面図である。
3 (a) is a plan view of another example of the substrate resistance / temperature fuse according to the present invention, FIG. 3 (b) is a bottom view of the same, and FIG. 3 (c). Is the line in (a) of FIG.
3C is a sectional view, and FIG. 3D is a sectional view taken along line II in FIG.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 膜電極 2a 膜電極 2b 膜電極 3 リ−ド線 3a リ−ド線 3b リ−ド線 4 低融点金属体 5 フラックス層 6 膜抵抗 60 膜抵抗体 61 第1ガラス層 62 第2ガラス層 63 トリミングの切削スリット 7 樹脂のオ−バ−コ−ト DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Membrane electrode 2a Membrane electrode 2b Membrane electrode 3 Lead wire 3a Lead wire 3b Lead wire 4 Low melting point metal body 5 Flux layer 6 Membrane resistance 60 Membrane resistor 61 First glass layer 62 Second Glass layer 63 Cutting slit for trimming 7 Overcoat of resin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】セラミック基板上に低融点金属体と膜抵抗
とを設け、該膜抵抗は、抵抗ぺ−ストの印刷・焼付けに
より形成した膜抵抗体を第1のガラス層で被覆したの
ち、レ−ザ−トリミングで抵抗値調整することにより設
け、この膜抵抗上に第2のガラス層を設け、該膜抵抗と
上記の低融点金属体とを覆って上記セラミック基板に樹
脂を被覆したことを特徴とする基板型抵抗・温度ヒュ−
ズ。
1. A low melting point metal body and a film resistor are provided on a ceramic substrate, and the film resistor is formed by printing and baking a resistance paste, and then covering the film resistor with a first glass layer. A second glass layer is provided on the film resistor by adjusting the resistance value by laser trimming, and the ceramic substrate is coated with a resin so as to cover the film resistor and the low melting point metal body. Substrate type resistance / temperature fuse characterized by
Z.
【請求項2】第1のガラス層と第2のガラス層とを同材
質とした請求項1記載の基板型抵抗・温度ヒュ−ズ。
2. The substrate type resistance / temperature fuse according to claim 1, wherein the first glass layer and the second glass layer are made of the same material.
JP16590194A 1994-06-24 1994-06-24 Resistance/temperature fuse for board Pending JPH087731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16590194A JPH087731A (en) 1994-06-24 1994-06-24 Resistance/temperature fuse for board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16590194A JPH087731A (en) 1994-06-24 1994-06-24 Resistance/temperature fuse for board

Publications (1)

Publication Number Publication Date
JPH087731A true JPH087731A (en) 1996-01-12

Family

ID=15821149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16590194A Pending JPH087731A (en) 1994-06-24 1994-06-24 Resistance/temperature fuse for board

Country Status (1)

Country Link
JP (1) JPH087731A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000011831A (en) * 1998-06-19 2000-01-14 Nec Kansai Ltd Thermal fuse with resistance
CN102239535A (en) * 2009-01-21 2011-11-09 新力化工与资讯产品股份有限公司 Protection element
US8547195B2 (en) 2008-05-23 2013-10-01 Dexerials Corporation Protective element and secondary battery device
US8648688B2 (en) 2009-01-21 2014-02-11 Dexerials Corporation Protection element
CN105593962A (en) * 2013-09-26 2016-05-18 迪睿合电子材料有限公司 Short-circuiting element
CN108475602A (en) * 2015-12-18 2018-08-31 迪睿合株式会社 Fuse element
CN117153641A (en) * 2022-05-23 2023-12-01 功得电子工业股份有限公司 Protective element with cover

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000011831A (en) * 1998-06-19 2000-01-14 Nec Kansai Ltd Thermal fuse with resistance
US8547195B2 (en) 2008-05-23 2013-10-01 Dexerials Corporation Protective element and secondary battery device
CN102239535A (en) * 2009-01-21 2011-11-09 新力化工与资讯产品股份有限公司 Protection element
US8648688B2 (en) 2009-01-21 2014-02-11 Dexerials Corporation Protection element
US8803652B2 (en) 2009-01-21 2014-08-12 Dexerials Corporation Protection element
CN105593962A (en) * 2013-09-26 2016-05-18 迪睿合电子材料有限公司 Short-circuiting element
CN108475602A (en) * 2015-12-18 2018-08-31 迪睿合株式会社 Fuse element
CN117153641A (en) * 2022-05-23 2023-12-01 功得电子工业股份有限公司 Protective element with cover

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