JPH088309B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device.

(Prior Art) In a non-volatile semiconductor memory device such as an EPROM or an EEPROM, information is stored by, for example, accumulating electrons at a floating gate or an oxide film / nitride film interface.

In such a configuration, if positive mobile ions such as Na ⁺ are present in the wafer process or enter from the outside, they are attracted to accumulated electrons and neutralize them during use to cause malfunction. May be invited.

To solve this problem, the memory cell array is conventionally covered with an insulating film formed of, for example, a silicon oxide film containing phosphorus (hereinafter referred to as SiO ₂ ). That is, the insulating film generally has the property of immobilizing mobile ions by gettering. Therefore,
By covering the memory cell array with this, invasion of mobile ions from the outside can be prevented. Further, the above-mentioned insulating film has a property of absorbing mobile ions when subjected to a high temperature heat treatment. Therefore, after the insulating film is formed, by heat-treating the insulating film at a high temperature, mobile ions that have entered before the insulating film is formed can be absorbed and neutralization with stored electrons can be prevented.

However, in such a configuration, there is a problem that mobile ions may enter from a contact hole during wiring formation, or mobile ions may enter from a dicing line during dicing to neutralize stored electrons. .
That is, generally, under the insulating film, for example, SiO ₂
An oxide film formed by is provided. Mobile ions can move freely in this oxide film. Therefore, when the oxide film is exposed by the formation of the contact hole or the dicing process, the mobile ions enter from here.
Since the high temperature heat treatment as described above is not performed after the wiring is formed, the movable ions that have entered during the formation of the wiring cannot be gettered by the insulating film, and the neutralization with stored electrons cannot be prevented. The same applies to mobile ions that enter after dicing.

From the above, it is very important to prevent neutralization of accumulated electrons by mobile ions penetrating from the contact hole or the dicing line.

(Problems to be Solved by the Invention) As described above, in the conventional semiconductor memory device,
There is a problem that mobile ions may enter during wiring formation or dicing, neutralize stored electrons, and cause malfunction.

Therefore, an object of the present invention is to provide a semiconductor memory device capable of suppressing neutralization of stored electrons even when mobile ions enter during wiring formation or dicing.

[Structure of the Invention] (Means for Solving Problems) The present invention is formed in an element formation region of a semiconductor substrate,
A storage portion including a storage cell array including a plurality of storage cells; an oxide film formed on the semiconductor substrate so as to cover the storage portion; and a portion of the periphery of the storage portion that is located at least near the dicing line. An opening provided in the oxide film to expose the semiconductor substrate; and an insulating film provided on the oxide film and in the opening, the insulating film containing phosphorus to prevent movement of mobile ions in the oxide film. are doing.

Further, the opening is provided in an oxide film located around each memory cell in a portion where a large number of mobile ions exist among a plurality of storage cells, and the oxide film is provided on the oxide film and in the opening. An insulating film containing phosphorus is provided to prevent movement of mobile ions therein.

(Operation) According to the above configuration, the movable ions that have entered the oxide film from the contact hole or the dicing line during the wiring formation or the dicing are prevented from moving by the insulating film and cannot reach the memory cell. Thereby, neutralization of stored electrons can be suppressed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing a partial structure of an embodiment of the present invention, and FIG. 2 is a plan view showing the whole structure.

In FIG. 1, 11 is a silicon substrate. 12 is a memory cell array, and 13 is its memory cell. 14 is a peripheral circuit, and 15 is its transistor.

Note that FIG. 1 is an enlarged view of a portion shown as R in FIG. 2, that is, a minute portion of the boundary portion between the memory cell array 11 and the peripheral circuit 13.

The memory cell 13 is formed of, for example, a floating gate type MOS field effect transistor (hereinafter referred to as MOSFET). That is, in the memory cell 13, 131 is a source electrode, 132 is a drain electrode, 133 is a first gate insulating film, 134 is a floating gate electrode, and 135 is a second gate insulating film. And 136 is a control gate electrode.

In addition, the transistor 15 of the peripheral circuit 14 is formed of a MOSFET. That is, in the transistor 15, 151 is a source electrode, 152 is a drain electrode, 153 is a gate insulating film, and 154 is a gate electrode.

The memory cell 13 and the transistor 15 are made of, for example, SiO ₂
And is covered with an oxide film 16 of. This oxide film 16
An interlayer insulating film 17 made of, for example, SiO ₂ containing phosphorus is formed on the above so as to cover the memory cell 13 and the transistor 15. The interlayer insulating film 17 further has a part of the silicon substrate 11 via a groove 18 formed in the oxide film 16.
To come into contact with.

The groove 18 is formed by the storage cell array 12 as shown by the hatching in FIG.
Is formed all around. Therefore, the interlayer insulating film 17 is in contact with the silicon substrate 11 so as to surround the memory cell array 12.

The oxide film 16 is usually provided to protect the memory cell 13 and the transistor 15 from the diffusion of impurities (particularly phosphorus) from the interlayer insulating film 17 and to improve the reliability of the gate electrode. Is.

The semiconductor memory device of one embodiment has the above-mentioned configuration. Here, an example of the manufacturing process of this semiconductor memory device will be described with reference to FIGS. 3 to 5. In this process, first, as shown in FIG. 3, the memory cell 13 and the transistor 15 are formed by using various processes such as introduction of impurities by ion implantation. Next, as shown in FIG. 4, the oxide film 16 is formed to a thickness of about 500 Å by thermal oxidation, for example. Next, as shown in FIG. 5, trenches 18 are formed by removing the oxide film 16 along the entire periphery of the memory cell array 12 by, for example, a photolithography process. Next, an insulating film 17 containing phosphorus is deposited on the oxide film 16 by, for example, a CVD method to a thickness of about 5000 Å, resulting in the state shown in FIG.
After that, a semiconductor memory device is completed by forming contact holes, forming a wiring of aluminum or the like, and forming a protective film for this wiring.

As described above, in this embodiment, the memory cell array 12
The interlayer insulating film 17 is brought into contact with the silicon substrate 11 all around.

According to such a configuration, the movable ions that have entered the oxide film 16 from the contact holes or the dicing line during the wiring formation or the dicing process are not covered with the insulating film 17 in the groove 18.
The movement is blocked by and the storage cell 13 cannot be reached. Therefore, according to this embodiment, it is possible to suppress neutralization of accumulated electrons due to invasion of mobile ions and ensure stable operation.

Further, in this embodiment, since the interlayer insulating film 17 is used as the insulating film that comes into contact with the silicon substrate 11, the structure of the semiconductor memory device and the manufacturing process can be simplified.

In the above embodiment, the case where the interlayer insulating film 17 is brought into contact with the silicon substrate 11 along the entire circumference of the memory cell array 12 has been described. However, as shown in FIG. It is needless to say that the interlayer edge film 17 may be brought into contact with the silicon substrate 11 along the line.

In the previous embodiment, the interlayer insulating film is formed on the silicon substrate 11 over the entire circumference of the memory cell array 12 or the memory cell 13.
Although the case of making contact with the above has been described, it is needless to say that the contact may be made only over a part. For example, the contact is made at a portion where mobile ions easily enter such as the vicinity of the dicing line. This idea can be applied to the embodiment shown in FIG. In other words, the interlayer insulating film is brought into contact with the silicon substrate over the entire circumference of only the memory cell where a large number of mobile ions are present.

Further, although the case where the interlayer insulating film is used as the insulating film of the present invention has been described in the previous embodiment, the present invention is not limited to this, and it goes without saying that an insulating film dedicated to blocking movable ions may be provided. .

Further, in the above-described embodiment, the case where the insulating film is formed of SiO ₂ containing phosphorus has been described, but it is needless to say that the insulating film may be formed of SiO ₂ containing phosphorus and boron, for example.

Further, it goes without saying that the present invention can be applied to semiconductor devices other than nonvolatile ones.

[Effects of the Invention] As described above, according to the present invention, it is possible to prevent invasion of mobile ions during wiring formation of a peripheral circuit or during dicing, and it is possible to enhance the neutralization prevention capability of accumulated charges. A semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIG.
3 is a plan view, FIG. 3 to FIG. 5 are sectional views for explaining an example of the manufacturing process of the semiconductor memory device of one embodiment, and FIG. 6 is a plan view showing the structure of another embodiment of the present invention. It is a figure. 11 ... Silicon substrate, 12 ... Storage cell array, 13 ... Storage cell, 14 ... Peripheral circuit, 15 ... Transistor, 16 ...
Oxide film, 17 ... Interlayer insulation layer, 18 ... Groove.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/792

Claims (4)

[Claims] 1. A storage unit formed in a device formation region of a semiconductor substrate, the storage unit including a storage cell array including a plurality of storage cells; an oxide film formed on the semiconductor substrate to cover the storage unit; An opening that is provided in the oxide film at least in the vicinity of the dicing line in the periphery of the portion and that exposes the semiconductor substrate; and an opening that is provided on and in the opening of the oxide film. An insulating film containing phosphorus that blocks the movement of mobile ions. 2. The semiconductor memory device according to claim 1, wherein the opening is provided in the oxide film located all around the memory. 3. A storage portion formed in an element formation region of a semiconductor substrate and including a plurality of storage cells, an oxide film formed on the semiconductor substrate so as to cover the storage portion, and a storage portion of the plurality of storage cells. An opening provided in the oxide film located around each memory cell in a portion where at least a large number of mobile ions exist, exposing the semiconductor substrate; and an opening provided on the oxide film and in the opening, An insulating film containing phosphorus that blocks the movement of mobile ions in the oxide film. 4. The semiconductor memory device according to claim 3, wherein the opening is formed in the oxide film located around the entire periphery of each memory cell.