JPH0883207A - Data processing device and data processing method - Google Patents

Abstract

(57) [Summary] [Object] To improve a data processing device, memory access is continuously performed, data is supplied to a data processing unit without interruption, and an operation suspension period is minimized, so that data processing is performed at high speed. [Structure] An address generation unit 11 that generates an ADR address according to a parameter, a data processing unit 12 that calculates read data and outputs the calculation result data to a bus control unit, and a storage address specified by the ADR address. Memory 1 that reads the data in the memory, writes the data in the storage address specified by the ADW address, and stores it
3 and a bus control unit 14 that prioritizes a data read operation and adjusts a data write operation while monitoring the ADR address and ADW.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method, and more specifically,
The present invention relates to an improvement in an apparatus and method in which a plurality of bus masters share one memory and perform data processing while performing bus arbitration. In recent years, as various information processing apparatuses have been highly functionalized and diversified, speeding up of data processing is required. For example, a system that reads data corresponding to a certain parameter from the memory, performs certain arithmetic processing using this data, and updates the data when the data read from the memory is changed as a result (read modify) Write operation) is adopted.

According to this, when a plurality of bus masters share one memory to perform data processing, a bus arbitration unit is provided for each data processing block and the permission is obtained for a bus request. In addition, a method of executing memory access is adopted. However, after the bus master outputs the bus request, the data read operation may not be possible or the data processing unit may have an operation suspension period until the bus request is permitted.

Therefore, memory access is continuously performed,
There is a demand for an apparatus and method capable of supplying data to the data processing section without interruption to minimize the operation suspension period and speed up data processing.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional data processing apparatus. For example, in a data processing device with a bus arbitration function, as shown in FIG. 6, a memory 3, an address generator & transfer controller 1 and a data processor 2 are connected to a bus 5, a controller 1 and a data processor 2 (bus master). ), The bus arbitration unit 4 is connected.

The function of the device is that when the memory 3 is accessed from two bus masters while maintaining data consistency, both bus masters issue a memory access request to the bus arbitration unit 4 and, after the permission is obtained, Access the memory. For example, when the data corresponding to a certain parameter is read from the memory 3, a certain arithmetic process is performed using this data, and the data at the same address in the memory is updated,
First, the address generation unit & transfer control unit 1 generates the address "001" by a parameter from the outside. The address generation unit outputs a bus request = “0” to the bus arbitration unit 4, and after the bus arbitration unit 4 is permitted, reads the corresponding data “11” from the memory 3 and holds it internally to request the data processing unit 2. Forward according to.

The data processing unit 2 receives the received data "1".
Assuming that the data is changed to "18" as a result of the data processing based on "1", the data processing unit 2 outputs the bus request = "1" to the bus arbitration unit 4 and the data is changed to "18". After being permitted, the data “18” corresponding to the address “001” is written in the memory. As a result, the data at the same storage address in the memory is updated.

[0007]

According to the conventional example, when a plurality of bus masters share one memory to perform data processing, a bus arbitration unit 4 is provided for each data processing block, and the arbitration unit is provided. Issue a memory access request to 4,
After the permission is obtained, the memory access is executed.

Therefore, when the data is read from the memory 3 and transferred to the data processing unit 2, the address generation unit & transfer control unit 1 outputs a bus request = "0" to the bus arbitration unit 4, and then The data read operation is suspended until it is enabled. As a result, an idle period (dead time of memory access) occurs. If such an operation suspension period is to be supplemented by hardware, a complicated timing arbitration circuit or access cycle must be changed.

As a result, there is a problem that a wasteful time is spent for bus arbitration, which hinders speeding up of data processing and data cannot be updated efficiently. The present invention was created in view of the problems of the conventional example, and continuously accesses the memory, supplies data to the data processing unit without interruption, minimizes the operation pause period, and speeds up the data processing. It is an object of the present invention to provide a data processing device and a data processing method capable of achieving the above.

[0010]

As shown in FIGS. 1 to 5, a data processing apparatus according to the present invention has a principle device, a read address for reading data and a write address for writing data. And a first register for sequentially holding read addresses as shown in FIG. 2, the control means having a priority to a data read operation and adjusting the data write operation. A second register that sequentially shifts and holds the write address and data associated with the write address; a read address located at the head of the read addresses sequentially shifted by the first register; and the second register Compare all write addresses that are sequentially shifted by and output the write address that matches the read address. Characterized in that it has an address comparison circuit for, and a data selection circuit for selectively outputting the associated data to the write address matches the read address.

In the first data processor of the present invention,
As shown in FIG. 4C, the second register is associated with the remaining write address and the write address when the write address matching the read address and the data associated with the write address are output. It is characterized in that the filled data is packed. In the second data processing device of the present invention, the control means, as shown in FIG. 5, stores a first register for sequentially holding a read address designating a data read address of the memory, and data to be written in the memory. A second register for holding, an address comparison circuit for comparing a read address initially held in the first register with a newly held read address and outputting a data selection signal, and updating of data. And a data selection circuit for outputting either the read address initially held or the newly held read address based on a request signal and the data selection signal.

In the data processing method of the present invention, the read operation of data is prioritized and the write operation of data is adjusted while monitoring the read address for reading data and the write address for writing data. It is characterized by The first data processing method of the present invention is
On the other hand, a plurality of read addresses designating a read address of data are sequentially held, and on the other hand, a plurality of write addresses designating a write address of data and data to be written to the write address are sequentially stored in association with each other. Among the read addresses sequentially held, the read address held at the head position is compared with all the write addresses sequentially held on the other side, and the read address is compared with all the write addresses. As a result, if there is no address that matches, the read address held at the head position is output. If there is a address that matches, the write address that matches the read address and the write address. The data associated with the address is output.

According to the second data processing method of the present invention, on the one hand, the read address designating the data read address of the memory is sequentially held, on the other hand, the data to be written in the memory is held, and on the other hand, first, The held read address is compared with the newly held read address. As a result of comparing the two addresses, if the addresses do not match, the newly held read address is selected and In the case of a match, the first read address is selected as a write address, and the held data is output in association with the write address, and the above object is achieved.

[0014]

[Operation] Next, referring to FIGS.
The operation of the data processing device will be described. For example, the read address and the write address are monitored by the bus control unit 14, which is an example of the control means as shown in FIG. 1, and the data read operation is prioritized over the data write operation.
The write operation is adjusted.

Therefore, the read data from the memory can be supplied to the data processing section without interruption, without the write operation unlike the conventional bus arbitration method being influenced by the sequential processing. That is, as shown in FIG. 2, when the read address is supplied to the first register of the bus control unit 14, the address is sequentially shifted and held. Further, the write address from the data processing unit and the data associated with the write address are sequentially shifted and held in the second register. Of the read addresses sequentially shifted by the first register, the read address located at the head and all the write addresses sequentially shifted by the second register are compared by the address comparison circuit.

If there is no matching address in the comparison result at this time, the read address held at the head position is output to the memory, and if there is a matching address, the read address is matched. The write address and the data associated with the write address are selected by the data selection circuit and are output to the memory (first data processing method).

Therefore, the read address and the write address are monitored by the address comparison circuit, and the data read operation can be prioritized over the data write operation.
The write operation can be adjusted. As a result, the read data from the memory can be supplied to the data processing unit without interruption. In addition, memory access can be performed continuously, and data can be updated efficiently.

As a result, the time for bus arbitration is eliminated as compared with the conventional example, the operation suspension period in each data processing block is reduced, and the speed of data processing can be increased. The operation of the second data processing device of the present invention will be described. For example, as shown in FIG. 5, the read address is sequentially shifted and held by the first register of the bus control unit 14. Further, the data to be written in the memory is held by the second register. Here, the first held read address and the newly held read address are compared by the address comparison circuit. As a result, the data selection signal is output to the data selection circuit. The data selection circuit outputs either the first read address or a new read address based on the signal requesting data update and the data selection signal.

Therefore, as a result of comparing the two addresses, if the addresses do not match, a new read address is selected and the read operation is prioritized. When the addresses match, the first read address can be selected as the write address, and the data held in association with the write address can be output to the memory. As a result, the data read operation can be prioritized while the read address is monitored, and the write operation can be adjusted. In addition, memory access can be performed continuously, data can be efficiently updated, and data processing can be speeded up.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, each embodiment of the present invention will be described with reference to the drawings. 1 to 5 are diagrams illustrating a data processing device and a data processing method according to each embodiment of the present invention. (1) Description of First Embodiment FIG. 1 is an overall configuration diagram of a data processing device according to a first embodiment of the present invention, and FIG. 2 is an internal configuration diagram of its bus control unit. FIG. 3 shows a state transition chart of the shift register.

For example, a data processing device in which two bus masters share one memory 13 to access the memory is
As shown in FIG. 1, an address generation unit 11, a data processing unit 12, a memory 13, a bus control unit 14, and a data FIFO.
A memory 15 is provided. That is, the address generator 11 is an example of a bus master, generates a read address (hereinafter referred to as an ADR address) according to a parameter supplied from the outside, and outputs it to the bus controller 14. The address generation unit 11 uses the AD regardless of the memory access status.
Generate an R address. The ADR address is data relating to the reading of data.

The data processing unit 12 is an example of a bus master, inputs read data (DATA), performs arithmetic processing, for example, and outputs the arithmetic result data to the bus control unit 14. The memory 13 is connected to the bus 16 and reads data at a storage address specified by an ADR address, writes data at a storage address specified by a write address (hereinafter referred to as an ADW address), and stores the data. The data processing unit 12 executes, for example, arithmetic processing regardless of the memory access status. The ADW address is data relating to data writing.

The bus control unit 14 is an example of control means,
ADR is connected between the bus 16 and the data generator 12.
While monitoring the address and ADW, the data read operation is prioritized and the data write operation is adjusted.
The bus control unit 14 will be described in detail with reference to FIG. The data FIFO memory 15 is connected between the bus 16 and the data processing unit 12, inputs the data-processed data, and sequentially shifts the data.

As shown in FIG. 2, the bus control unit 14 includes, for example, a data control shift register (hereinafter simply referred to as a read register) 41, a memory control shift register (hereinafter simply referred to as a write register) 42, an address comparison circuit 43, It is composed of a selector 44 and a bus control signal generation circuit 45. The read register 41 is an example of the first register, and the ADR from the address generation unit 11 is used.
The addresses are sequentially shifted and held, and the ADR address is output to the bus control signal generation circuit 45 in preference to the ADW address. The write register 42 is an example of the second register 42, and includes a write address shift register 42A and a write data shift register 42B. The register 42A sequentially shifts and holds the ADW address from the data processing unit 12. The register 42B sequentially shifts and holds the data attached to the ADW address from the data processing unit 12. The internal configuration of the write register 42 will be described in detail with reference to FIG.

The address comparison circuit 43, among the ADR addresses sequentially shifted by the read register 41,
The ADR address located at the head and the write register 42
By comparing all the ADW addresses sequentially shifted by, the ADW address that matches the ADR address is output. The address comparison circuit 43 outputs the address comparison / selection signals SA1, SA2 ... To the write register 42 and the selector 44 when an ADW address matching the ADR address is found.

The selector 44 is an example of a data selection circuit, which selects the data associated with the ADW address that matches the ADR address according to the address comparison / selection signals SA1, SA2, etc., and uses it to select the bus control signal generation circuit. Output to 45. The bus control signal generation circuit 45 is connected to the bus 16 and adjusts the ADR address, the ADW address and the data to a predetermined potential and transmits the adjusted potential to the bus 16. The circuit 45 generates a data enable signal R / W for identifying a data writing or reading operation, and outputs it to the memory 13 and the data F.
The data is transferred to the IFO memory 15 and the data processing unit 12.

Now, the write register 42 will be described. For example, the write address shift register 42A is composed of three memory circuits 421, 423 and 425 and two selectors 422 and 424 as shown in FIG. Memory circuit 421
Holds the ADW address based on the shift signal SS. The selector 422 selects either the ADW address output from the memory circuit 421 or the ADW address held in the memory circuit 423 according to the address comparison / selection signal SA1.

The memory circuit 423 holds the ADW address based on the shift signal SS. The selector 424 selects either the ADW address output from the memory circuit 423 or the ADW address held in the memory circuit 424 according to the address comparison / selection signal SA1. The address comparison / selection signals SA1, SA2 ... Are asserted when the address comparison circuit 43 finds an ADW address that matches the ADR address. The register 42A shifts the previous ADW address, deletes the matching ADR = ADW address, and packs one ADW address for storage. The register 42B has a similar function.

As a result, in the write register 42, A
When the ADW address that matches the DR address and the data associated with the ADW address are output, the remaining A
The data associated with the DW address and the ADW address can be packed, and the data in the memory can be updated efficiently. This will be described with reference to FIG.

Next, the operation of the data processing method according to the first embodiment of the present invention will be described. For example, in the case where two bus masters share one memory 13 as shown in FIG. 1 to access the memory, the address generator 11 transfers A to the read register 41 of the bus controller 14.
When the DR address is supplied, the address is sequentially shifted and held.

The ADW address from the data processing unit and the data associated with the ADW address are sequentially shifted and held in the write register 42. Among the ADR addresses sequentially shifted by this read register 41,
The ADR address located at the head and all the ADW addresses sequentially shifted by the write register 42 are compared by the address comparison circuit.

For example, as shown in FIG. 4A, the head ADR address of the read register 41 = 0010 and all the ADW addresses of the write register 42 = 0053,
0022, 0002, 00AA, 00BC, 0011 are compared. However, there is no match for 0010.
In this case, the data is read from the memory with the ADR address = 0010. In the data read at this time, the data read from the memory 13 is the data FI.
It is once written in the FO memory 15 and transferred to the data processing unit 12.

When the address is shifted by one,
As shown in (B), the first AD of the read register 41
R address = 0002, and this and write register 4
All 2 ADW addresses = 0053,0022,00
02, 00AA, 00BC, 0011 are compared. In this case, there are some that match 0002. In this case, for the first time, ADW address = ADR address = 000
2, DATA = FD is written in the memory 13,
At the same time as it is updated, it is written in the data FIFO memory 15.

Note that the write access becomes possible.
When read access does not occur, ADR address and A
This is either the case when the DW address matches and the data update of the memory 13 and the data transfer to the data processing unit 12 are executed at the same time, or the buffer of the write register 42 is in the overflow state. The data associated with the ADW address at this time is selected by the data selection circuit,
They are output to the memory 13 (first data processing method).

Further, as shown in FIG.
When the ADW address = 0002 that matches the address and DATA = FD associated therewith are output, the remaining ADW address = 00AA, 00 in the write register 42.
BC, 0011 and accompanying DATA = 14, D
E and D1 are packed in the higher order side. In addition, the data processing unit 1
2 sequentially processes the data in the data FIFO memory 15 while monitoring the data enable signal R / W of the data FIFO memory 15.

As a result, in the data processing unit 12, the data FIFO memory 15 is irrespective of the memory access status.
Can be read from and processed for data. Also,
By monitoring the ADR address and the ADW address via the bus control unit 14, it is possible to adjust the data write operation that prioritizes the data read operation. In this way, according to the data processing device of the first embodiment of the present invention, as shown in FIG. 2, the bus control unit 14 having the read register 41, the write register 42, the address comparison circuit 43 and the selector 44 is provided. Is provided.

Therefore, the registers 41 and 42 are used to
By collectively managing the DR and ADW addresses and monitoring the ADR address and the ADW address by the address comparison circuit 43, the data read operation can be prioritized over the data write operation, and the write operation can be adjusted. You can As a result, the read / write processing can be integrated and executed, and the read data from the memory 13 can be read continuously without being influenced by the sequential processing of the write operation like the conventional bus arbitration method. 12
Can be supplied to.

That is, according to the data processing method of the first embodiment of the present invention, on the one hand, the ADR address is sequentially held, and on the other hand, the ADW address and the data are sequentially held together, Among the ADR addresses, the ADR address held at the head position is compared with all the ADW addresses held sequentially on the other hand, and as a result, if there is no matching address, it is held at the head position. Output ADR address, and if there is a match, the ADW that matches the ADR address
The address and the data associated with the ADW address are output.

Therefore, the read access and the write access can be continuously performed, the time for bus arbitration is reduced as compared with the conventional example, the operation suspension period in each data processing block is reduced, and the data processing It is possible to increase the speed. If the read access and the write access have the same address, the read data is invalidated and new data is transferred to the memory 13 and the data FIFO memory 1.
Data can be efficiently updated by transferring the data.

(2) Description of Second Embodiment FIG. 5 shows an internal configuration diagram of the bus control unit of the data processing apparatus according to the second embodiment of the present invention. In the second embodiment, unlike the first embodiment, the number of register stages is reduced,
The read operation and the write operation are adjusted while monitoring the read address by reducing the address comparison target.

That is, as shown in FIG. 5, the bus control unit of the second data processing device of the present invention includes address shift registers (hereinafter simply referred to as read registers) 51, 52,
An address comparison circuit 53, a selector 54, a bus control signal generation circuit 55, and a data register 56 are provided. The read register 51 is a storage element that holds an ADR address that newly specifies a data read address of the memory. The read register 52 is the first A shifted from the register 51.
A storage element that holds a DR address. The ADR address is supplied from the address generator as in the first embodiment.

The address comparison circuit 53 includes both registers 51,
The ADR address stored in 52 is compared and the data selection signal SE is output to the selector 54. For example, the circuit 53
Outputs the signal SE = "H" level when the first ADR address and the next ADR address match, and outputs the signal SE = "L" level when the addresses do not match.

The selector 54 outputs either the first ADR address or the next ADR address based on the data update request signal SN and the data selection signal SE. The signal SN is, for example, a control signal that is supplied from the data processing unit and that updates data at the same storage address in the memory. Similar to the first embodiment, the bus control signal generation circuit 55 is connected to the bus 16 and adjusts the ADR address, the ADW address and the data to a predetermined potential and transmits them to the bus 16. The data register 56 is data to be written in the memory (DATA)
Is a memory element that holds The data is transferred from the data processing unit and rewritten at any time.

Next, the operation of the bus control unit will be described with respect to the data processing method according to the second embodiment of the present invention. For example, when the first ADR address is supplied from the address generation unit to the read register 51 as shown in FIG. 5, the ADR address is shifted and held in the register 52 of the next stage, and then the new ADR address is registered. Held at 51. Further, when there is data to be written in the memory, the data is transferred from the data processing unit to the register 56 and held therein.

In this state, the address comparison circuit 53 compares the first ADR address with the new ADR address. As a result, the data selection signal SE changes to the selector 55.
Is output to In the selector 54, the first ADR based on the data update request signal SN and the data selection signal SE.
Either the address or the new ADR address is output.

That is, as a result of comparing the two addresses, if the addresses do not match, the signal SE = "H".
The level becomes high, a new ADR address is selected, and the read operation is prioritized. As a result, the data processing unit executes the arithmetic processing based on the data read from the memory, that is, the arithmetic processing related to the data based on the ADR address stored in the register 52, regardless of the memory access status.

When a new ADR address is supplied to the register 51, the signal SN is asserted, and the addresses match each other, the signal SE becomes "L" level, and the first ADR from the selector 54. The address is selected as the ADW address, and the data held in association with the ADW address is output to the memory (second data processing method). As a result, the data update process is executed. At the same time, the data held in association with the ADW address is transferred to the data processing unit as the next processing data.

As described above, according to the data processor of the second embodiment of the present invention, as shown in FIG. 5, the read registers 51, 52, the address comparison circuit 53, the selector 54, and the bus control signal generator are generated. A bus controller having a circuit 55 is provided. Therefore, the registers 51 and 52 manage the preceding and following ADR addresses, and when the two addresses are compared by the address comparison circuit 53, if the addresses do not match, the first ADR address is selected and the read operation is performed. have priority. When the addresses match, a new ADR address can be selected as the ADW address, and the data held in association with the ADW address can be output to the memory.

As a result, the data read operation can be prioritized while monitoring a small number of ADR addresses.
The write operation can be adjusted. In addition, memory access can be performed continuously, data can be efficiently updated, and data processing can be speeded up.

[0050]

As described above, according to the data processing apparatus and the data processing method of the present invention, the data read operation is prioritized and the data write operation is adjusted while monitoring the read address and the write address. It Therefore, the write operation does not depend on the sequential processing as in the conventional example, and the read data from the memory can be supplied to the data processing section without interruption. Further, the memory access can be continuously performed, the time for bus arbitration is eliminated as compared with the conventional example, and the operation suspension period in each data processing block can be reduced. In addition, the data can be updated efficiently.

As a result, it is possible to improve the data processing capacity, and this contributes greatly to the provision of a data processing device capable of high-speed memory access.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a data processing device according to a first embodiment of the present invention.

FIG. 2 is an internal configuration diagram of a bus control unit according to the first embodiment of the present invention.

FIG. 3 is an internal configuration diagram of a register on the write side according to the first embodiment of the present invention.

FIG. 4 is a state transition diagram of the shift register according to the first embodiment of the present invention.

FIG. 5 is an internal configuration diagram of a bus control unit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a data processing device with a bus arbitration function according to a conventional example.

[Explanation of symbols]

 11 ... Address generation unit, 12 ... Data processing unit, 13 ... Memory, 14 ... Bus control unit, 15 ... Data FIFO memory, 16 ... Bus, 41 ... Data control shift register, 42 ... Memory control shift register, 42A ... Write address shift register, 42B ... Write data shift register, 43, 53 ... Address comparison circuit, 44, 422, 422, 54 ... Selector, 45, 55 ... Bus control signal generating section, 51, 52 ... Address shift register, 421, 423, 425 ... Memory circuit, ADR ... Read address, ADW ... Write address, SN ... Data update request signal, SE ... Data selection signal, R / W ... Data enable signal.

Claims (6)

[Claims] 1. A control unit that prioritizes a data read operation while monitoring a read address related to data read and a write address related to data write and adjusts the data write operation, wherein the control unit is a read Of the first register that sequentially shifts and holds addresses, the second register that sequentially shifts and holds the write address and data associated with the write address, and the read address that is sequentially shifted by the first register, An address comparison circuit that compares the read address located at the head with all the write addresses sequentially shifted by the second register and outputs a write address that matches the read address.
And a data selection circuit for selectively outputting data associated with a write address that matches the read address. 2. The second register packs the remaining write address and the data associated with the write address when the write address matching the read address and the data associated with the write address are output. The data processing device according to claim 1, wherein 3. The first control means for sequentially shifting and holding a read address designating a data read address of a memory, a second register for holding data to be written in the memory, and the first register. An address comparison circuit that outputs a data selection signal by comparing the read address initially held in the first and the newly held read address, and a signal requesting data update and the first based on the data selection signal. 2. The data processing apparatus according to claim 1, further comprising a data selection circuit that outputs one of the read address held in the memory and the newly held read address. 4. A data processing method, wherein priority is given to a data read operation while monitoring a read address related to data read and a write address related to data write, and the data write operation is adjusted. 5. On the one hand, a plurality of read addresses designating a read address of data are sequentially held, and on the other hand, a plurality of write addresses designating a write address of data and data to be written to the write address are sequentially attached. On the one hand, among the read addresses sequentially held on the one hand, the read address held at the head position is compared with all the write addresses held sequentially on the other hand, and the read address and all the write addresses are compared. As a result of comparing with the address,
If no address matches, the read address held at the head position is output. If there is a address match, the write address matching the read address and the write address are output. A data processing method, comprising: outputting accompanying data. 6. On the one hand, a read address designating a data read address of the memory is sequentially held, on the other hand, data to be written to the memory is held, and on the other hand, the first held read address and a new hold are newly held. When the two addresses are not matched as a result of comparing the two read addresses, the newly held read address is selected, and when the addresses match, the first held address is selected. A data processing method comprising: selecting a read address as a write address and outputting the held data in association with the write address.