JPH088352B2 - Heterojunction FET - Google Patents
Heterojunction FETInfo
- Publication number
- JPH088352B2 JPH088352B2 JP62233041A JP23304187A JPH088352B2 JP H088352 B2 JPH088352 B2 JP H088352B2 JP 62233041 A JP62233041 A JP 62233041A JP 23304187 A JP23304187 A JP 23304187A JP H088352 B2 JPH088352 B2 JP H088352B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- doped
- gate electrode
- gaas
- heterojunction fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔概要〕 化合物半導体装置に係り，特にIII/V族化合物半導体
を用いたヘテロ接合FETに関し， プロセス時の加熱及びその後の工程の加熱によるショ
ットキー特性の劣化を防ぐことを目的とし， ２次元電子ガス供給層としてInAlAs,ゲート電極とし
てAlを使用し，その間にGaAs層を挿入する構造をもって
構成する。The present invention relates to a compound semiconductor device, and more particularly, to a heterojunction FET using a III / V group compound semiconductor, which prevents deterioration of Schottky characteristics due to heating during a process and subsequent heating. For this purpose, InAlAs is used as the two-dimensional electron gas supply layer, Al is used as the gate electrode, and a GaAs layer is inserted between them.
〔産業上の利用分野〕 本発明は化合物半導体装置に係り，特にIII−Ｖ族化
合物半導体を用いたヘテロ接合FETに関し，プロセス時
の加熱及びその後パッケージ組み込み時までの加熱によ
るショットキー特性の劣化のないヘテロ接合FETを提供
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a heterojunction FET using a III-V group compound semiconductor, which is characterized by deterioration of Schottky characteristics due to heating during processing and subsequent heating up to package mounting. No heterojunction FET is provided.
従来,InP基板の上にバッファー層としてノンドープIn
AlAs層，チャネル層としてノンドープInGaAs層,2次元電
子ガス供給層（以下電子供給層と略）としてSiドープIn
AlAs層を積み，その上にゲート電極としてAl金属を配し
たゲート・チャネル構造を有する高電子移動度トランジ
スタ（HEMT）が知られている。Conventionally, non-doped In was used as a buffer layer on the InP substrate.
AlAs layer, non-doped InGaAs layer as channel layer, Si-doped In as two-dimensional electron gas supply layer (hereinafter referred to as electron supply layer)
A high electron mobility transistor (HEMT) having a gate-channel structure in which an AlAs layer is stacked and an Al metal is arranged as a gate electrode on the AlAs layer is known.
ところが，プロセス時の加熱及びその後のパッケージ
組込み時に至る途中の加熱により，ゲート電極のAlがす
ぐ下のsiドープInAlAs層と反応して界面に変質を来す結
果，ショットキー特性が劣化するという問題があった。However, due to the heating during the process and the heating during the process of assembling the package after that, Al of the gate electrode reacts with the Si-doped InAlAs layer immediately below and deteriorates the interface, resulting in the deterioration of the Schottky characteristic. was there.
AlとInAlAsのショットキー接合は160℃以上で合金化
する。しかるにプロセス時及びその後の工程で，もっと
高い温度にさらされることがあるのでショットキー接合
界面が変質する。そこでこの変質を避けるための手段を
講じようとするのが，本発明の目的である。The Al-InAlAs Schottky junction alloys at 160 ° C and above. However, during the process and subsequent steps, it may be exposed to higher temperatures, and the Schottky junction interface deteriorates. Therefore, it is an object of the present invention to take measures to avoid this deterioration.
第１図は本発明の構造を示す。化合物半導体の基板１
の上にバッファー層として第１のノンドープ化合物半導
体，チャネル層として第２のノンドープ化合物半導体
層，スペーサーとして第３のノンドープ化合物半導体
層，電子供給層としてSiドープInAlAs層，拡散防止層と
してGaAs層を積層し，その上にゲート電極としてAlを配
した構造をとる。FIG. 1 shows the structure of the present invention. Compound semiconductor substrate 1
A first non-doped compound semiconductor as a buffer layer, a second non-doped compound semiconductor layer as a channel layer, a third non-doped compound semiconductor layer as a spacer, a Si-doped InAlAs layer as an electron supply layer, and a GaAs layer as a diffusion prevention layer. It has a structure in which Al is stacked as a gate electrode on top of it.
本発明の特徴とするところは,III−Ｖ族化合物半導体
を用いたヘテロ接合FETにおいて，電子供給層としてInA
lAs,ゲート電極としてAlを使用し，その間にGaAs層を挿
入することにあり，これによって上記問題点は解決され
る。A feature of the present invention is that, in a heterojunction FET using a III-V group compound semiconductor, InA is used as an electron supply layer.
The problem is to use lAs and Al as the gate electrode and insert a GaAs layer between them, which solves the above problems.
GaAs層の挿入はゲート電極と電子供給層の間でAlが相
互拡散するのを防ぐ。電子供給層としてGaAs,ゲート電
極としてAlを使用したショットキー接合は500℃付近ま
で昇温してもショットキー特性は劣化しない。そこで上
記変質を避けるためにAl層とInAlAs層の間にGaAs層を挿
入することにした。この場合は新たにGaAs層とInAlAs層
の間の格子不整から生じる内部歪が問題となるが,GaAs
層の厚さを転位の発生しない数十Å程度に抑えればその
影響は小さい。The insertion of the GaAs layer prevents Al from interdiffusing between the gate electrode and the electron supply layer. The Schottky junction using GaAs as the electron supply layer and Al as the gate electrode does not deteriorate in Schottky characteristics even if the temperature is raised to around 500 ° C. Therefore, we decided to insert a GaAs layer between the Al layer and the InAlAs layer to avoid the above alteration. In this case, the internal strain newly caused by the lattice mismatch between the GaAs layer and the InAlAs layer becomes a problem.
The effect is small if the layer thickness is suppressed to several tens of liters at which dislocations do not occur.
本発明の実施例を次に示す。InP基板１上にバッファ
層２としてノンドープInAlAsを3000Å，チャネル層３と
してノンドープInGaAsを1000Å，スペーサー４としてノ
ンドープInAlAsを50Å，電子供給層５としてSiドープし
たＮ−InAlAs（Ｎ＝１×1018cm-3）を500Å成長させ
た。その上に拡散防止層６としてSiドープしたｎ−GaAs
（ｎ＝１×1018cm-3）を30Å成長させた。その上にAlを
真空蒸着しゲート電極を形成した。最後にソース電極８
及びドレイン電極９を形成し，表面不活性化膜10をつけ
た。Examples of the present invention will be described below. On the InP substrate 1, 3000 Å non-doped InAlAs is used as the buffer layer 2, 1000 Å non-doped InGaAs is used as the channel layer 3, 50 Å non-doped InAlAs is used as the spacer 4, and Si-doped N-InAlAs (N = 1 × 10 18 cm) is used as the electron supply layer 5. -3 ) was grown to 500Å. Si-doped n-GaAs as a diffusion prevention layer 6 thereon
(N = 1 × 10 18 cm −3 ) was grown at 30Å. Al was vacuum-deposited thereon to form a gate electrode. Finally the source electrode 8
A drain electrode 9 was formed, and a surface passivation film 10 was attached.
この構成のショットキー接合を有するFETは，拡散防
止層６を設けない従来構造のショットキー接合を有する
FETに比較して良好なショットキー特性を示した。The FET having the Schottky junction of this structure has the Schottky junction of the conventional structure in which the diffusion prevention layer 6 is not provided.
The Schottky characteristic was better than that of the FET.
なお，実施例では拡散防止層としてSiドープｎ−GaAs
層を使用したが，必ずしもsiドープは必要でなく,GaAs
でもよい。In the embodiment, Si-doped n-GaAs is used as the diffusion prevention layer.
Layer was used, but si-doping is not necessary, GaAs
But it is okay.
GaAs層を拡散防止層として挿入することにより，ソー
ス，ドレイン等のオーミックコンタクトの熱処理や，ダ
イボンド等の熱プロセスに伴うゲート電極のAlとチャネ
ル層InAlAsの間の相互拡散を抑えることができ，ショッ
トキー特性の劣化を防ぐことができる。By inserting the GaAs layer as the diffusion prevention layer, it is possible to suppress the interdiffusion between Al of the gate electrode and the channel layer InAlAs due to the heat treatment of ohmic contacts such as the source and drain and the thermal process such as die bonding. It is possible to prevent deterioration of key characteristics.
本発明により，良好なショットキー特性を有するヘテ
ロ接合FETを提供することができる。The present invention can provide a heterojunction FET having good Schottky characteristics.
第１図は本発明の構造を示す図である。 図において， １は基板， ２はバッファー層， ３はチャネル層， ４はスペーサー ５は電子供給層 ６は拡散防止層， ７はゲート電極 ８はソース電極 ９はドレイン電極 10は表面不活性化膜 である。 FIG. 1 is a diagram showing the structure of the present invention. In the figure, 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a spacer, 5 is an electron supply layer, 6 is a diffusion prevention layer, 7 is a gate electrode 8, 8 is a source electrode, 9 is a drain electrode, and 10 is a surface passivation film. Is.
Claims (1)
合FETにおいて,2次元電子ガス供給層としてSiドープInA
lAs,ゲート電極としてAlを使用し，その間にGaAs層を挿
入することを特徴とするヘテロ接合FET。1. In a heterojunction FET using a III-V group compound semiconductor, Si-doped InA is used as a two-dimensional electron gas supply layer.
A heterojunction FET characterized by using AlAs and Al as the gate electrode and inserting a GaAs layer between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233041A JPH088352B2 (en) | 1987-09-17 | 1987-09-17 | Heterojunction FET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62233041A JPH088352B2 (en) | 1987-09-17 | 1987-09-17 | Heterojunction FET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6474765A JPS6474765A (en) | 1989-03-20 |
| JPH088352B2 true JPH088352B2 (en) | 1996-01-29 |
Family
ID=16948874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62233041A Expired - Fee Related JPH088352B2 (en) | 1987-09-17 | 1987-09-17 | Heterojunction FET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088352B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH088354B2 (en) * | 1989-03-28 | 1996-01-29 | 松下電器産業株式会社 | Heterojunction field effect transistor |
| EP0452054B1 (en) * | 1990-04-11 | 1995-07-12 | Hughes Aircraft Company | HEMT structure with passivated structure |
| US5055891A (en) * | 1990-05-31 | 1991-10-08 | Hewlett-Packard Company | Heterostructure transistor using real-space electron transfer |
| JP3086748B2 (en) * | 1991-07-26 | 2000-09-11 | 株式会社東芝 | High electron mobility transistor |
| US5488237A (en) * | 1992-02-14 | 1996-01-30 | Sumitomo Electric Industries, Ltd. | Semiconductor device with delta-doped layer in channel region |
| JP2001044417A (en) * | 1999-07-26 | 2001-02-16 | Fujitsu Ltd | Semiconductor device |
-
1987
- 1987-09-17 JP JP62233041A patent/JPH088352B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6474765A (en) | 1989-03-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |