JPH088358B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention forms a low-concentration diffusion layer and a high-concentration diffusion layer in a self-aligned manner to increase the breakdown voltage of a MIS (metal-insulating film-semiconductor) type field effect transistor. The present invention relates to a method for manufacturing a semiconductor device that enables the above.

Conventional technology With the progress of LSI technology, semiconductor integrated circuits have become higher in performance and larger in scale, and the dimensions of elements have become smaller and smaller. In particular, the size of the gate electrode of a MIS type field effect transistor (hereinafter abbreviated as MIS type transistor) is 0.8 to 0.8 mm as typified by a 1 Mbit dynamic memory (1MDRAM).
1.2 μm is used.

With the miniaturization of the element size, the breakdown voltage of the element against the power supply voltage and the short channel effect have advanced, and it has become difficult to stabilize the characteristics in the conventional element structure.

Therefore, the so-called LDD (Lightly Doped Drain), in which the drain of the MIS transistor is composed of a low-concentration diffusion layer
Structures have become popular.

Two examples of a conventional method for manufacturing an MIS type transistor having an LDD structure are shown in FIGS. 2 (a) to (c) and FIGS. 3 (a) to (c) using sectional views. 2 (a) to (c) and FIGS. 3 (a) to (c) all show the case where a P-type substrate is used.

 The first example is shown in FIG.

As shown in FIG. 2A, the P-type substrate 1 is provided with a gate insulating film.
2. After forming the gate electrode 3, the N type low concentration diffusion layer 4 is formed by the ion implantation method.

Next, as shown in FIG. 2B, a silicon dioxide film 5 is formed by a chemical vapor deposition method.

Next, as shown in FIG. 2 (c), the silicon dioxide film 5 is formed on the sidewalls of the gate electrode 3 and the gate insulating film 2 by the well-known anisotropic etching using the reactive ion etching technique. After processing so as to leave 5 ', the N-type high-concentration diffusion layer 6 is formed by the ion implantation method. Next, the interlayer insulating film 9 is formed and heat treatment or the like is performed to form an MIS type transistor having an LDD structure.

 The second example is shown in FIG.

As shown in FIG. 3A, a gate insulating film is formed on the P-type substrate 1.
2, a gate electrode 3, and then a silicon nitride film 7 which is an oxidation resistant film is formed, and then an N type low concentration diffusion layer 4 is formed by an ion implantation method.

Next, as shown in FIG. 3B, heat treatment is applied to the gate electrode 3, the side wall of the gate insulating film 2 and the surface of the low concentration diffusion layer 4 to form a silicon dioxide film 5.

Next, as shown in FIG. 3C, the N-type high concentration diffusion layer 6 is formed.
Are formed by an ion implantation method. Next, the interlayer insulating film 9 is formed and heat treatment or the like is performed to form an MIS type transistor having an LDD structure.

Problems to be Solved by the Invention In the case of the first example shown in FIG. 2, the etching time in the step of forming the silicon dioxide film 5 ′ on the side walls of the gate electrode 3 and the gate insulating film 2 by the etching technique,
Due to the variation in the etching rate accuracy, the film thickness of the silicon dioxide film 5'on the side wall varies, and the variation in the characteristics of the MIS transistor has been a problem.

In the case of the second example shown in FIG. 3, the gate electrode 3
Since the silicon nitride film 7 is formed thereover, the dimensional accuracy of the gate electrode 3 is likely to vary, and the variation in MIS type transistor characteristics has been a problem.

The present invention has been made in view of the above problems, and stably forms a silicon dioxide film on a side wall of a gate electrode or the like,
Furthermore, the present invention provides a method for manufacturing a semiconductor device in which a MIS transistor having an LDD structure is formed in a self-aligning manner without deteriorating the dimensional accuracy of the gate electrode.

Means for Solving the Problems In order to achieve the above object, the present invention provides a step of forming a gate insulating film on a semiconductor substrate, a gate electrode subjected to high-concentration impurity diffusion, and a conductive type opposite to the semiconductor substrate. After the low-concentration diffusion layer is formed, a heat treatment is performed in an atmosphere containing ammonia (NH ₃ ) gas, and then a heat treatment is performed in an atmosphere containing oxygen (O ₂ ) gas, and then the low-concentration diffusion layer is formed. There is a step of forming a diffusion layer having a conductivity type opposite to that of the substrate having a higher concentration.

Action According to the present invention, it is possible to perform the operation in an ammonia (NH ₃ ) gas atmosphere.
By heat treatment at about 00 ℃, the surface concentration is 1 × 10 ¹⁸ cm
^{On the} surface of the low concentration diffusion layer of ^-3 or less, an oxidation resistant film supposed to be a silicon nitride film is formed, but the concentration is 1 × 10 ¹⁸ cm.
A high-concentration diffusion layer surface of about ^-3 or more cannot form an oxidation resistant film, and a high-concentration diffusion layer of 1 × 10 ¹⁸ cm ^-3 or more is formed on the gate electrode layer. By forming the low-concentration diffusion layer of ¹⁸ cm ⁻³ or less, it becomes possible to selectively form the silicon dioxide film on the surface of the gate electrode and its sidewall, and further on the silicon dioxide film.

According to the method for manufacturing a semiconductor device of the present invention, it is not necessary to etch the silicon dioxide film on the side wall of the gate electrode layer or the like, and the dimensional accuracy can be formed with higher accuracy.

Example Hereinafter, a specific example will be described with reference to a cross-sectional view in FIG.
~ (D).

In FIG. 1A, a silicon dioxide film which is a gate insulating film 2 and a polycrystalline silicon film which is a gate electrode film 3 are sequentially laminated on a P-type semiconductor substrate 1 and heat-treated in a phosphine (PH ₃ ) gas atmosphere. After applying the lithography technology,
The gate portion of the MIS type transistor is formed by using the etching technique. Next, the N-type low-concentration diffusion layer 4 is formed by using the ion implantation technique by self-alignment.

In this embodiment, the thickness of the silicon dioxide film that is the gate insulating layer 2 is 20 nm, and the thickness of the polycrystalline silicon film of the gate electrode 3 is 400 nm. The heat treatment conditions in a phosphine (PH ₃ ) gas atmosphere were a temperature of 1000 ° C. and a time of 20 minutes, and the impurity concentration of the polycrystalline silicon film when subjected to the treatment was set to about 3 × 10 ²⁰ cm ⁻³ . Further, phosphorus (P ⁺ ) ions were implanted as impurities in the N-type low-concentration diffusion layer 4 to a concentration of 2 × 10 ¹⁷ cm ^-3 .

Next, as shown in FIG. 1 (b), ammonia (NH ₃ )
After heat treatment is performed in a gas atmosphere to form a silicon nitride film 8 which is an oxidation resistant coating on the surface of the N-type low concentration diffusion layer 4, thermal oxidation is performed in an atmosphere containing oxygen (O ₂ ) gas. A silicon dioxide film 5 ′ is formed on the gate electrode 3 and its side wall and also on the side wall of the gate insulating film 2.

In this example, the ammonia (NH ₃ ) gas heat treatment conditions were a pressure of 300 mTorr, a temperature of 750 ° C., and a treatment time of 5 minutes. The thermal oxidation treatment conditions are a mixed gas atmosphere of oxygen (O ₂ ) gas and hydrogen (H ₂ ) gas, a temperature of 900 ° C., a treatment time of 30 minutes, and a silicon dioxide film 5 ′ on the gate electrode 3.
The film thickness was 180 nm.

Next, as shown in FIG. 1C, the N-type high concentration diffusion layer 6 was formed by using the ion implantation technique by self-alignment, and then the interlayer insulating film 9 was formed by the vapor phase epitaxy method.

In this embodiment, as the N-type high-concentration diffusion layer 6, heso-ion implantation is performed, the impurity concentration is 8 × 10 ¹⁹ cm ⁻³ , the diffusion length (x
j) 0.35 μm. Further, as the interlayer insulating film 9, a silicon dioxide film (BPSG film) containing boron and phosphorus ions is used.
8 μm.

Next, as shown in FIG. 1 (d), the wiring layer 10 and the protective film 11 were formed at predetermined portions by using the well-known diffusion technique, vapor phase growth technique, lithography technique, and etching technique.

In this embodiment, the wiring layer 10 is an aluminum alloy film 0.8 μm, and the protective film 11 is a silicon nitride film 0.8 μm.

In the present embodiment, the LDD structure using the P-type substrate has been described, but it is needless to say that it can be used for the N-type substrate and can be used even when a P-type or N-type well layer is formed in the substrate.

Further, although a silicon dioxide film is used as the gate insulating film 2, even in a laminated structure of two layers and three layers having different compositions,
It goes without saying that the same effect is obtained, and even if a refractory metal other than the polycrystalline silicon film is used as the gate electrode 3, the same effect is obtained.

Further, phosphine (PH ₃ ) gas was used for forming the high temperature impurities in the gate electrode layer 3, but gases such as phosphorus oxychloride (POCl ₃ ) gas containing phosphorus ions, boron oxide (B ₂ O ₃ ) containing boron ions, etc. It goes without saying that the same effect can be obtained by using.

Effects of the Invention As described above, a silicon dioxide film is formed on the sidewalls of the gate electrode and the gate insulating film by performing a heat treatment in an ammonia (NH ₃ ) gas atmosphere after selectively forming a portion having a different impurity concentration. The MIS type transistor can be formed with high precision and has a high precision LDD structure.

[Brief description of drawings]

1 (a) to 1 (d) are sectional views showing a sectional view of an embodiment of the present invention in the order of steps, FIGS. 2 (a) to 2 (c) and 3rd.
(A)-(c) is each sectional drawing which showed the sectional view of the conventional manufacturing method in order of process. 1 ... P-type silicon substrate, 2 ... gate insulating film (silicon dioxide film), 3 ... gate electrode (polycrystalline silicon film), 4 ... N-type low-concentration diffusion layer, 5,5 '... silicon dioxide Film, 6 ... N-type high-concentration diffusion layer, 7,8 ... Silicon nitride film, 9 ... Interlayer insulating film (BPSG film), 10 ... Metal wiring (aluminum alloy), 11 ... Protective film (silicon nitride) film).

Claims (1)

[Claims] 1. A step of forming an insulating film on a one-conductivity-type semiconductor substrate and forming a gate electrode subjected to high-concentration diffusion,
After forming a low-concentration diffusion layer of opposite conductivity type on the surface of the semiconductor substrate, heat treatment is performed in an atmosphere containing ammonia (NH ₃ ) gas, and heat treatment is performed in an atmosphere containing oxygen (O ₂ ) gas. And a step of forming a diffusion layer of a conductivity type opposite to that of the substrate having a concentration higher than that of the low concentration diffusion layer.