JPH088382A - Manufacture of resin sealed semiconductor device - Google Patents
Manufacture of resin sealed semiconductor deviceInfo
- Publication number
- JPH088382A JPH088382A JP14142394A JP14142394A JPH088382A JP H088382 A JPH088382 A JP H088382A JP 14142394 A JP14142394 A JP 14142394A JP 14142394 A JP14142394 A JP 14142394A JP H088382 A JPH088382 A JP H088382A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plating layer
- tin
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 title claims abstract description 8
- 229920005989 resin Polymers 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000007747 plating Methods 0.000 claims abstract description 21
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000011261 inert gas Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Landscapes
- Injection Moulding Of Plastics Or The Like (AREA)
- Electroplating Methods And Accessories (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止型半導体装置の
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置の製造方法
は、半導体チップを搭載して樹脂封止したリードフレー
ムの樹脂体より導出した外部リードの表面に電気めっき
法で錫−鉛めっき層を形成した後、水洗して９０〜１０
０℃の乾燥空気で１５〜３０分間程度乾燥させ、しかる
後、タイバーカット、リード切断、リード成型等のリー
ド加工を行っていた。2. Description of the Related Art A conventional method for manufacturing a resin-encapsulated semiconductor device is a tin-lead plating layer formed by electroplating on the surface of an external lead derived from a resin body of a lead frame on which a semiconductor chip is mounted and resin-encapsulated. After forming, wash with water to 90-10
It was dried with dry air at 0 ° C. for about 15 to 30 minutes, and thereafter, lead processing such as tie bar cutting, lead cutting, and lead molding was performed.
【０００３】[0003]
【発明が解決しようとする課題】この従来の樹脂封止型
半導体装置の製造方法では、錫−鉛めっき層の組成比が
８：２の場合、その硬度は８Ｈｖ（マイクロビッカース
硬度）程度であり、リード加工の際に切断又は成型用の
金型でめっき層が削れて半田屑が発生し、リード間短絡
を生じるという問題があった。In this conventional method of manufacturing a resin-encapsulated semiconductor device, when the composition ratio of the tin-lead plating layer is 8: 2, the hardness is about 8 Hv (micro Vickers hardness). However, there has been a problem in that, during lead processing, the plating layer is scraped off by a die for cutting or molding, solder scraps are generated, and a short circuit occurs between leads.
【０００４】[0004]
【課題を解決するための手段】本発明の樹脂封止型半導
体装置の製造方法は、半導体チップを搭載して樹脂封止
したリードフレームの樹脂体より導出した外部リードの
表面に錫−鉛めっき層を形成する工程と、前記リードフ
レームを不活性ガス中で熱処理し錫−鉛めっき層の硬度
を高める工程とを含んで構成される。According to a method of manufacturing a resin-sealed semiconductor device of the present invention, a surface of an external lead led out from a resin body of a lead frame on which a semiconductor chip is mounted and resin-sealed is tin-lead plated. It comprises a step of forming a layer and a step of heat treating the lead frame in an inert gas to increase the hardness of the tin-lead plating layer.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００６】図１（ａ）〜（ｄ）は本発明の一実施例を
説明するための工程順に示した断面図である。1 (a) to 1 (d) are sectional views showing the steps in order to explain one embodiment of the present invention.
【０００７】まず、図１（ａ）に示すように、４２合金
又は銅合金等からなるリードフレームのアイランドに半
導体チップ１を搭載して樹脂体２により樹脂封止し、樹
脂体２より外部リード３を導出する。First, as shown in FIG. 1A, a semiconductor chip 1 is mounted on an island of a lead frame made of 42 alloy or copper alloy, and is sealed with a resin body 2. 3 is derived.
【０００８】次に、図１（ｂ）に示すように、樹脂体２
より導出された外部リード３の表面に電気めっき法によ
り錫と鉛の組成比が８：２である錫−鉛めっき層４を１
０〜２０μｍの厚さに形成した後、水洗してリードフレ
ームを清浄化する。Next, as shown in FIG. 1B, the resin body 2
A tin-lead plating layer 4 having a tin-lead composition ratio of 8: 2 is formed on the surface of the external lead 3 thus derived by electroplating.
After forming to a thickness of 0 to 20 μm, the lead frame is cleaned by washing with water.
【０００９】次に、リードフレームを１００℃未満の窒
素ガス等の乾燥不活性ガス中で乾燥させた後温度を１０
０〜２００℃に上昇して５〜７時間の熱処理を行い、錫
−鉛めっき層４を硬化させる。ここで、錫−鉛めっき層
４は錫−鉛合金の結晶化により硬化すると考えられる。Next, the lead frame is dried in a dry inert gas such as nitrogen gas at a temperature of less than 100.degree.
The temperature is raised to 0 to 200 ° C. and heat treatment is performed for 5 to 7 hours to cure the tin-lead plating layer 4. Here, it is considered that the tin-lead plating layer 4 is hardened by crystallization of the tin-lead alloy.
【００１０】次に、図１（ｃ）に示すように、タイバー
カットおよびリード切断加工を行いリードフレームから
切離す。Next, as shown in FIG. 1C, tie bar cutting and lead cutting processing are performed to separate the lead frame from the lead frame.
【００１１】次に、図１（ｄ）に示すように、外部リー
ド３をＪ字形に成型してＰＬＣＣを形成する。Next, as shown in FIG. 1D, the external leads 3 are molded into a J shape to form a PLCC.
【００１２】図２は加熱温度を変えた場合の熱処理時間
とめっき層のビッカース硬度の関係を示す図である。FIG. 2 is a diagram showing the relationship between the heat treatment time and the Vickers hardness of the plating layer when the heating temperature is changed.
【００１３】図２に示すように、１００〜２００℃で５
〜７時間の熱処理の場合に１００％の錫めっき層の硬度
１３Ｈｖに匹敵する硬度を得ることができ、錫−鉛めっ
き層の耐摩耗性を向上させ、リード加工時のめっき層の
削れ屑の発生を抑えることができる。As shown in FIG. 2, 5 at 100 to 200 ° C.
In the case of heat treatment for up to 7 hours, it is possible to obtain a hardness comparable to the hardness 13Hv of 100% of the tin plating layer, improve the wear resistance of the tin-lead plating layer, and remove the scraps of the plating layer during lead processing. Occurrence can be suppressed.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、樹脂封止
したリードフレームの外部リードに錫−鉛めっき層を形
成した後不活性ガス雰囲気中で加熱処理することによ
り、めっき層を硬化させ、その後のリード加工工程にお
けるめっき層の削れ屑の発生を抑えることができるとい
う効果を有する。As described above, according to the present invention, the tin-lead plating layer is formed on the outer lead of the resin-sealed lead frame, and then the heat treatment is performed in the inert gas atmosphere to cure the plating layer. Therefore, it is possible to suppress the generation of scraps of the plating layer in the subsequent lead processing step.
【図１】本発明の一実施例を説明するための工程順に示
した断面図。1A to 1D are cross-sectional views showing a process sequence for explaining an embodiment of the present invention.
【図２】本発明の熱処理条件とめっき層の硬度との関係
を示す図。FIG. 2 is a diagram showing a relationship between heat treatment conditions of the present invention and hardness of a plated layer.
１ 半導体チップ ２ 樹脂体 ３ 外部リード ４ 錫−鉛めっき層 1 Semiconductor Chip 2 Resin Body 3 External Lead 4 Tin-Lead Plating Layer
Claims (2)
ードフレームの樹脂体より導出した外部リードの表面に
錫−鉛めっき層を形成する工程と、前記リードフレーム
を不活性ガス中で熱処理し錫−鉛めっき層の硬度を高め
る工程とを含むことを特徴とする樹脂封止型半導体装置
の製造方法。1. A step of forming a tin-lead plating layer on the surface of an external lead led out from a resin body of a lead frame on which a semiconductor chip is mounted and resin-sealed, and the lead frame is heat-treated in an inert gas. And a step of increasing the hardness of the tin-lead plating layer.
求項１記載の樹脂封止型半導体装置の製造方法。2. The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the heat treatment temperature is 100 to 200 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14142394A JPH088382A (en) | 1994-06-23 | 1994-06-23 | Manufacture of resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14142394A JPH088382A (en) | 1994-06-23 | 1994-06-23 | Manufacture of resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH088382A true JPH088382A (en) | 1996-01-12 |
Family
ID=15291656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14142394A Pending JPH088382A (en) | 1994-06-23 | 1994-06-23 | Manufacture of resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088382A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081206A (en) * | 2007-09-25 | 2009-04-16 | Koa Corp | Method of manufacturing resistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102386A (en) * | 1991-03-29 | 1993-04-23 | Daido Steel Co Ltd | High strength lead frame material and manufacture thereof |
| JPH05243452A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Surface mount semiconductor device and manufacturing method thereof |
-
1994
- 1994-06-23 JP JP14142394A patent/JPH088382A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05102386A (en) * | 1991-03-29 | 1993-04-23 | Daido Steel Co Ltd | High strength lead frame material and manufacture thereof |
| JPH05243452A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Surface mount semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081206A (en) * | 2007-09-25 | 2009-04-16 | Koa Corp | Method of manufacturing resistor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960910 |