JPH088421A - Semiconductor device and solid-state imaging device - Google Patents

Abstract

(57) [Abstract] [Objective] In the horizontal output gate section at the final stage of the horizontal transfer register in the CCD solid-state imaging device, without increasing manufacturing steps such as ion implantation of impurities, and without applying a bias from the outside, Enables potential adjustment under the gate. [Structure] In a horizontal output gate section HOG at a subsequent stage of a horizontal transfer register in a CCD solid-state imaging device, an Al film 34 is formed on a polycrystalline silicon film 33 forming a gate electrode 32.
A junction 35 is formed, and the thickness of the polycrystalline silicon film 33 is controlled to adjust the potential under the horizontal output gate portion HOG by the polycrystalline silicon film 33 and the junction 35 so as to set an optimum potential. To configure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrode-insulator-semiconductor structure and a solid-state image pickup device.

[0002]

2. Description of the Related Art FIGS. 5 and 6 show a horizontal transfer register of a conventional CCD solid-state image sensor and its output section. This C
A horizontal transfer register 1 having a CCD structure in a CD solid-state image sensor is provided on a transfer channel region 3 of a first conductivity type, for example, n type, formed on a main surface of a semiconductor substrate 2 with a gate insulating film 4 made of a SiO ₂ film or the like interposed therebetween. A plurality of first transfer electrodes 5A made of a first-layer polycrystalline silicon film and second transfer electrodes 5B made of a second-layer polycrystalline silicon film are arranged alternately along the transfer direction.

In this horizontal transfer register 1, every two adjacent transfer electrodes 5A and 5B connected to each other are taken as one set, and every other set of transfer electrodes 5 [5A, 5B] and the other one.
Two-phase horizontal drive pulses φH ₁ and φH ₂ are applied to every other pair of transfer electrodes 5 [5A, 5B]. In the transfer channel region 3 below each second transfer electrode 5B, the second
A conductive type or p-type semiconductor region 6 is formed by, for example, ion implantation of impurities, whereby a storage portion using the first transfer electrode 5A as a storage electrode and the second transfer electrode 5 are formed.
A transfer portion having a transfer portion having B as a transfer electrode is formed. 16A and 16B respectively correspond to 1
It is an Al wiring connected to the end portion of _every other transfer electrode 5, and horizontal drive pulses φH ₁ and φH ₂ are applied through it. Reference numerals 16a and 16b denote contact portions.

After the final transfer section of the horizontal transfer register 1, a horizontal output gate section HOG formed by forming a gate electrode 8 made of, for example, a second-layer polycrystalline silicon film via a gate insulating film 4 is formed. A floating diffusion region FD formed of an n-type semiconductor region serving as a charge-voltage conversion unit is formed in the subsequent stage. Horizontal output gate unit HOG
Is connected to the end of the gate electrode away from the horizontal transfer register 1 via the contact portion 15a.
A fixed output gate voltage V _HOG or a ground potential (GND) is applied through. The floating diffusion region FD is connected to the output amplifier 17. t ₁ is an output terminal.

Further, a reset drain region 9 composed of an n-type semiconductor region is provided, and a reset gate portion 10 is provided between the reset drain region 9 and the floating diffusion region FD. Reset drain region 9
Is connected to the Al wiring 1 via a contact portion 13a.
The reset voltage V _RD (for example, the power supply voltage V _DD ) is applied through 3.

A reset pulse φ _RG is applied to the reset gate portion 10 through an Al wiring 14 connected to one end of a gate electrode 11 made of, for example, a second-layer polycrystalline silicon film via a contact portion 14a.

In this CCD solid-state image pickup device, as shown by the potential 19 in FIG.
The signal charges are transferred by the phase drive pulses φH ₁ and φH ₂ , and the signal charges for each pixel are transferred to the floating diffusion region FD through the horizontal output gate unit HOG. And the floating diffusion area FD
The voltage according to the signal charge transferred to the output amplifier 17 is supplied to the output amplifier 17, and the CCD output according to the signal charge is read from the terminal t ₁ .

After the signal charge for one pixel is read out,
The reset gate pulse φ _RG is applied, the reset gate unit 10 is turned on, and the floating diffusion region F
The signal charge of D is swept out to the reset drain region 9,
The potential of the floating diffusion region FD is reset to the potential of the reset drain region 9.

By the way, the conventional horizontal output gate HOG
In the above, the potential φa under the gate portion, that is, the potential barrier Δφ is adjusted by the impurity region 7 by the impurity ion implantation or by applying an external bias. When the impurity region 7 is formed, a gate potential (GND) is applied to the gate electrode,
When the impurity region 7 is not formed, for example, a fixed positive external bias V _HOG is applied.

The potential barrier Δφ of the horizontal output gate portion HOG is the floating diffusion region F.
The dynamic range of D and the floating diffusion region FD from the transfer unit at the final stage of the horizontal transfer register 1
The optimum value is determined in consideration of the charge transfer to the battery.

That is, if the potential φa under the horizontal output gate section HOG is too deep, the signal charge will be transferred to the horizontal output gate section H.
If it flows back to the OG, and if the potential φa is too shallow, the amplitude of the voltage applied to the transfer section at the final stage becomes too large.

[0012]

By the way, in the horizontal output gate portion HOG, when the potential under the output gate is adjusted by ion implantation of impurities, a step of forming another portion where the amount of impurities is, for example, horizontal transfer. Register 1
There is no problem if it can be used also in the step of forming the p-type semiconductor region 6 for forming the potential barrier under the second transfer electrode (transfer electrode) 5B, but if it cannot be used, a dedicated mask and ion implantation step are required. Become.

Further, the potential under the horizontal output gate portion HOG is adjusted from the outside by a fixed bias, that is, the gate voltage V.
_In the method of applying _HOG , _needless to say, an external power source is required, and since the horizontal output gate portion HOG has a small electrostatic capacitance, electrostatic breakdown is likely to occur, which is not preferable in terms of reliability.

On the other hand, in an insulated gate field effect transistor (MIS transistor) having a polycrystalline silicon gate electrode, for example, a predetermined impurity is ion-implanted into a channel region when the threshold voltage V _th under the gate is adjusted. However, also in this case, a mask for adjustment and an ion implantation step are separately required.

In view of the above points, the present invention provides a semiconductor element having an electrode-insulator-semiconductor structure, a potential under the gate (eg, MIS) without increasing the number of manufacturing steps.
The present invention provides a semiconductor element in which the threshold voltage V _th ) of the type transistor can be set to a desired value.

According to the present invention, in the solid-state image sensor, the potential under the horizontal output gate section at the final stage of the horizontal transfer register can be set to a desired value without increasing the manufacturing process or applying an external bias. Is provided.

[0017]

A semiconductor element according to the first aspect of the present invention has a gate electrode 55 on a semiconductor substrate 51 via a gate insulating film 54, and a polycrystalline silicon film 56 constituting the gate electrode 55. A junction 58 with the Al film 57 is formed thereon, and the potential under the gate electrode 55 is set by the polycrystalline silicon film 56 and the junction 58.

The second aspect of the present invention is the semiconductor element of the first aspect of the invention, in which the potential under the gate electrode 55 is adjusted by the film thickness d ₂ of the polycrystalline silicon film 56.

In the solid-state image sensor according to the third aspect of the present invention, the polycrystalline silicon film 33 forming the gate electrode 32 in the horizontal output gate section HOG at the subsequent stage of the horizontal transfer register 22.
A junction 35 with the Al film 34 is formed on the upper portion, and a potential φa under the horizontal output gate portion HOG is set by the polycrystalline silicon film 33 and the junction 35.

According to a fourth aspect of the present invention, in the solid-state image pickup device according to the third aspect, the potential φa under the horizontal output gate portion HOG is adjusted by the film thickness d ₁ of the polycrystalline silicon film 33.

[0021]

According to the first aspect of the present invention, the junction 5 with the Al film 57 is formed on the polycrystalline silicon film 56 forming the gate electrode 55.
8 is formed, the potential under the gate electrode 55 shifts due to the work function difference between the polycrystalline silicon film 56 and the junction portion 58 as compared with the case of one layer of the polycrystalline silicon film, and a desired value of Set to potential. When applied to a MIS transistor as a semiconductor element,
A desired threshold voltage V _th can be set.

According to the second aspect of the present invention, in the semiconductor element of the first aspect of the invention, the junction 58 and the gate electrode 55 are formed by changing the film thickness d ₂ of the polycrystalline silicon film 56 constituting the gate electrode 55. Since the distance from the lower semiconductor surface changes, the potential shift amount changes, and the potential under the gate electrode 55 can be adjusted to a desired value. In this case, the conventional manufacturing process such as impurity ion implantation is unnecessary, and therefore, the potential can be adjusted and the optimum value can be set without increasing the manufacturing process.

According to the third aspect of the present invention, the horizontal output gate section H subsequent to the horizontal transfer register 22 in the solid-state image pickup device is used.
In the OG, the horizontal output gate portion HOG is formed by the work function difference between the polycrystalline silicon film 33 and the junction portion 35 by forming the junction portion 35 with the Al film 34 on the polycrystalline silicon film 33 forming the gate electrode 32. Lower potential φa
However, compared with the case of one layer of polycrystalline silicon film, it shifts and is set to a potential φa of a desired value.

According to the fourth aspect of the present invention, in the solid-state image pickup device of the third aspect, the film thickness d _{1 of the} polycrystalline silicon film 33 forming the gate electrode 32 of the horizontal output gate portion HOG.
By changing the distance between the junction 35 and the semiconductor surface under the gate electrode 32, the potential shift amount changes, and the potential φa under the horizontal output gate portion HOG can be adjusted to a desired value. .

In this case, the conventional manufacturing process such as impurity ion implantation is not necessary, and therefore the manufacturing process is not increased.
In addition, the potential can be adjusted without preparing an external power source, and the potential can be set to an optimum value.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 show a CCD solid-state image pickup device according to this embodiment, particularly a horizontal transfer register and an output section thereof. The horizontal transfer register 2 in the CCD solid-state image pickup device 21 is formed on the transfer channel region 24 of the first conductivity type, for example, n type, which is formed on the main surface of the semiconductor substrate 23, via the gate insulating film 25 made of SiO ₂ or the like, for example. A plurality of first transfer electrodes 26A made of a first-layer polycrystalline silicon film and second transfer electrodes 26B made of a second-layer polycrystalline silicon film are alternately arranged along the transfer direction.

In the horizontal transfer register 22, every two adjacent transfer electrodes 26A and 26B connected to each other are set as a set, and the transfer electrodes 26 are set every other pair [26A, 26B].
And every other pair of transfer electrodes 26 [26A, 26
B] and two-phase horizontal drive pulses φH ₁ and φH _{2 respectively.}
Is applied. In the transfer channel region 25 below each second transfer electrode 26B, the second conductivity type, that is, p-type semiconductor region 27 is formed.
Are formed by, for example, ion implantation of impurities, thereby forming a transfer part having a storage part having the first transfer electrode 26A as a storage electrode and a transfer part having the second transfer electrode 26B as a transfer electrode. .

The alternate transfer electrodes 26 and the alternate transfer electrodes 26 are connected through Al wirings 29 and 30, respectively, which are connected via contact portions 29a and 30a at positions apart from the horizontal transfer register, respectively. Drive pulse φH ₁
And φH ₂ are applied.

At the final stage of the horizontal transfer register 22, a horizontal output gate portion HOG formed by forming a gate electrode 32 through a gate insulating film 25 is formed, and at the subsequent stage, a charge-voltage conversion means such as an n-type semiconductor. A floating diffusion region FD composed of regions is formed. The floating diffusion region FD is connected to the output amplifier 36. t ₂ is an output terminal.

Further, a reset drain region 37 made of an n-type semiconductor region is formed, and between the reset drain region 37 and the floating diffusion region FD,
The reset gate portion 38 is formed. The reset gate portion 38 is configured by forming a gate electrode 39 of, for example, a second-layer polycrystalline silicon film via the gate insulating film 25, and an Al wiring 40 connected to one end of the gate electrode 39 via a contact portion 40a. A reset pulse φ _RG is applied through. A reset voltage V _RD (for example, power supply voltage V _DD ) is applied to the reset drain region 37 through the Al wiring 41 connected through the contact portion 41a.

In this example, the gate electrode 32 of the horizontal output gate section HOG is constructed as follows. That is, for example, a second-layer polycrystalline silicon film 33 is formed on the gate insulating film 25 on the first conductivity type, that is, the n-type semiconductor region, an Al film 34 is laminated on the second-layer polycrystalline silicon film 33, and the polycrystalline film is formed immediately above the output gate. A gate electrode 32 is formed by forming a junction portion 35 between the silicon film 33 and the Al film 34 (a contact portion in which the so-called polycrystalline silicon film 33 and the Al film 34 are mutually reacted and alloyed).

Therefore, in the gate electrode 32 of the horizontal output gate portion HOG, as shown in FIG. 3, the junction portion 35 alloyed by mutual reaction is formed at the interface between the polycrystalline silicon film 33 and the Al film 34. Presents a structured structure. The Al film 34 is
An insulating film formed on the polycrystalline silicon film 23, for example, SiO
It is joined to the polycrystalline silicon film 33 through the contact hole 44 of the _two films 43.

The transfer channel region 24 of the Al film 34
For example, the ground potential (GND) inside the element is applied to the gate electrode 32 through the Al wiring 45 extending from the far end.
Is given.

In this horizontal output gate portion HOG, the gate electrode 32 in which the polycrystalline silicon film 33 and the Al film 34 are joined is formed immediately above the output gate, so that the potential φa under the gate electrode 32, and hence the potential. The barrier Δφ shifts due to the work function difference between the polycrystalline silicon film 33 and the junction 35 of the polycrystalline silicon film 33 and the Al film 34.

As a result of the test, the potential shift amount is a negative number V, which shows good reproducibility.
In this example, the potential shift is a direction in which the potential becomes shallow. Further, the potential shift amount changes depending on the film thickness d ₁ of the polycrystalline silicon film 33. That is,
By changing the film thickness d ₁ , the distance between the junction 35 with the Al film 34 and the surface of the p-type semiconductor region under the gate electrode 32 changes, so the influence of the junction 35 increases or decreases, and the potential shift amount changes. .

That is, if the distance is large, the shift amount is small, and if the distance is small, the shift amount is large. Therefore,
By using the polycrystalline silicon film 33 having an appropriate film thickness d ₁ , the horizontal output gate portion H can be obtained without ion implantation.
The potential under the OG can be adjusted.

In the CCD solid-state image pickup device 21, as shown by the potential 46 in FIG. 1, the signal charges are transferred in the horizontal transfer register 22 by the two-phase drive pulses φH ₁ and φH ₂ as described above, and one pixel The signal charge for each is transferred to the floating diffusion region FD through the horizontal output gate unit HOG. Then, the voltage corresponding to the charge of the floating diffusion region FD is output to the output amplifier 3
Then, the CCD output corresponding to the signal charge is read out.

After the signal charge for one pixel is read out,
A reset pulse φ _RG is applied, and the reset gate unit 38
Is turned on, the signal charges in the floating diffusion region FD are swept out to the reset drain region 37, and the potential of the floating diffusion region FD is reset to the potential of the reset drain region 37.

According to the CCD solid-state image pickup device 21 described above,
In the horizontal output gate portion HOG, the polycrystalline silicon film 33
Gate electrode 32 having a junction 35 with Al film 34 on top
By forming, the potential under the gate electrode 32 can be shifted as compared with the case where the polycrystalline silicon film 1 layer is used. That is, by controlling the film thickness d ₁ of the polycrystalline silicon film 33, the potential barrier under the gate electrode 32 can be easily increased without increasing the number of steps such as ion implantation of impurities or preparing an external power source. It can be adjusted and the potential barrier can be set to an optimum value.

In this embodiment, since it is sufficient to form the contact hole 41 in the insulating film 40 on the polycrystalline silicon film 33, the number of steps is not increased at all. Further, since the gate electrode 32 is connected to the ground potential inside the image pickup device, there is no fear of electrostatic breakdown.

Although the impurity ion implantation is not necessary in the above example, it is of course possible to set the potential under the horizontal output gate portion HOG by combining the impurity ion implantation and the gate electrode structure of the present invention. Is.

A potential dip may occur between the final stage transfer section of the horizontal transfer register 22 and the horizontal output gate section HOG, but this dip can be erased by the bias applied to the final stage transfer section. It is possible.

The present invention also applies to a semiconductor element having a so-called electrode-insulator-semiconductor structure having a gate electrode on a semiconductor substrate via a gate insulating film, as the gate electrode, as in the above-described embodiment. A gate electrode formed with the Al film 34 so as to form the junction 35 on the polycrystalline silicon film 33 can be applied. By controlling the film thickness of the polycrystalline silicon film 33 having the gate electrode structure, the potential under the gate electrode can be easily adjusted to a desired value.

FIG. 4 shows an embodiment applied to a MIS type transistor. In this example, the first conductivity type, that is, n type source region 5 is formed on the second conductivity type, for example, p type semiconductor substrate 51.
2 and the drain region 53 are formed, and the gate electrode 55 is formed between the source region 52 and the drain region 53 on the substrate 51 via the gate insulating film 54 made of, for example, SiO ₂ . The gate electrode 55 is the polycrystalline silicon film 5
6 and an Al film 57 are laminated to form a polycrystalline silicon film 56.
Of Al and the Al film 57 (so-called polycrystalline silicon film 5
6 and the Al film 57 interact with each other to form an alloyed contact portion) 58. Reference numeral 59 is an insulating film.

Insulated gate type field effect transistor of this example
According to 50, the polycrystalline silicon forming the gate electrode 55
Threshold value due to the work function difference between the film 56 and the junction 58.
Voltage V_thIs set, and the thickness of the polycrystalline silicon film 56 is set.
d₂Depending on the threshold voltage V _thCan be adjusted
It

[0047]

According to the semiconductor element of the present invention, since the junction with the Al film is formed on the polycrystalline silicon film forming the gate voltage, the number of manufacturing steps such as impurity ion implantation is not increased. The potential under the gate electrode, for example, the threshold voltage V _th can be set to a desired value. Further, the potential can be adjusted to a desired value by adjusting the potential shift amount by controlling the film thickness of the polycrystalline silicon film.

According to the solid-state image pickup device of the present invention, in the horizontal output gate section at the final stage of the horizontal transfer register, the polycrystalline silicon film forming the gate electrode has a junction with the Al film. The potential of the horizontal output gate section can be set to an optimum value without increasing the number of manufacturing steps such as impurity ion implantation and without applying a bias from the outside. Further, by controlling the film thickness of the polycrystalline silicon film forming the gate electrode, the shift amount of the potential can be easily adjusted to a desired value.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (including a potential diagram) showing an example of a main part of a solid-state imaging device according to the present invention, that is, a horizontal transfer register and an output part.

FIG. 2 is a plan view of FIG.

FIG. 3 is an enlarged cross-sectional view of a gate electrode of a horizontal output gate section according to the present invention.

FIG. 4 is a cross-sectional view showing an example of an insulated gate field effect transistor according to the present invention.

FIG. 5 is a cross-sectional view (including a potential diagram) of a main part of a conventional solid-state imaging device, that is, a horizontal transfer register and an output part.

FIG. 6 is a plan view of FIG.

[Explanation of symbols]

 21 CCD solid-state image sensor 22 horizontal transfer register 23 substrate 24 transfer channel region 25 gate insulating film 26 [26A, 26B] transfer electrode HOG horizontal output gate part 32 gate electrode 33 polycrystalline silicon film 34 Al film 35 polycrystalline silicon film and Al Bonding part with film 37 Reset drain region 38 Reset gate part 39 Gate electrode FD Floating diffusion region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/78 H01L 29/78 301 C

Claims (4)

[Claims] 1. A semiconductor substrate has a gate electrode with a gate insulating film interposed therebetween, and a junction with an Al film is formed on the polycrystalline silicon film forming the gate electrode. A semiconductor element, wherein a potential under the gate electrode is set by a junction. 2. The semiconductor device according to claim 1, wherein the potential under the gate electrode is adjusted by the film thickness of the polycrystalline silicon film. 3. A horizontal output gate portion in a subsequent stage of a horizontal transfer register, wherein a junction with an Al film is formed on a polycrystalline silicon film forming a gate electrode, and the polycrystalline silicon film and the junction form the junction. A solid-state image pickup device characterized in that a potential under a horizontal output gate section is set. 4. The solid-state imaging device according to claim 3, wherein the potential under the horizontal output gate portion is adjusted by the film thickness of the polycrystalline silicon film.