JPH088470B2 - Flip-flop circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit in a semiconductor integrated circuit or the like, and more particularly to a flip-flop circuit suitable for high-speed operation (hereinafter referred to as FF circuit).

(Conventional Technology) Conventionally, as a technology in such a field,
E-E TRANSACTION ON ELECTRON
Device (IEEE TRANSACTIONS ON ELECTRON DEVICE
S), ED-29 [2] (1982-2) (US) Mizutani et al. “Gigabit Logic Operation with Enhancement-Mode GaAs MESFET IC (Gigabit Logic Op
integration with Enhancement-Mode GaAs MESFET IC '
S) ”There was one described in P199-204. The configuration will be described below with reference to the drawings.

FIG. 2 is a circuit diagram showing a configuration example of a conventional master / slave FF circuit.

This FF circuit is composed of an integrated circuit (hereinafter referred to as an IC) that uses GaAs MESFET (Sheyotky Barrier Gate Field Effect Transistor), which has excellent high-frequency characteristics. It consists of a master side FF circuit 10 and a slave side FF circuit. It is configured. The master-side FF circuit 10 has a 2-input NOR gate 11 that takes the NOR of the data input D and the clock input C, and a 2-input that takes the NOT of the inverted data input and the clock input C.
A NOR gate 12 is provided, and two-input NOR gates 13 and 14 are cascade-connected to the output sides of the NOR gates 11 and 12. Also provided is an inverter 15 which inverts the clock input C to produce an inverted clock input. Slave side FF
The circuit 20 has the same circuit configuration as that of the master side FF circuit 10, is composed of four 2-input NOR gates 21 to 24, and is cascade-connected to the output side nodes N1 and N2 of the master side FF circuit 10. There is. In the figure, Q is data output and is inverted data output.

FIG. 3 is a time chart showing the operation of the master side FF circuit 10 of FIG.

While the clock input C is at "L" level, NOR gates 11 and 22
Acts as a simple inverter, the same signals as the data input D and the inverted data input are output to the nodes N1 and N2. Next, when the clock input C becomes "H" level, NO
The outputs of the R gates 11 and 12 are at the “L” level regardless of the data input D and the inverted data input, and the NOR gates 13 and 14 are the data input D and the inverted data input before the clock input C is at the “H” level. Acts to hold.

This type of FF circuit operates only for one clock input C, but cannot be applied to two clock inputs. Therefore, an FF circuit which operates for two clock inputs C1 and C2 has been conventionally proposed in the form shown in FIG.

FIG. 4 shows a conventional FF circuit for inputting two clocks. Instead of the two-input NOR gates 11 and 12 shown in FIG.
The difference from FIG. 2 is that gates 11A and 12B are provided. The FF circuit of FIG. 4 is configured as a master / slave type FF circuit by connecting it in two stages.

In the FF circuit of FIG. 4, while the clock input C1 is at the "L" level, the 3-input NOR gates 11A and 11B operate in the same way as the 2-input NOR gate without the clock input C1. It operates to obtain the data output Q and the inverted data output synchronized with the clock input C2. Further, while the clock input C2 is at "L" level, the clock input C1 operates with respect to the clock input C1, so that the data output Q and the inverted data output synchronized with the clock input C1 can be obtained.

Further, when the number of clock inputs to be synchronized is increased, the NOR gates 11A and 12A may be composed of multi-input gates.

(Problems to be Solved by the Invention) However, the FF circuit configured as described above requires a gate with a larger number of inputs as the number of clock inputs increases, and the gate with a large number of inputs is more than that of a gate with one input. Since the operating speed becomes slow, the maximum operating speed of the FF circuit becomes slow, and technically unsatisfactory results were not obtained.

The present invention provides an FF circuit which solves the problem that the above-mentioned conventional technique has a problem that the operation speed becomes slow due to an increase in the number of clock inputs.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an FF circuit which is connected in parallel between a data input terminal and a first node and is turned on by independent clock inputs, Is connected in parallel between a first parallel transfer gate circuit including N transfer gates (N is an arbitrary integer of 2 or more) to be turned off, and an inverting data input terminal and a second node, A second parallel transfer gate circuit, which is composed of N transfer gates which are on / off controlled by the independent clock inputs and has the same configuration as the first parallel transfer gate circuit, is provided. Further, the first and second inverters connected in series between the first node and the second node and forwardly connected between the first node and the inverted data output terminal. A third inverter, and a fourth inverter connected in the forward direction between the second node and the data output terminal.
And an inverter are provided.

(Operation) According to the present invention, since the FF circuit is configured as described above, the plurality of transfer gates in the first parallel transfer gate circuit and the second parallel transfer gate circuit are provided by the plurality of clock inputs independent of each other. A plurality of transfer gates in the gate circuit are turned on and off to control input data given to the data input terminal and the inverted data input terminal. These plurality of transfer gates have a function of allowing data to be input without causing a delay. The input data fetched by the first and second parallel transfer gate circuits is latched (held) by the first and second inverters, and the latched data is inverted data output by the third and fourth inverters. It is output to the terminal and the data output terminal. The third and fourth inverters output the latched data to the outside,
That is, it has a function as an output buffer.

(Embodiment) FIG. 1 is a circuit diagram of a master / slave FF circuit for 2-clock input showing an embodiment of the present invention.

The FF circuit is composed of, for example, GaAs / MESFET / IC, and includes a master side FF circuit 30 and a slave side FF circuit 50.

The master side FF circuit 30 has an input terminal (data input terminal) 31 for data input D, an inverted input terminal (inverted data input terminal) 32 for opposite data input, and an inverted output terminal (inverted data output terminal) for inverted data output. ) 33, and data output Q
It has an output terminal (data output terminal) 34 for. The drains of two transfer gates 35 and 36 formed of normally-off MESFETs are commonly connected to the input terminal 31, and their sources are commonly connected to the first node N11. Similarly, the drains of the two transfer gates 37 and 38 formed of normally-off MESFETs are also commonly connected to the inverting input terminal 32, and the sources thereof are commonly connected to the second node N12. DCFL between the first and second nodes N11 and N12
First and second inverters 41, 42 made of (Direct Coupled FET Legic) are connected in cascade. Furthermore, the first
The third inverter 43 formed of DCFL is connected in the forward direction between the node N11 and the output terminal 33, and the fourth inverter 44 formed of DCFL is also formed between the second node N12 and the inverting output terminal 34. Are connected in the forward direction. The two transfer gates 35 and 36 form a first parallel transfer gate circuit, and the two transfer gates 37 and 38 form a second parallel transfer gate circuit. The transfer gates 35 and 37 are on / off controlled by the clock input C1, and the transfer gates 36 and 38 are on / off controlled by the clock input C2.

The slave side FF circuit 50 cascade-connected to the output terminals 33 and 34 of the master side FF circuit 30 has the same configuration as the master side FF circuit 30, and has an output terminal 53 for data output Q and an inversion for inverted data output. The output terminal 54, four transfer gates 55 to 58, and first to fourth inverters 61 to 64 are included. The transfer gates 55 and 57 are turned on and off by the inverted clock input 1 and the transfer gates 56 and 58 are turned on and off by the inverted clock input 2.

FIG. 5 is a time chart showing the operation of the first master side FF circuit 30.

During the period T1 in which the clock input C1 is at "L" level, the transfer gates 35 and 37 are in the off state. At this time, if the clock input C2 goes high, the transfer gates 36,3
Since 8 is turned on, the data input D and the inverted data are inverted by the inverters 43 and 44, and the inverted data output and the data output Q are output from the inverted output terminal 33 and the output terminal 34, respectively. When the clock input C2 goes to "L" level, the transfer gates 36 and 38 are turned off and the inverter 4
1, 42 holds the data input D and the inverted data input when the clock input C2 is at "H" level. As a result, a signal synchronized with the clock input C2 is output.

Similarly, during the period T2 when the clock input C2 is at “L” level, the signal synchronized with the clock input C1 is inverted output terminal 33.
And is output from the output terminal 34.

The slave side FF50 also performs almost the same operation as the master side FF30. Therefore, the circuit of FIG. 1 operates as an FF circuit that operates for two types of clock inputs C1,1 and C2,2.

 The present embodiment has the following advantages.

(I) Since the circuit is composed only of the transfer gates 35 to 38, 55 to 58 and the inverters 41 to 44, 61 to 64, the delay time due to the multi-input gate does not increase and the operating speed can be increased.

That is, for example, when operating with the clock input C1,1 system, the flip-flop operation is performed by setting the clock input C2, system to "L" level and turning off the transfer gates 36, 38, 56, 58. At this time, since the transfer gates 36, 38, 56, 58 are in a state of being separated from the circuit, no delay time of signal transmission occurs. On the other hand, in the circuit of FIG. 4, even when the clock input C2 is set to "L", the NOR gates 11A and 12B through which the clock input C1 passes always operate, so that the signal transmission of the NOR gates 11A and 12B is prevented. There will be a delay. This delay time becomes longer as the number of inputs to the NOR gates 11A and 11B increases. Therefore, the FF circuit of this embodiment can operate at high speed.

(Ii) Since the inverters 41 and 42 and 61 and 62 form a latch circuit, a stable and high-speed operation can be obtained as compared with the case where the other gates such as NOR gates are used.

(Iii) If more clock inputs are required, transfer gates 35, 36, 37, 38,
This can be easily achieved by simply increasing the number of parallel connections at 55, 56, 57, 58.

(Iv) In this embodiment, it is possible to use only the master side FF circuit 30 or the slave side FF circuit 50. For example, it may be used as a latch circuit or the like.

The present invention is not limited to the illustrated embodiment, and various modifications can be made. The following are examples of such modifications.

(A) Transfer gates 35 to 38, 55 to 58 are MESFET
Instead of this, a switch element such as a MOSFET or a bipolar transistor may be used.

(B) Inverters 41 to 44, 61 to 64 are also CMOS other than DCFL.
It may be configured by an inverter or the like.

(Effects of the Invention) As described in detail above, according to the present invention, since the FF circuit is composed of only the transfer gate and the inverter, even if the number of clock inputs is increased, the signal delay is extremely small and stable. High-speed operation becomes possible.

[Brief description of drawings]

1 is a circuit diagram of an FF circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional FF circuit, FIG. 3 is a time chart of FIG. 2, and FIG. 4 is a circuit of a conventional FF circuit. Figures and 5 are the time charts of Figure 1. 30 …… Master side FF circuit, 31 …… Input terminal, 32 …… Inversion input terminal, 33,54 …… Inversion output terminal, 34,53 …… Output terminal, 35 to 38, 55 to 58 …… Transfer gate, 41 ~ 44,61
~ 64 …… Inverter, C1, C2 …… Clock input, 1,
2 ... Inverted clock input, N11, N12 ... Node.

Claims (1)

[Claims] 1. N (N is an arbitrary integer of 2 or more) transfers which are connected in parallel between a data input terminal and a first node and are on / off controlled by independent clock inputs. It comprises a first parallel transfer gate circuit composed of gates and N transfer gates connected in parallel between the inverted data input terminal and the second node, and turned on and off by the independent clock inputs. A second parallel transfer gate circuit having the same configuration as the first parallel transfer gate circuit, and first and second inverters connected in cascade between the first node and the second node, A third inverter connected in the forward direction between the first node and the inverted data output terminal, and between the second node and the data output terminal A flip-flop circuit comprising: a fourth inverter connected in a forward direction.