JPH088765A - Carrier generation circuit - Google Patents

Abstract

PURPOSE:To obtain a carrier generation circuit which is used for a synchronous broadcasting, etc., having the necessity of matching the frequencies and phases of the outputs of plural carrier generation circuits. CONSTITUTION:A decoder 1 outputs the reference clock (e) having one block period. The first rise of the reference clock (e) having one block period since the power source is turned on is detected and outputted by a reset signal generation circuit 2. By this reset signal (f), the register 32 of a DDS 3 is reset and the address of a ROM 33 is cleared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier generation circuit,
In particular, the present invention relates to a carrier wave generation circuit used for synchronous broadcasting or the like in which it is necessary to match the frequencies and phases of outputs of a plurality of carrier wave generation circuits.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional carrier generation circuit.

The decoder 6 receives the audio signal a conforming to the AES / EBU format, and outputs the audio data b and the reference signal d for the DDS system clock.

The conventional carrier wave generation circuit is constructed by the decoder 6
And the reference signal d is input and the DD synchronized in phase with this signal
It has a DDS system clock generation circuit 4 which outputs an S system clock g, and a DDS (direct digital synthesizer) 3 which inputs the DDS system clock g and outputs a sine wave having a frequency corresponding to the frequency setting signal c. .

The DDS 3 has an adder 31 and a register 32 for accumulating the frequency setting signal c, and converts the output of the register 32 into sine amplitude information by a sine table written in the ROM 33 as phase information. , D /
The A converter 34 converts the analog value and outputs the analog value. The address of the ROM 33, that is, the register 32 for determining the phase of the carrier wave output is cleared only when the power is turned on.

As the DDS system clock generation circuit 4, a PLL (phase locked loop) circuit for phase-locking with the reference signal d is constituted by a phase comparator 41, a voltage controlled oscillator 43 and a frequency divider 42.

The filter 5 is a filter for removing spurious (unwanted wave) of the output from the DDS 3, and outputs the signal transmitted through this filter 5 as a carrier wave i.

[0008]

In the conventional carrier wave generation circuit shown in FIG. 2, the register 32 in the DDS3 for determining the phase of the output carrier wave i is cleared only when the power is turned on. When the same reference signal d is supplied to a plurality of carrier wave generation circuits, the frequencies of the carrier waves output by the respective carrier wave generation circuits can be made to match, but the power-on time of each carrier wave generation circuit must be made exactly the same. Therefore, there is a problem that the clear timing of the register 32 is different and the phases of the carrier waves output by the carrier wave generating circuits cannot be matched.

The present invention has been made in view of the above points, and an object of the present invention is to provide a carrier generation circuit used for synchronous broadcasting or the like in which it is necessary to match the frequencies and phases of outputs of a plurality of carrier generation circuits. To do.

[0010]

In order to achieve the above object, the present invention inputs a digital audio signal of AES / EBU format to input digital audio data and a reference clock which is an integral multiple of the sampling frequency of the digital data. And a DDS system clock generating circuit which outputs a DDS system clock phase-synchronized with this reference signal by inputting a reference clock that is an integral multiple of the sampling frequency from this decoder as a reference signal.
In a carrier generation circuit having a DDS which inputs a DDS system clock from a system clock generation circuit and outputs a sine wave having a frequency corresponding to a frequency setting signal as a carrier, the decoder outputs a reference clock of one block period, The RDS of the DDS is detected by detecting the first rising after the power supply of the reference clock of one block cycle is turned on.
A reset signal generation circuit for outputting a reset signal for clearing the OM address is provided.

[0011]

According to the present invention, with the above configuration, the decoder outputs the reference clock of one block period, the first rising edge of the reference clock of one block period after power-on is detected, and the reset signal generated by the reset signal generation circuit is output. Clears the DDS ROM address.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a carrier generation circuit according to the present invention.

The decoder 1 inputs an audio signal a conforming to the AES / EBU format, and outputs audio data b and DDS.
Reference signal d for system clock and reference clock e of one block period (1 block = 192 frames = 1/48
kHz × 192 = 4 mSec) is output.

In the present embodiment, the DDS system clock reference signal d is used as a reference signal, and D synchronized in phase with this signal is used.
The DDS system clock generation circuit 4 for generating the DS system clock g includes a phase comparator 41 and a frequency divider 42.
And a voltage controlled oscillator 43.

The DDS 3 receives the DDS system clock g generated by the DDS system clock generation circuit 4 and outputs a sine wave corresponding to the frequency setting signal c.

The reset signal generation circuit 2 detects the first rising edge of the output of the decoder 1 for the reference clock e of one block cycle after the power is turned on and outputs the reset signal f to output DD.
By clearing the register 32 for setting the address of the ROM 33 of S3, the phase of the output of the DDS 3 is set to 0 degree.

The reference clock e of one block period is 4 mS.
Since the ec cycle (250 Hz), the carrier frequency is 25
If it is an integral multiple of 0 Hz, the phase of the output of the DDS3 is set to 0 degree once at the rising edge of the reference clock e of one block period, so that the output of DS3 is always output at the subsequent rising edge of the reference clock e of the one block period. Phase is 0
It becomes degree.

Therefore, the phase of the output of the DDS 3 can be set to 0 degree at the rising edge of the reference clock e of one block period regardless of the power-on timing, so that the same audio signal a is input to a plurality of carrier generation circuits. Even if the power is turned on at different timings, the phases of the carrier waves h to be output can be matched.

[0020]

As described above, according to the present invention,
Input the AES / EBU format digital audio signal and output the audio digital data. Decoder ROM address is detected at this timing by detecting the first rising edge of the reference clock of one block cycle output from the decoder. Since the register to be set is cleared, there is an effect that the frequencies and phases of the outputs of the plurality of carrier wave generation circuits that receive the same audio signal can be matched.

As a result, it is possible to provide a carrier generation circuit used for synchronous broadcasting or the like in which the frequencies and phases of the outputs of the plurality of carrier generation circuits need to be matched.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a carrier generation circuit according to the present invention.

FIG. 2 is a block diagram of a conventional carrier wave generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 decoder 2 reset signal generation circuit 3 DDS 31 adder 32 register 33 ROM 34 D / A converter 4 DDS system clock generation circuit 41 phase comparator 42 frequency divider 43 voltage controlled oscillator 5 filter

Claims (3)

[Claims] 1. A decoder which inputs a digital audio signal of AES / EBU format and outputs digital data of audio and a reference clock which is an integral multiple of the sampling frequency of the digital data, and an integer multiple of the sampling frequency from the decoder. The DDS system clock generating circuit that inputs the reference clock of 1) as a reference signal and outputs the DDS system clock that is phase-synchronized with the reference signal, and the DDS system clock from the DDS system clock generating circuit that inputs the frequency setting signal In a carrier wave generation circuit having a DDS that outputs a sine wave having the above frequency as a carrier wave, the decoder outputs a reference clock of one block period, and detects the first rising edge of the reference clock of the one block period after the power is turned on. Clear the DDS ROM address Carrier wave generating circuit, characterized in that it comprises a reset signal generating circuit for outputting a reset signal. 2. The DDS includes an adder for accumulating the frequency setting signal, a register for outputting phase information of a carrier wave to be output, a ROM in which amplitude information of a sine wave is stored in advance, and a ROM of the ROM. D / that converts the output to an analog value
The carrier generation circuit according to claim 1, further comprising an A converter, wherein the reset signal zero-clears phase information output from the register. 3. The carrier generation circuit according to claim 2, further comprising a filter for removing spurious of a sine wave output from the DDS.