JPH0482407A - Digital signal generator - Google Patents

Abstract

PURPOSE:To take perfect synchronism with a measuring instrument with reference frequency of 10MHz by generating a signal of 2<n>Hz synchronized with 10MHz as the clock signal of a DDS. CONSTITUTION:Prescribed frequency data is added on an adder 1, and is inputted to a latch 2. Waveform data of prescribed bits is outputted from memory 3 to a D/A converter 4. Meanwhile, a clock signal system frequency-divides a reference clock of 10MHz to 2<7>Hz by a frequency divider and inputs it to a phase comparator 7. The output of the comparator 7 is inputted to an oscillator 9, and goes to the signal of 2<n>Hz and is frequency-divided to the one of 2<7>Hz by a frequency divider 11, and is inputted to the comparator 7. The output of the comparator is inputted to the latch 2 and the D/A converter 4 as the clock signal. Thereby, the signal of 2<n>Hz can be obtained with 1Hz resolution as an analog output waveform. Therefore, the perfect synchronism with the measuring instrument with reference frequency of 10MHz can be taken.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a digital signal generator using DDS (Digital Direct Synthesizer) technology, and more particularly to improvement of a clock signal system.

<Prior Art> DDS technology is widely used in digital signal generators.

FIG. 3 is a schematic block diagram of such a digital signal generator using DS technology. In the figure, N-bit frequency data is input to one input terminal of an adder 1, and output data of the adder 1 is input via a counter 2 to the other input terminal. The output data of the latch 2 is input as an address for reading sine wave data stored in the memory 3. The sine wave data read from the memory 3 is input to a D/A converter 4 and converted into an analog waveform signal. The analog waveform signal is then output to the outside via the low-pass filter 5.

Incidentally, a binary type adder 1 has conventionally been used in such a DS because it has a simple configuration and can realize high-speed operation.

Therefore, in order to obtain IHz resolution as an analog waveform output, the frequency of the clock signal CLK input to the latch 2 must be set to 2''Hz (n≧2).

<Problem to be solved by the invention> However, the standard frequency of high-frequency measuring instruments used for boat fishing is 10 MHz.
Since it is set to z, the frequency 27 as mentioned above
DDS driven by a clock signal of Hz (n≧2)
When using a digital signal generator including a digital signal generator, there is a problem that complete synchronization with other measuring instruments cannot be achieved.

The present invention has been made with attention to these points,
The purpose is to provide a digital signal generator including a DDS using a binary adder that can be perfectly synchronized with a measuring instrument having a reference frequency of 10 MHz.

Means for Solving the Problems> The present invention to solve the above problems is as follows: In a digital signal generation device including a DDS using a binary adder, the clock signal system of the DDS converts a 10 MHz reference clock to 27 Hz. A first frequency divider that divides the frequency; a phase comparator that receives the output of the first frequency divider as one input; and an oscillator that outputs a 2-Hz signal based on the output of the phase comparator. and a second frequency divider which divides the output of the oscillator to 27 Hz and inputs the frequency to the other input terminal of the phase comparator.

Effect> According to the digital signal generator of the present invention, a 2"Hz signal synchronized with 10MHz is generated as a DDS clock signal.

As a result, complete synchronization can be achieved between a digital signal generator including a DDS using a binary adder and a measuring instrument having a reference frequency of 10 MHz.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock signal system used in a digital signal generator according to the present invention.
This focuses on the relationship of 10 MHz-27 x 25 Hz. In the figure, the reference clock of the IOMH 2 is input to a first frequency divider 6, frequency-divided to 27 Hz, and input to one input terminal of a phase comparator 7. The output of the phase comparator 7 is inputted via a low-pass filter 8 to an oscillator 8 which outputs a 27 Hz signal. As the oscillator 9, a voltage controlled frequency variable crystal oscillator (VCXO) is used. The output of the oscillator 9 is output to the output terminal 10 and the second
The frequency divider 11 is manually operated. The second frequency divider 11 divides the 27 Hz signal of the oscillator 8 to 27 Hz and inputs the divided signal to the other input terminal of the phase comparator 7. Note that the clock signal system forms a phase locked loop (PLL).

FIG. 2 is a block diagram showing an embodiment of a digital signal generator including a DDS using the clock signal system shown in FIG. Therefore, their explanation will be omitted. In Figure 2,
24-bit frequency data is added to adder 1, and adder 1 and latch 2 have a 24-bit configuration.

Here, the least significant bit of the frequency data corresponds to IHz, and then the higher bits correspond to 2122...22
It will correspond to 3Hz. Input the upper 12 bits of the output data of latch 3 as the address of memory 3,
8-bit waveform data is output from the memory 3 to the D/A converter 4.

On the other hand, a 2"Hz (-16,777216MH2) signal is input as a clock from the clock signal system shown in FIG. 1 to the latch 2 and the D/A converter 4. As a result,
As an analog output waveform, IHz resolution Te2 "H2~
A 222Hz signal is obtained.

Note that the reference frequency of the PLL of the clock signal system that generates the 2 Hz (=16.777216 MH2) signal is as low as 27 Hz (=128 Hz>), but since it is a constant frequency that is required for the output. A sufficiently low-sensitivity voltage-controlled frequency variable crystal oscillator can be used, and the SS of the voltage-controlled frequency variable crystal oscillator itself can be used.
Since the B noise is also very low, the loop band can be made sufficiently narrow, so there is no risk of causing any practical problems.

<Effects of the Invention> As described in detail above, according to the present invention, a digital signal generator including a DDS using a binary adder that can be perfectly synchronized with a measuring instrument having a reference frequency of 10 MHz can be used. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a clock signal system used in a digital signal generation device according to the present invention, and FIG. 2 is a block diagram of a digital signal generation device including a DDS using the clock signal system shown in FIG. Block diagram showing one embodiment, third
Figure G is a schematic block diagram of a digital signal generator using DDS technology. 1...Adder 2...Latch 3...Memory 4...D/A converter 5...Low pass filter 6
... first frequency divider 7 ... phase comparator 8 ... low-pass filter 9 ... oscillator 11 ... second frequency divider.

Claims (1)

[Claims] In a digital signal generation device including a DDS using a binary adder, the clock signal system of the DDS includes a first clock signal that divides a 10 MHz reference clock into 2^7 Hz.
a frequency divider, a phase comparator having one input as the output of the first frequency divider, an oscillator that outputs a 2^nHz signal based on the output of the phase comparator, and an output of the oscillator. a second frequency divider which divides the frequency of the signal into 2^7Hz and inputs the frequency to the other input terminal of the phase comparator.