JPH089141A - Marker erasing device - Google Patents

Abstract

PURPOSE:To avoid a marker from being left unerased resulting from a position deviation of original setting at preliminary scanning and copy scanning in the marker erasing device in which a marker written by a marker pen on an original for edit preliminary processing is erased when the original is read for the execution of edit. CONSTITUTION:A marker recognition circuit 1 recognizes a marker in the preliminary scanning and stored in a marker data storage section 2-1. In the case of copy scanning, an output as if to be a marker part is outputted from a marker thickening circuit 8 as to an area to be extended by a width designated in advance in the main scanning direction and the sub scanning direction from the marker part read in the preliminary scanning. Thus, even when an original set in the copy scanning is more or less deviated from the position in the case of the preliminary scanning, the marker read in the copy scanning is resident in the extended area. When the marker is in existence in the extended area, a selection circuit 3 selects data of a replacement level setting section 4 to erase the marker.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a marker erasing device for erasing a marker written on a document by a marker pen for editing preparation processing when reading the document for editing.

[0002]

2. Description of the Related Art In an image processing apparatus such as a copying machine or a facsimile, a partial area of a document is designated and the characters in the area are italicized, or only the image in that area is left and other areas are left. Editing such as erasing may be performed. When performing such editing, the area is specified by enclosing it with a marker pen. In addition, the part written with the marker pen is called a marker here.

FIG. 4 is a diagram for explaining an original image and a marker. Reference numeral 20 is a document, 21 is a marker, 22 is a document image, 23 is a main scanning line, D _B is a black level, D _M is a marker level, D _U is a marker upper limit value, and D ₁ is a marker lower limit value. FIG. 4A shows a document image 22 on the document 20.
It shows a state in which is surrounded by a marker 21. Figure 4 (b)
Indicates the change in density when reading along the main scanning line 23.

The density of the original image 22 is at the black level D _B , but the density of the marker 21 is at the marker level D _M which is considerably lower than that. This density is about the same as gray. Whether or not the portion showing a certain concentration is the portion of the marker is detected by determining whether or not the concentration is between the preset marker upper limit value D _U and the marker lower limit value D _l. Do by investigating.

When designating an area with a marker,
The original is read twice with the image scanner. The first reading (hereinafter referred to as “prescan”) is performed to recognize the area designated by the marker. The second reading (hereinafter referred to as “copy scan”) is performed in order to perform a pre-designated editing process (for example, a process of leaving only the region and erasing others) on the designated region. Since the marker was not originally written on the manuscript, it must be erased at the time of copy scanning.

FIG. 2 shows a conventional marker erasing device.
In FIG. 2, 1 is a marker recognition circuit, 2 is a memory device, 3 is a selection circuit, 4 is a replacement level setting unit, 5 is a marker density upper limit value setting unit, 6 is a comparison circuit, and 7 is an AND circuit.

The read image data input (during pre-scanning) is image data obtained by reading a document with a marker attached thereto with an image scanner (not shown). The prescan is intended only to find out which part of the document is marked with a marker, and at this time, only the marker recognition circuit 1 and the memory device 2 are operated.

The marker recognition circuit 1 compares the density of the image data with the marker upper limit value D _U and the marker lower limit value D ₁ shown in FIG. 4 to judge whether the read portion is the marker portion or not. The marker data a is output. The marker data a has a value of “1” for a pixel position determined to be a marker portion, and a value of “0” for a pixel position determined not to be a marker portion. Then, it is stored in the memory device 2. As the memory device 2, for example, like a page memory,
Use a storage device that has the capacity to record data on the pixel positions of the entire document.

(At the time of copy scan) At this time, parts other than the marker recognition circuit 1 are operated. The same original document with the marker is read again by the image scanner, and the read image data is input to the selection circuit 3.
When the image data of the marker portion is input, the image data is not output, and the replacement level data (for example, the background color data of the document) provided by the replacement level setting unit 4 is selected and output. To be done. This means that the marker will be erased.

When the image data of the portion which is not the marker is input, the input image data is selected and output as it is. The determination as to whether or not the image data of the marker portion is made by the output f from the memory device 2 and the output g from the comparison circuit 6 in FIG. 2, and the determination result is A
It is represented by the value of the output h from the ND circuit 7. That is,
The output h has the following values. When the image data of the marker part → output h is "1" When the image data of the part which is not marker → output h is "0"

First, the output f from the memory device 2 will be described. The data (output f) read from the memory device 2 is the data of the same address (pixel position) as the read image data that is currently input to the selection circuit 3. Since the same manuscript is read, when the marker portion is read by the copy scan, if the memory device 2 is searched by the address and the marker data a is read, the value should be "1". . Also, "0" should be read at the address of the portion other than the marker.

Next, the output g from the comparison circuit 6 will be described. This output g is a signal indicating whether or not the marker overlaps the original image. FIG. 5 is a diagram showing a situation in which the marker 21 has overlapped the original image 22.
Although the overlapping portion 22-1 is a marker portion, it is a part of the document image 22, and therefore, it is necessary not to erase it. The role of the comparison circuit 6 and the marker density upper limit value setting unit 5 is to prevent the overlapping portion 22-1 from being erased when the marker 21 is written so as to overlap the original image 22.

The image data read by the copy scan is input to the selection circuit 3 and also to the comparison circuit 6, and is compared with the marker density upper limit value of the marker density upper limit value setting unit 5. This value is the marker upper limit value D in FIG.
_{Like U} , it is set to a value higher than the marker level D _M but lower than the black level D _B. When it is lower than the marker density upper limit value, the output of the comparison circuit 6 is "1",
When the concentration is high, it is set to "0". In the overlapping section 22-1, since the density is higher than the marker density upper limit value, “0” is output.

When "0" is input from the comparison circuit 6 to the AND circuit 7, the output read from the memory device 2 is "1" (which means that it is the pixel position of the marker portion). Even if there is, the output of the AND circuit 7 becomes "0". At this time, the marker erasing operation is not performed in the selection circuit 3 (that is, the replacement level setting unit 4
No replacement is done at the level. ). Thus,
The overlapping part 22-1 remains without being erased.

When both the data read from the memory device 2 and the signal from the comparison circuit 6 are "1", the output of the AND circuit 7 becomes "1". In this case, the marker is erased by replacing the read image data of the marker with the replacement level.

As a conventional document relating to the marker erasing device, there is, for example, JP-A-4-53346.

[0017]

[Problems to be Solved by the Invention]

(Problem) However, in the above-described conventional marker erasing device, when reading a document with a marker, if the position of the document is misaligned between prescan and copy scan, a part of the marker remains without being erased. There was a problem that it would end up.

(Explanation of Problems) FIG. 6 is a diagram showing a situation in which a part of the marker remains without being erased. Reference numeral 21-1 is a prescan reading marker, 21-2 is a copy scanning reading marker, and 24 is a marker shift portion. Figure 6
(A) shows the marker read by the prescan and the marker read by the copy scan.

Since the same manuscript is read, if the manuscript is set at the same position twice, the marker is also read at the same position. That is, the pre-scan reading marker 21-1 and the copy-scan reading marker 21-2 are exactly overlapped. However, if the position where the original is set is displaced, both are displaced as shown in FIG.

The marker erasing device is a device for erasing by replacing the portion of the marker in the image read by the copy scan with the image data such as the background color of the original.
Which portion is the marker portion is determined by the prescan reading marker 21-1. That is, the portion of the prescanning read marker 21-1 is the portion determined to be the marker, and this portion is replaced with the image data such as the background color of the original during the copy scan.

Therefore, the reading marker 2 at the time of copy scanning
A portion of 1-2 which is overlapped with the prescan reading marker 21-1 is replaced by image data such as the background color of the original, but the marker shift portion 24 which is a non-overlapped portion.
Is not replaced. As a result, as shown in FIG. 6B, the image data of the marker density remains in the marker shift portion 24. An object of the present invention is to solve such a problem.

[0022]

In order to solve the above-mentioned problems, in the marker erasing device of the present invention, a marker recognizing means for recognizing a marker portion from the read image data of the document at the time of prescan, and the marker recognizing means Marker data storage means for storing the marker data, comparison means for comparing the read image data of the original at the time of the copy scan and the marker density upper limit value, and the marker data stored in the marker data storage means for the copy scan. The density of the read image data is read as a result of comparison by the marker thickening means for processing as a marker portion at a pixel position within a predetermined width in the main scanning direction and the sub-scanning direction from the actual marker portion and the comparison means. The read image is smaller than the upper limit value of the marker density, and is read by the marker thickening means. When the pixel position of the data is processed as a marker portion, a preset unit that can erase the marker portion is selected, and in other cases, the read image data is directly selected. And decided to include.

[0023]

[Operation] At the time of copy scan, the area expanded by a predetermined width in the main-scanning direction and the sub-scanning direction from the marker part read at the time of pre-scan is treated as if it were the marker part. Then, even if the document set at the time of copy scanning is slightly displaced from the position set at the time of pre-scan, the marker portion read at the time of copy scanning remains in the expanded area, and the marker remains without being erased. That will disappear.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing the embodiments, the basic concept of the present invention will be described with reference to FIG. In FIG. 7, reference numeral 20 is a document, 21-1 is a prescan reading marker, 25 is an expansion marker, 26 is an expansion start position marker, W _X is an expansion width in the main scanning direction, and W _Y is an expansion width in the sub scanning direction.

As shown in FIG. 7A, in the present invention, the prescan reading marker 21-1, which is the data for determining which portion is the marker portion, is set in the main scanning direction and the sub scanning direction. To make the marker thicker by making it an enlarged marker 25 like a dotted line. The state after expansion is shown in FIG. The expansion width is selected to be a value slightly larger than the deviation width expected when setting the original. Then, even if the document set at the time of copy scanning is displaced, it will stay within the range of the enlarged marker 25 which is the thickened prescan reading marker, and the marker image will not remain.

FIG. 7B shows where the expansion start position marker 26 for setting the expansion start reference position is positioned. If the extension width is 1 pixel on both sides of the pre-scan reading marker 21-1 in both the main scanning direction and the sub-scanning direction, and the total extension width is 2 pixels,
First, the pre-scan reading marker 21-1 is shifted to the position (dotted line position) traced back in the opposite direction by one pixel which is half the total expansion width in each direction, and this is used as the expansion start position marker 26.

Next, as shown in FIG. 7C, the expansion start position marker 26 is expanded by the expansion width in each direction. In the case of expanding one pixel on each side, the total expanded width on both sides is 2 pixels.
_X also has 2 pixels, and the expanded width W _{Y in the} sub-scanning direction also has 2 pixels.

FIG. 7D shows the expanded result. As a result of being expanded as shown in FIG. 7C, the read marker 21-1 at the time of prescan is thickened, and the enlarged marker 2
It becomes 5. Since this portion is treated as a marker portion, even if the document set at the time of the copy scan is slightly displaced, the copy scan-time read marker 21-2 read at that time falls within the range of the enlargement marker 25. Therefore, all the marker images can be deleted.

(Embodiment) An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing a marker erasing device of the present invention. The reference numerals correspond to those in FIG.
-1 is a marker data storage unit, 2-2 is a sub scanning direction marker extension count value storage unit, and 8 is a marker thickening circuit. Those having the same reference numerals as those in FIG. 2 operate similarly. The marker thickening circuit 8 is a circuit that thickens the pre-scan reading marker by a predetermined width.

In the conventional memory device 2, the marker data a
However, in the present invention, the marker data storage section 2-1 is provided as an area for storing the same, and the storage area called the sub-scanning direction marker extension count value storage section 2-2 is also provided. Is also provided. This is used to store the sub scanning direction marker extension count value (which will be described later), which is required when the marker thickening circuit 8 performs the marker thickening process.

(1) Operation during prescan At the time of prescan, the read image data is input only to the marker recognition circuit 1, and if the density is within the marker recognition range, it is recognized as a marker, as in the conventional case. The marker data a is sent to the memory device 2. The marker data a is written in the marker data storage unit 2-1 as the data of the marker read during the prescan. This is the end of the prescan operation.

(2) Operation at Copy Scan At the time of copy scan, the read image data is the selection circuit 3
Is input to the comparison circuit 6. As described with reference to FIG. 5, the comparison circuit 6 checks whether or not the input image data is data at a position belonging to the overlapping portion 22-1 with the original image 22. If so, the output g is set to "0", and otherwise, it is set to "1".

In the selection circuit 3, if the AND circuit 7
If the output h from is "1", the data from the replacement level setting unit 4 is selected (corresponding to the deletion of the input image data), and if it is "0", the data is input. Image data is selected and output. The output h of the AND circuit 7 is determined by the output g of the comparison circuit 6 and the output f of the marker thickening circuit 8. Since the comparison circuit 6 has already been described, the marker thickening circuit 8 will be described here.

(3) Structure of Marker Thickening Circuit 8 FIG. 3 is a diagram showing the structure of the marker thickening circuit 8. In FIG. 3, 9 is a main scanning processing circuit, 91 is a selection circuit, and 9
2 is a counting unit, 93 is a binarizing circuit, 10 is a main scanning direction expansion width setting unit, 11 is a sub-scanning processing circuit, 111 is a selecting circuit, 112 is a counting unit, 113 is a binarizing circuit, and 12 is sub-scanning. Directional expansion width setting unit, 13 is an address generation circuit, 1
Reference numeral 31 is a main scanning address generation circuit, 132 is a main scanning offset address setting unit, 133 is a sub scanning address generation circuit, and 134 is a sub scanning offset address setting unit.

The extension width setting unit 10 in the main scanning direction is shown in FIG.
This is a part for setting the expanded width W _X in the main scanning direction of (C),
If you want to extend only W _X , set the value “W _X +1”. For example, when it is desired to expand one pixel on each side by a total of two pixels, the value "2 + 1", that is, "3" is set. "3" written in the main-scanning-direction expanded width setting unit 10 in FIG. 3 is the set value in that case. Similarly, the value "W _Y +1" is also set in the sub-scanning direction expansion width setting unit 12.

The main scanning offset address setting unit 132 and the sub scanning offset address setting unit 134 are shown in FIG.
It is set to obtain the expansion start position marker 26 in (b). The extension start position marker 26 shifts the prescan reading marker 21-1 read by the prescan by a few pixels in the direction opposite to the main scanning direction and the sub-scanning direction, and sets it as the start position of the extension process. It is a thing. In other words, it is obtained by shifting by "the amount of pixels to be thickened in the opposite direction to each direction". For example,
When it is desired to thicken by one pixel on both sides of the pre-scan reading marker 21-1, the number of pixels to be thickened in the opposite direction to each direction is 1 pixel respectively. “1” is set in each of the scanning offset address setting sections 134.

The address generated by the main scanning address generating circuit 131 is the main scanning offset address setting section 132.
Only the address set in is added. The same applies to the address generated by the sub-scanning address generation circuit 133. Therefore, when both are set to "1", a position advanced by "1" in the main scanning direction and "1" in the sub-scanning direction as compared with the case where there is no offset (that is,
This is an address that points to a position that is one pixel ahead in the lower right 45 ° direction.

Address d from the address generation circuit 13
As can be seen from FIG. 1, the marker data storage unit 2-
It is used to read out the marker data a from 1. When the read image data at the time of copy scan is sequentially input at each address, the address generation circuit 13 in the marker thickening circuit 8 outputs the address d obtained by adding the offset amount to the address. 7
In the case of (b), although the read image data that has been input is still the data at the position of the dotted line 26, the prescan reading marker 21-
The data at the position 1 is read.

The read result is as shown in FIG. The hatched portion 26 is data indicating that it is a marker portion, and the other portions are data indicating that it is not a marker portion. Since the area of the data indicating the marker portion is expanded starting from the shaded portion, the portion 26 is the extension start position marker.

FIG. 8 shows the distribution of marker data immediately before the start of expansion. This is an enlargement of FIG. 7C, and the pixel positions (1 to 14) in the main scanning direction and the line number (1 in the sub scanning direction
15 to 15) are filled in. However, the hatched lines shown in FIG. 7C are omitted. The portion of the expansion start position marker 26 is data “1” (high) indicating that it is a marker portion, and the other portions are data “0” (low) indicating that it is not a marker portion.

Note that FIG. 8 is not a diagram showing that such one page of data is actually stored in some memory. If the marker data a read by the marker thickening circuit 8 is recorded for only one page, the marker data value at each address is as described above. The expansion operation in each direction will be described below with reference to this drawing.

(3-1) Operation of Main Scan Processing Circuit 9 The marker data a read from the marker data storage section 2-1 is used as a signal to the selection circuit 91 and the counting section 92 of the main scan processing circuit 9. To be The count value of the count unit 92 is initially set to zero. The 0 is used as the input A of the selection circuit 91, and the set value of the main scanning direction expansion width setting unit 10 (assumed to be “3” in FIG. 3) is used as the input B.

When the marker data a read from the marker data storage section 2-1 is the data "1" (high) indicating that it is a marker portion, the selection circuit 91 selects the input B. When the data is “0” (low) indicating that it is not the marker portion, the input A is selected.
Therefore, since the address is advanced in the main scanning direction on a certain line and the marker data a is 0 until it reaches the extension start position marker 26, the input A (= 0).
Is selected. When the address enters the area of the extension start position marker 26, the marker data a is 1, so the input B (= 3) is selected.

When the marker data a is "1", the count section 92 is set with the value from the selection circuit 91 and outputs the value. When the marker data a is "0", the held count value is reduced by 1 and the reduced value is output. Therefore, at the address where the marker data a is "1" (in other words, the address within the area of the extension start position marker 26), the count output of the counting unit 92 is "3", but the address advances in the main scanning direction. Then, the count output at the address after exiting the area of the expansion start position marker 26 becomes a value that is sequentially decremented by 1 as described later with reference to FIG.

The count output of the count section 92 is binarized by the binarization circuit 93 into "1" (high) and "0" (low). The threshold for binarization is a value between 1 and 0 (for example, 0.5
), And it is discriminated whether the count output is 1 or more or 0. An address whose output from the binarization circuit 93 is 1 is treated as an address belonging to the marker portion.
When "3" is set in the main scanning direction expansion width setting unit 10, the value of 1 or more may be "3", "2", or "1". The area where the count unit 92 takes these values indicates the entire area of the marker extended in the main scanning direction, and thus the count value of the counting unit 92 can be referred to as a “main scanning direction marker extension count value”.

FIG. 9 is a diagram for explaining changes in the marker extension count value in the main scanning direction. 26-1 is a marker end pixel position in the main scanning direction, and 27 to 29 are pixel positions subsequent thereto. Main scanning direction marker end pixel position 26-1
As shown in FIG. 8, the expansion start position marker 26
Among the pixel positions of, the pixel position of the end portion traced in the main scanning direction. This pixel position is the expansion start position marker 26
The count output of the counting unit 92 is “3”.

As the address advances in the main scanning direction, pixel position 2
When it reaches 7, it looks like this: The pixel position 27 is
Since it is a pixel position that has left the area of the extension start position marker 26, the marker data a read from the marker data storage unit 2-1 is “0”. Therefore,
The selection circuit 91 selects the input A (= 3 ← the count value of the counting unit 92 at the previous pixel position is 3), and the counting unit 92 subtracts 1 from the input A (= 3).
Therefore, the count value of the pixel position 27 is 2.

When the address advances and reaches the next pixel position 28, the value of the input A becomes 2 which is the previous count value. Since the pixel position 28 is also outside the area of the extension start position marker 26, the marker data a read from the marker data storage unit 2-1 is “0”. Therefore, the selection circuit 91 selects the input A (= 2), and the count unit 92 subtracts 1 from the input A, so that the count value becomes 1. The same operation is performed at the next pixel position 29, and the count value becomes zero. In the present invention, since a pixel position having a count value of 1 or more is treated as a marker portion, a pixel treated as a marker portion is extended by two pixels behind the marker end pixel position 26-1 in the main scanning direction in the main scanning direction. It has been done.

FIG. 10 is a diagram showing the distribution of marker extension count values in the main scanning direction. The reference numerals correspond to those in FIG. Only the count value of 1 or more is shown. The count value of the pixel position not shown is 0. When the address is advanced to the next, the count value of the count unit 92 also changes to the value at that address. FIG. 10 shows that if the count value at each address is recorded, such a distribution will be obtained. The portions where the count values are “2” and “1” are the portions expanded in the main scanning direction.

(3-2) Operation of Sub-scan Processing Circuit 11 The output k of the main-scan processing circuit 9 is used as a signal to the selection circuit 111 and the counting section 112 of the sub-scan processing circuit 11. The count value of the counting unit 112 is initially set to 0. The binarization circuit 113 sets a count value of 1 or more to "1" (high) and a count value of 0 to "0" (low).
And The output f of the binarization circuit 113 is used as one input to the AND circuit 7 in FIG.

A sub-scanning direction marker extension count value b read from the sub-scanning direction marker extension count value storage unit 2-2 in FIG. 1 is input as an input C of the selection circuit 111, and an input D is a sub-scanning direction. The setting value of the expansion width setting unit 12 (assuming "3") is input.

FIG. 11 is a diagram showing the sub-scanning direction marker extension count value storage unit 2-2. This storage section has a capacity for storing data corresponding to pixel positions for one line of the document. When the address is advanced in the main scanning direction, the count value of the count unit 112 at each address is written in this. When the count value is 1 or more, the address is treated as a marker portion, but the sub-scanning direction marker extension count value storage unit 2-2 in which this count value is written has the scanning moved one line down. In this case, it plays a role of storing which address of the previous line belongs to the marker portion.
In other words, it indicates a pixel position that can be expanded in the sub-scanning direction. The initial value of the sub scanning direction marker extension count value storage unit 2-2 is set to 0.

When the address of the read image data input in FIG. 1 is the Nth address from the beginning of a line, the subscanning direction marker extension count value storage unit 2
-2, the count value written in the Nth address from the beginning is read and used as the input C of the selection circuit 111.

When the main scanning processing output k is data "1" (high) indicating that it is a marker portion (when the count value is 1 or more in FIG. 10), the selection circuit 11
At 1, the input D (= 3 ← the set value of the sub-scanning direction expansion width setting unit 12) is selected. When the data is "0" (low) indicating that it is not a marker portion (when the count value is 0 in FIG. 10), the input C is selected.

When the main scanning processing output k is "1", the counting section 112 is set with the value from the selection circuit 111 and outputs the value. When the main scanning processing output k is "0", the held count value is reduced by 1 and the reduced value is output. Therefore, the address at which the main scanning processing output k is "1" (the address whose count value is 1 or more in FIG. 10)
Then, the count output of the count unit 112 is "3", but the count output at other addresses is as shown in FIG.
Change as described in 2.

FIG. 12 is a diagram for explaining changes in the marker extension count value in the sub-scanning direction after each line main scanning. The address numbers in the main scanning direction and the line numbers in the sub scanning direction correspond to those in FIG.

(A) In the case of line 1 ... FIG. 12 (a) As can be seen from FIG. 10, in line 1, the main scanning processing output k
Is 0 (low) at any address, the selection circuit 1
At 11, the input C is always selected. Since the initial value of the sub scanning direction marker extension count value storage unit 2-2 is set to 0, all the read values are 0. Counting unit 11
In 2, since the main scanning processing output k is 0, 0 which is an input from the selection circuit 111 can be subtracted from 1. However, the minimum value of the output of the counting unit 112 is set to 0, and the output is set to 0 when 1 is subtracted from 0. Therefore, 0 is sent to the binarization circuit 113 at any address, and 0 is written in the sub-scanning direction marker extension count value storage unit 2-2 as the sub-scanning direction marker extension count value e. Therefore, the value of the sub scanning direction marker extension count value storage unit 2-2 at the stage when the scanning of the line 1 is completed is as shown in FIG. The same applies to the case of line 2.

(B) In the case of line 3 ... FIG. 12 (b) As can be seen from FIG. 10, the count value is 1 or more at the 3rd to 12th addresses in the main scanning direction, so the main scanning processing output k is It is 1 (high). Therefore, the input D (= 3) is selected in the counting unit 112, and the counting unit 11
In 2, the value (3) is set and output. Therefore, the sub-scanning direction marker extension count value e at the third to twelfth addresses in the main scanning direction becomes 3, and this is written in the sub-scanning direction marker extension count value storage unit 2-2.

Since the count value in FIG. 10 is 0 at the first, second, and thirteenth and fourteenth addresses in the main scanning direction, the main scanning processing output k is 0 (low). Therefore, as the input C, the value of 0 read from the corresponding address of the sub scanning direction marker extension count value storage unit 2-2 is input, and the count unit 112 subtracts 1 from the value.
The minimum value is set to 0. This 0 is sent to the binarization circuit 113 and is also sent to the sub-scanning direction marker extension count value storage unit 2-2 as the sub-scanning direction marker extension count value e. Thus, the value of the sub scanning direction marker extension count value storage unit 2-2 at the stage when the scanning of the line 3 is finished is
It is as shown in FIG.

(C) Line 4 ... FIG. 12 (c) As can be seen from FIG. 10, the count value becomes 1 or more at the third to fifth addresses and the tenth to twelfth addresses in the main scanning direction. Therefore, the main scanning processing output k is 1 (high). Therefore, the input D "3" is written to the address of the sub scanning direction marker extension count value storage unit 2-2.

At the 6th to 9th addresses in the main scanning direction, the count value in FIG. 10 is 0, so the main scanning processing output k becomes 0, and the input C is selected by the selection circuit 111. The values at these addresses stored in the sub scanning direction marker extension count value storage unit 2-2 are “3” as shown in FIG. Since the main scanning processing output k is 0, the count unit 112 subtracts 1 from 3 to obtain “2”. This 2 is sent to the binarizing circuit 113, and at the same time, the sub scanning direction marker extension count value storage unit 2-2.
And is written to the corresponding address.

The 1st to 2nd addresses in the main scanning direction and the 13th and 14th addresses are the same as in the case of line 3. Thus, the value of the sub scanning direction marker extension count value storage unit 2-2 at the stage when the scanning of the line 4 is finished is as shown in FIG.

With respect to the lines 5, 6, 11 to 14, the same operations as described above are performed, as shown in FIGS.

FIG. 13 is a diagram showing the distribution of the marker extension count values in the sub-scanning direction thus obtained. The reference numerals correspond to those in FIG. Although only the count value of 1 or more is written, the count value of the address not written is 0. An address part with a count value of 1 or more is treated as a marker part. This portion is nothing but the portion of the enlarged marker 25 in FIG.

When the scanning line is advanced to the next, the count value stored in the sub scanning direction marker extension count value storage unit 2-2 also changes. FIG. 13 shows that if the count value in each line is recorded, such a distribution will be obtained. The portions where the count values are “2” and “1” indicate the portions expanded in the sub-scanning direction.

The count output of the counting section 112 is binarized by the binarization circuit 113 into "1" (high) and "0" (low). The threshold for binarization is a value between 1 and 0 (for example,
0.5), and it is distinguished whether the count output is 1 or more or 0. An address whose output from the binarization circuit 113 is 1 is treated as an address belonging to the marker portion. When "3" is set in the sub-scanning direction expansion width setting unit 12, the value of 1 or more can be "3", "2", or "1". Since the area where the count output of the counting unit 112 takes those values indicates the entire area of the marker extended in the sub-scanning direction, the count value of the counting unit 112 is referred to as a sub-scanning direction marker extension count value. I can.

Although the marker erasing device according to the present invention is configured by hardware in the above-described embodiments, the present invention can be realized by configuring by software.

[0068]

As described above, according to the marker erasing apparatus of the present invention, at the time of copy scan, the marker portion read at the time of prescan is expanded by a predetermined width in the main scanning direction and the subscanning direction. , Treat it as if it were a marker part. Therefore, even if the document set at the time of the copy scan is slightly displaced from the position set at the time of the pre-scan, the marker portion read at the time of the copy scan remains in the expanded area, and the marker remains without being erased. That will disappear.

[Brief description of drawings]

FIG. 1 is a diagram showing a marker erasing device of the present invention.

FIG. 2 is a diagram showing a conventional marker erasing device.

FIG. 3 is a diagram showing a configuration of a marker thickening circuit.

FIG. 4 is a diagram illustrating a document image and a marker.

FIG. 5 is a diagram showing a situation in which a marker overlaps an original image.

FIG. 6 is a diagram showing a situation in which some of the markers remain without being erased.

FIG. 7 is a diagram for explaining the basic idea of the present invention.

FIG. 8 is a diagram showing a distribution of marker data immediately before the start of expansion.

FIG. 9 is a diagram for explaining changes in the main scanning direction marker extension count value.

FIG. 10 is a diagram showing a distribution of marker extension count values in the main scanning direction.

FIG. 11 is a diagram showing a sub scanning direction marker extension count value storage unit.

FIG. 12 is a diagram for explaining changes in the marker extension count value in the sub-scanning direction after each line main scanning.

FIG. 13 is a diagram showing a distribution of marker extension count values in the sub-scanning direction.

[Explanation of symbols]

1 ... Marker recognition circuit, 2 ... Memory device, 2-1 ... Marker data storage section, 2-2 ... Sub scanning direction marker extension count value storage section, 3 ... Selection circuit, 4 ... Replacement level setting section, 5 ... Marker density Upper limit value setting unit, 6 ... Comparison circuit, 7
... AND circuit, 8 ... Marker thickening circuit, 9 ... Main scanning processing circuit, 91 ... Selection circuit, 92 ... Counting unit, 93 ... Binarizing circuit, 10 ... Main scanning direction expansion width setting unit, 11 ... Sub scanning processing circuit , 111 ... Selection circuit, 112 ... Count unit, 1
13 ... Binarization circuit, 12 ... Sub-scanning direction expansion width setting unit, 1
3 ... Address generation circuit, 131 ... Main scanning address generation circuit, 132 ... Main scanning offset address setting unit, 133
... Sub-scanning address generation circuit, 134 ... Sub-scanning offset address setting unit, 20 ... Original document, 21 ... Marker, 21-
DESCRIPTION OF SYMBOLS 1 ... Prescan reading marker, 21-2 ... Copy scan reading marker, 22 ... Original image, 22-1 ... Overlapping part, 23 ... Main scanning line, 24 ... Marker shift part, 2
5 ... Enlargement marker, 26 ... Expansion start position marker, 26
-1 ... Marker end pixel position in main scanning direction, 27, 28,
29 ... Pixel position, a ... Marker data, b ... Sub scanning direction marker extension count value, k ... Main scanning processing output, d ... Address, e ... Sub scanning direction marker extension count value, f,
g ... Output, W _X ... Main scanning direction expanded width, W _Y ... Sub scanning direction expanded width

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Koichi Okamura 3-7-1, Fuchu, Iwatsuki-shi, Saitama Fuji Zerox Corporation (72) Inventor Takashi Nakajima 3-7-1, Fuchu, Iwatsuki-shi, Saitama Prefecture Fuji Xerox Co., Ltd. (72) Inventor Hiroshi Hayashi 3-7-1 Fuchu, Iwatsuki City, Saitama Prefecture Fuji Xerox Co., Ltd.

Claims (2)

[Claims] 1. A marker recognition means for recognizing a marker portion from read image data of a document at the time of prescan, a marker data storage means for storing the marker data from the marker recognition means, and a read image of the document at the time of copy scan. Comparing means for comparing the data and the upper limit of the marker density, and the marker data stored in the marker data storage means are read out at the time of the copy scan, and a predetermined width in the main scanning direction and the sub scanning direction from the actual marker portion is read. As a result of the comparison by the marker thickening means for processing as a marker portion at the pixel position inside and the comparing means, the density of the read image data is smaller than the marker density upper limit value, and the pixel of the read image data is made by the marker thickening means. A marker if the position was treated as a marker part A marker erasing device comprising: a selection unit that selects preset data from which a part can be erased and otherwise selects the read image data as it is. 2. The marker thickening means is preset with an address generating means for generating an address used for reading out the marker data from the marker data storage means and a pixel position to which the data of the marker portion is output. A main scanning processing means for expanding the main scanning direction by a predetermined width, and a sub scanning processing means for expanding the pixel position where the data of the marker portion is output in the sub scanning direction by a preset width. The marker erasing device according to claim 1, wherein: