JPH089191A - Field discrimination circuit - Google Patents

Abstract

PURPOSE:To provide the field discrimination circuit which is suppressed in mounting area and is stable against temperature changes. CONSTITUTION:A pulse generator 10 receives a composite synchronizing signal A and outputs of a horizontal synchronizing signal pulse B and a clock pulse C with period 0.5H synchronized with the horizontal synchronizing pulse B. An inverter 11 inverts the composite synchronizing signal A. An AND gate 12 detects a vertical synchronizing signal A2. A latch circuit 13 provides an output of a pulse F to latch a detection state of the vertical synchronizing signal A2. A counter 14 starts count of the clock pulse C when the pulse F is outputted and generates a pulse G when the five pulses C are counted. A D-FF 15 detects a level of the composite synchronizing signal A at the rising time of the pulse G.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field discrimination circuit suitable for field discrimination of an interlaced television video signal.

[0002]

2. Description of the Related Art FIG. 4 is an external view of a liquid crystal compact television. The liquid crystal compact television 1 is composed of a liquid crystal display unit 1a of about 5 inches, an outer frame 1b, and a printed wiring board 1c on which a circuit for driving the liquid crystal display unit 1a is mounted. The printed wiring board 1c is provided on the back side of the liquid crystal display unit 1a so as to face the liquid crystal display unit 1a. As shown in the figure, since the liquid crystal display section 1a is extremely small, the outer size and the height dimension of the printed wiring board 1c are severely limited. Further, a large number of circuits such as a tuner circuit, an audio circuit, a luminance signal processing circuit and a color signal processing circuit forming a video signal, and a liquid crystal display circuit are mounted on the printed wiring board 1c.

By the way, the image displayed on the liquid crystal compact television is composed of television video signals. As is well known, NTSC (National Television System Com)
mittee) method or PAL (Phase Alternation by L)
In the television video signal of the ine) system or the like, interlaced scanning is performed at the time of capturing an image, so that one image is configured by the first field and the second field. There is a field discriminating circuit in the circuit for discriminating between the first field and the second field. In the liquid crystal compact television, the component parts of the field discriminating circuit are miniaturized as much as possible from the above-mentioned circumstances, and the printed wiring board 1c. It is necessary to reduce the mounting area above.

[0004]

However, conventionally, this field discriminating circuit is an analog integrator circuit which uses a lot of discrete parts and a field discriminating dedicated I which is commercially available.
It was composed by combining C. For this reason, there is a limit in suppressing the mounting area of the field determination circuit, and there is a problem that the characteristics of the circuit are easily affected by temperature because the analog integration circuit is used.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a field discriminating circuit capable of suppressing the mounting area of the field discriminating circuit and operating stably with respect to a temperature change. To do.

[0006]

In order to solve the above-mentioned problems, the field discriminating circuit according to the first aspect of the invention has a horizontal synchronizing signal immediately before a first equivalent pulse included in a vertical synchronizing signal period of a composite video signal for television broadcasting. It is characterized in that the field is discriminated by the level of the composite synchronizing signal from 6.5 pulses after the horizontal scanning period to 7.0 horizontal scanning periods after the pulse.

In order to solve the above problems, the field discriminating circuit of the present invention receives a composite sync signal obtained from a television video signal, forms a horizontal sync pulse from the composite sync signal, and outputs the horizontal sync pulse. A pulse generation circuit that outputs a pulse signal having a frequency higher than that of the horizontal synchronization pulse and that is synchronized with the horizontal synchronization pulse, and the horizontal synchronization pulse is first generated after the generation timing of the vertical synchronization signal included in the composite synchronization signal. Detecting means for detecting the time point to, and counting the pulse signal having a frequency higher than the horizontal synchronizing pulse after the time point when the detecting means outputs the detection signal,
Counting means for outputting a signal when the count value reaches a constant value, and the level of the composite synchronizing signal is checked at the time when the signal is output from the counting means, and a field discrimination signal is determined based on the check result. It is provided with a field discriminating means for outputting.

According to a third aspect of the present invention, in order to solve the above-mentioned problem, in the field discriminating circuit according to the second aspect, the detecting means inverts the composite synchronizing signal, and an output signal of the inverter. An AND gate that outputs a logical product signal with the horizontal sync pulse and a time point at which the horizontal sync pulse first occurs after the generation timing of the vertical sync signal included in the composite sync signal with the logical product signal as an input is detected. And a latch circuit.

[0009]

The vertical synchronizing signal and the horizontal synchronizing signal included in the television video signal have different phases in the first field and the second field. The field discriminating circuit according to any one of claims 1 to 3 utilizes this phase difference to perform field detection.
That is, the detecting means detects the time when the horizontal synchronizing pulse is first generated after the timing of generating the vertical synchronizing signal. Due to the above-mentioned phase difference, the detection result by this detection means differs between the first and second fields. As a result, after the detection signal is output from the detection means, the level of the composite synchronization signal at the time when the signal is output from the counting means after a lapse of a certain time becomes different levels in the first and second fields. It becomes possible to detect.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A case in which the field discriminating circuit according to the present invention is applied to an NTSC system television image signal will be described with reference to FIGS. FIG.
Is a circuit diagram of the field discrimination circuit according to the present embodiment, FIG. 2 is a timing chart showing the detection operation of the first field,
FIG. 3 is a timing chart showing the detection operation of the second field.

In FIG. 1, reference numeral a is a terminal to which a negative composite sync signal A separated from a television video signal is applied. The composite sync signal A shown in FIG. 2 represents a waveform near the vertical blanking period of the first field, and the composite sync signal A shown in FIG. 3 represents a waveform near the vertical blanking period of the second field. It represents. As shown in these figures, the composite sync signal A has one horizontal period (hereinafter, 1
It is composed of a horizontal synchronizing signal A1 and a vertical synchronizing signal A2 having a pulse width corresponding to 3H. Serrations A3 are inserted at intervals of 0.5H in the vertical synchronizing signal A2, and before and after the vertical synchronizing signal A2,
The equivalent pulse A4 is inserted at intervals of 0.5H.

The pulse generator 10 detects only the horizontal synchronizing signal component from the composite synchronizing signal A input to the terminal a, and 0.75H after the falling time t6 of the horizontal synchronizing signal A1 of the composite synchronizing signal A. A horizontal synchronizing pulse B having a rising interval of 1H and a clock pulse C having a period of 0.5H in synchronization with the horizontal synchronizing pulse B are output.

Here, the delay time T1 from the fall of the vertical sync signal A2 with respect to the rise of the horizontal sync pulse B in the first field is 0.75H, while
The delay time T2 from the fall of the vertical sync signal A2 with respect to the rise of the horizontal sync pulse B in the second field is 0.25H.

The inverter 11 inverts the composite synchronizing signal A and outputs a positive composite synchronizing signal D. The AND gate 12 forms a pulse signal E (see FIGS. 2 and 3) by taking the AND of the positive polarity composite synchronizing signal D and the horizontal synchronizing pulse B, and outputs the pulse signal E. The latch circuit 13 reads the signal “H” at the terminal D at the rising edge of the pulse signal E and outputs it as a signal F (see FIGS. 2 and 3). Then, it is reset at time t5 by a reset pulse (not shown) output from the counter 14 described next.

The counter 14 receives the signal F and the clock pulse C, and starts counting the clock pulse C when the signal F rises at time t1. Then, when five clock pulses C are counted, a pulse signal G having a pulse width corresponding to a half cycle of the clock pulse C is output,
Then it is reset. A D-FF (delay flip-flop) 15 reads the composite synchronizing signal A at the terminal D at the rising timing of the pulse signal G and outputs it as a field detection signal FD (see FIGS. 2 and 3).

In the above structure, as shown in FIG. 2, in the first field, the signal F rises with a delay of time T1 (0.75H) from the falling time t0 of the vertical synchronizing signal A2, while in the second field. , As shown in FIG. 3, from the falling time t0 of the vertical synchronizing signal A2 to the time T2.
The signal F rises with a delay of (0.25H). As a result,
In the first field, the composite synchronizing signal A is at "H" level when the pulse signal G rises, and in the second field, the composite synchronizing signal A is at "L" level when the pulse signal G rises. Therefore, the field detection signal FD becomes "H" in the first field and "L" in the second field, which enables field detection.

According to the field discriminating circuit having the above structure,
The field discriminating circuit can be configured only by a digital circuit without using discrete components such as a resistor or a capacitor. As a result, the following effects can be obtained. (1) Since the circuit can be configured as one ASIC (application-specific integrated circuit), the number of components can be reduced, the mounting area on the printed wiring board can be suppressed, and the power consumption can be reduced. is there. (2) The circuit operation becomes stable against changes in the ambient temperature. (3) The circuit operation is less likely to be affected by the power supply voltage.

In the structure of the field discriminating circuit described above, the period of the clock pulse is 0.5H, but the period of the clock pulse may be any other period as long as it is 0.5H or less. However, in this case, it is necessary to change the count value for outputting the pulse signal G by changing the cycle of the clock pulse.

The field discriminating circuit according to the present invention can also be applied to a PAL system television video signal. However, in this case, the count value of the counter 14 needs to be changed.

[0020]

The field discriminating circuit according to the present invention is
Since it is composed of a digital circuit, the mounting area on the printed wiring board can be reduced, and thus the liquid crystal compact television can be miniaturized. In addition, low power consumption can be achieved and stable operation with respect to fluctuations in ambient temperature or power supply voltage can be obtained, so that the operating performance of the liquid crystal compact television can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a field discrimination circuit according to the present invention.

FIG. 2 is a timing chart illustrating a first field detection operation of the field determination circuit according to the present invention.

FIG. 3 is a timing chart illustrating a first field detection operation of the field determination circuit according to the present invention.

FIG. 4 is a diagram showing an example of an external appearance of a liquid crystal compact television.

[Explanation of symbols]

 10 pulse generator 11 inverter 12 AND gate 13 latch circuit 14 counter 15 D-FF

Claims (3)

[Claims] 1. A period from 6.5 horizontal scanning periods to 7.0 horizontal scanning periods after the horizontal synchronization pulse immediately before the first equivalent pulse included in the vertical synchronization signal period of the composite video signal for television broadcasting. A field discrimination circuit characterized by discriminating a field according to the level of a composite synchronizing signal. 2. A composite sync signal obtained from a television video signal is input, a horizontal sync pulse is formed and output from the composite sync signal, and the horizontal sync pulse is synchronized with the horizontal sync pulse.
And a pulse generating circuit for outputting a pulse signal having a frequency higher than that of the horizontal synchronizing pulse, and a detecting means for detecting a time point at which the horizontal synchronizing pulse first occurs after the generation timing of the vertical synchronizing signal included in the composite synchronizing signal. Counting means for counting the pulse signals having a frequency higher than that of the horizontal synchronizing pulse after the detection means outputs the detection signal, and outputting the signal when the count value reaches a constant value; A field discriminating circuit comprising a field discriminating means for checking the level of the composite synchronizing signal at the time when the signal is output, and outputting a field discriminating signal based on the check result. 3. The detecting means receives an inverter for inverting the composite synchronizing signal, an AND gate for outputting a logical product signal of the output signal of the inverter and the horizontal synchronizing pulse, and the logical product signal as an input. 3. The field discriminating circuit according to claim 2, further comprising: a latch circuit for detecting a time point at which the horizontal synchronizing pulse is first generated after the generation timing of the vertical synchronizing signal included in the composite synchronizing signal.