JPH0896525A - Data processing device - Google Patents

Abstract

(57) [Summary] [Object] To provide an apparatus capable of detecting a predetermined frequency component in modulated data more accurately and effectively without increasing the circuit scale. A data processing device is a device that adds control data to each predetermined number of input data and performs predetermined modulation, and that follows the predetermined number of input data following the control data depending on the state of the control data. And a modulation means for modulating the input data so that a part of the predetermined number of data is affected, and a single control data is affected by both the predetermined number of input data and the predetermined number of data. And a detection means for detecting a specific frequency component in the modulated data based on the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device,
In particular, the present invention relates to a device that digitally modulates input data and outputs it.

[0002]

2. Description of the Related Art As an apparatus of this type, for example, a digital VTR for recording / reproducing a digital signal on / from a recording medium has been conventionally known.

Among such digital VTRs, particularly for consumer use, when recording a digital signal on a magnetic tape, the recording density is increased by narrowing the track width as much as possible to increase the consumption of the magnetic tape. Need to be less. As a result of narrowing the recording track width in this way, so-called tracking, in which the head correctly traces the recording track, is important in order to correctly reproduce the recording signal.

An apparatus for multiplexing a pilot signal for tracking in a digital VTR with a recording signal is disclosed in Japanese Patent Laid-Open No. 255969/1992.

FIG. 8 is a block diagram showing a conventional structure of an apparatus for multiplexing a pilot signal of this kind with a recording signal.

In FIG. 8, the recording signal input from the input terminal 601 is a "0" addition circuit 602 for every 24 bits.
And "1" are added to the addition circuit 603, and "0" and "1" are added as control bits, respectively, and output to the 2T precoders 604 and 605. Precoder 604,6
05 is 25-bit data interleaved NRZI
It modulates and outputs to the component extraction circuits 606 and 607, the bit continuity detection circuits 608 and 609, and the selection circuit 610.

The component extraction circuits 606 and 607 calculate the predetermined frequency component and DC component of the pilot signal to be multiplexed in the concatenated signal sequence of the already encoded signal sequence and the supplied 25-bit information word, and calculate The correlation with the pilot signal component is detected and output to the comparison circuit 610.

The comparison circuit 610 compares the component supplied from the component extraction circuit 606 with the component supplied from the component extraction circuit 607, and the selection circuit 611 is provided with a signal indicating the more correlated pilot signal component. Output.

The bit continuity detection circuits 608 and 609 calculate the maximum number of consecutive "0" s or "1" s in the supplied 25-bit information word, and output it to the selection circuit 611. The selection circuit 611 is basically a precoder 604, 60.
Among the 25 bits supplied by 5, the information word on the side indicated by the signal from the comparison circuit 610 is output to the output terminal 612.

However, when one of the maximum numbers supplied from the bit continuity detecting circuits 608 and 609 is, for example, 10 or more, the selecting circuit 611 gives priority to the output terminal 612 of the 25-bit information word having the smaller maximum number. Output.

[0011]

However, in the conventional example as described above, a precoder, a component extraction circuit and a bit continuity detection circuit are required on each of the side to which "0" is added and the side to which "1" is added, The circuit scale becomes large.

Further, it is conceivable that the precoder, the component extracting circuit and the bit continuity detecting circuit are shared by the "0" addition side and the "1" addition side and used for time division. In this case, the operation clock of the device is accelerated. Necessary and costly.

In view of the above problems, the present invention has an object of providing an apparatus capable of detecting a predetermined frequency component in modulated data more accurately and effectively without increasing the circuit scale. And

[0014]

SUMMARY OF THE INVENTION In order to solve the problems conventionally held and to achieve the above object, the present invention is an apparatus for adding control data for each predetermined number of input data and performing predetermined modulation. The state of the control data affects a part of the predetermined number of input data following the control data and a part of the other predetermined number of data subsequent to the predetermined number of input data. A specific frequency in the modulated data based on data that is affected by a single control data in both the predetermined number of input data and the other predetermined number of data And a detection means for detecting the component.

[0015]

Since the present invention is configured as described above, the specific frequency component in the modulated data can be detected accurately and effectively with a simple structure.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings.

In this embodiment, the case where the present invention is applied to a digital VTR will be described. FIG. 1 is a block diagram showing a schematic structure of a recording system of a digital VTR for multiplexing and recording pilot signals for tracking control according to the present invention.

In the figure, 1 is an input terminal for inputting a digital signal including a video signal, an audio signal and the like, 2 is an encoding for the digital signal input from the input terminal 1, and I
This is a digital signal processing circuit for adding a D code, a synchronization code, an error correction code, etc. In this embodiment, 24-bit data (hereinafter referred to as a code word), which is obtained by simultaneously outputting three 8-bit data for one word, The signals are output in parallel from the circuit 2.

The 24-bit data is supplied to the modulation circuits 3 and 4, respectively. These modulation circuits 3 and 4 convert the above-mentioned 24-bit data into 25-bit data and, at the same time, return the amount of predetermined frequency f1, f2 component and DC component when this data group is returned to the bit stream, as will be described later. Adjust and output.

The modulation circuit 3 outputs a bit stream in which the respective components of f1, f2 and DC are suppressed, and the modulation circuit 4 similarly suppresses the respective components of f1, f2 and DC and f1.
Alternatively, the bitstream having the f2 component is output.

In FIG. 1, 5 and 6 are recording amplifiers,
The bit streams output from the modulation circuits 3 and 4 are input to the head ch1 and the head ch3, the head ch2 and the head ch4, respectively.

Next, referring to FIG. 1 as a first embodiment of the present invention.
The modulation circuits 3 and 4 in FIG.

FIG. 2 is a block diagram showing the configuration of the modulation circuits 3 and 4. In FIG. 2, the digital signal processing circuit 10
The data output from 2 is input to the input terminal 10 every 24 bits.
1 is input, and the separation circuit 102 separates it into a data string of 12 odd-numbered bits and a data string of 12 even-numbered bits. Then, the odd-numbered data string is output to the 12-bit register 103, and the even-numbered data string is output to the 12-bit register 104.

In the present embodiment, since the 24-bit input data is processed from the odd-numbered data string, the switches SW1 and SW2 are first connected to the a side. Register 10
The odd-numbered data string stored in No. 3 is supplied to the 1T precoder 105 via the switch SW1, where NRZ
I modulation is applied. This is a process of taking the EXOR of each data that is continuously input. The output of the precoder 105 is supplied to the 24-bit register 107 via the switch SW2 and is also output to the determination circuit 106.

The 1T precoder 105 will be described below with reference to FIG.
The determination circuit 106 will be described.

FIG. 3 is a block diagram showing the configuration of the 1T precoder 105 and the decision circuit 106. In FIG.
12-bit data string from switch SW1 is EXOR
It is serially supplied to the circuit 201, and the 1-bit register 2
EXOR with the data one clock before output from 02
Is output. The output of the EXOR circuit 201 is delayed by one clock by the 1-bit register 202, is fed back to the EXOR circuit 201, and the determination circuit 106 is also provided.
Is supplied to.

In the decision circuit 106, the precoder 10
The 12-bit output data 5 is EXOR circuits 207 to 2
10 and the up / down counter 211 are serially supplied. Further, the signal generating circuits 203 to 206 generate binary rectangular wave signals indicating the sin component and the cos component at the frequencies f1 and f2 of the pilot signals to be multiplexed, and each EX signal.
It outputs to the OR circuit to 207-210. EXOR circuit 2
07-210 take the EXOR of the input 12-bit data and each pilot component and output it to the up / down counters 212-215.

The up / down counters 211 to 215 are reset when the processing for the odd-numbered 12 bits in each 24-bit data is completed. Then, when the input data is "1", the internal register is set to +1 and when the input data is "0", the internal register is set to -1. Total 24 of even 12 bits in 24-bit data
The component extraction circuit 21 calculates the calculation result for the bit data.
6 to 219. FIG. 4 shows the configuration of the component extraction circuit.

In FIG. 4, the up / down counter 21
The outputs of 2 to 215 are supplied to the adder 303 and the subtractor 304, where they are respectively calculated with the output of the register 301. In the register 301, the result of the operation so far described below (the odd-numbered 12-bit data in one codeword inputted immediately before and the 1 inputted before that)
The history of the operation result of even-numbered 12-bit data in the codeword is stored in the adder 303.
Outputs the sum of the input data and the data in the register 301 to the absolute value circuit 305. Further, the subtractor 304 subtracts the input data from the data of the register 301 and outputs it to the absolute value circuit 306. This operation is based on the last input 1
Precode (NRZI) is performed by adding a different bit (“0” or “1”) to the beginning of a total of 24 bits of the even-numbered 12 bits of the codeword and the currently input odd-numbered 12-bit data. In this case, the sum of the output of the up / down counter and the output of the register 301 is obtained.

The absolute value circuits 305 and 306 respectively calculate the absolute value of the input data and output it to the subtractor 307. The subtractor 307 calculates the absolute value circuit 3 from the output of the absolute value circuit 305.
The output of 06 is subtracted and output to the adders 222 to 224.

The outputs of the component extraction circuits 216 to 219 are added by the adders 222 to 224, respectively, and the adder 22
5 is output.

The up / down counter 211, like the above-described up / down counter, calculates 24-bit data continuously input as it is and outputs it to the component extraction circuit 220. This means that the DC component in the input 24-bit data is calculated. The component extraction circuit 220 performs the same calculation on the input data and outputs the result to the adder 225. The adder 225 adds the output from the adder 224 and the output from the component extraction circuit 220 to add the code check circuit 2
21 is output.

The sign check circuit 221 outputs "1" when the input data is positive and outputs "0" when the input data is negative.

In this embodiment, the binary rectangular wave signal of sin and cos components of each pilot signal is EXORed with the input data, and the result is calculated by the up / down counter. Therefore, the output of the up / down counter indicates the phase difference between the input data and the pilot signal component.

That is, when the absolute value of the output of the up / down counter is small, the phase difference with each rectangular wave signal is small, and when the absolute value is large, the phase difference with each rectangular wave signal is large. Is. In the present embodiment, the smaller absolute value of the output of the up / down counter and the addition result of the register 301 is output as the final modulation data. Therefore, in the present embodiment, the adder 30
The output of 3 represents the processing result of the data when the control data “0” is added to the input 12 bits and precoded, and the output of the subtractor 304 is precoded by adding the control data “1”. The data processing result is shown.

When all the processing for this odd-numbered 12-bit data string is completed, the output of the code check circuit 221 is output from the decision circuit 106 to the synthesizing circuit 109, and the selection signals s in the respective component extracting circuits 216 to 220 are output.
It is output as el. The switch 302 in FIG. 4 switches according to this selection signal, and in the present embodiment, it is connected to the a side when the output of the code check circuit 221 is "0", and connected to the b side when it is "1". Therefore, when the output of the code check circuit 221 is "0", the output of the adder 303 is selected, and when it is "1", the output of the subtractor 304 is selected.

Here, the fact that the output of the code check circuit 221 is "0" means that the absolute value of the output of the absolute value circuit 305 is smaller as described above. And
In the present embodiment, since the output of the adder 303, which is the data with the smaller absolute value, is selected and stored in the register 301, the register 301 stores the data with the smaller phase difference from the pilot component, that is, the history information. The data that matches the rectangular wave signal representing each pilot signal component is stored. By the way, if the switch 302 is configured to select the data opposite to that of the present embodiment, the control data having the same frequency as each pilot signal but the opposite phase data is output.

When the above-mentioned calculation is completed for the odd-numbered data, the switches SW1 and SW2 are connected to the side b, the 1-bit register 202 in the precoder 105 is set to "0", and the determination circuit 106 is set. The values of the up / down counters 216 to 220 are reset to "0".

The remaining even-numbered data is calculated, but only the up-down counter is used for the even-numbered data. The reason for this will be described later.

The even-numbered data read from the register 104 is processed by the 1T precoder 105 as described above.
It is ZI converted and stored in the 24-bit register 108 via the switch SW2. 24-bit register 107,
Reference numeral 108 stores the input odd-numbered data and even-numbered data for 24 bits, that is, for 2 codewords of data.

The data read from the registers 107 and 108 is output to the synthesizing circuit 109. FIG. 5 shows the configuration of the synthesis circuit 109.

In FIG. 5, a 12-bit register 401
12-bit odd-numbered data, which is one codeword before the code that has just been input and processed, is input from the register 107, and the 12-bit register 402 also has one codeword before the code that has just been input and processed. 12-bit even-numbered data is input. Further, the 1-bit data of the code check result output from the determination circuit 106 is input to the 1-bit register 409, and the EXOR circuit 405 EXORs the check result data and the data stored in the register 402 and the switch 408. Output to.

The 1-bit data of the code check result output from the determination circuit 106 is delayed by the delay circuit 406 and output to the EXOR circuit 403. Delay circuit 40
Reference numeral 6 delays and outputs the code inspection result for one codeword in the input data. Therefore, in the EXOR circuit 403, 24 bits before the one codeword of the data currently input are input.
The code check result output for bit data is input. The EXOR circuit 403 outputs the code check result output from the delay circuit 406 and the 12-bit register 401.
EXOR with the odd-numbered 12-bit data from is taken and sequentially output to the EXOR circuit 404.

Here, the sign check result is delayed and EXORed with the odd-numbered 12-bit data of the input data, because the control data (here, 1 bit as the sign check result is used for the immediately preceding 24-bit data. Data) and subjected to interleaved NRZI modulation, even-numbered data in 25-bit data obtained by adding 1 bit of control data to the currently input 24-bit data,
That is, the influence of the control data added to the immediately preceding 24-bit data on the odd-numbered data in the 24-bit data before adding the control data has an influence, and in this embodiment, 0 is set as the initial data of NRZI in the precoder 105. This is because it is used.

Further, 1-bit control data output from the inspection circuit 110 is input to the 1-bit register 407 as described later, and the EXOR circuit 404 outputs this control data and odd-numbered data output from the EXOR circuit 403. 1
EXOR with 2 bits is taken and output to the switch 408.

The switch 408 is for the EXOR circuit 40.
Outputs 4 and 405 and 1-bit control data from the register 409 are selected and output. That is, the switch 4
08 is first connected to the c terminal and thereafter alternately connected to the a terminal and the b terminal, and outputs precode data in which 1 bit of control data is added to the 24 bit data which has just been input.

The 25-bit data output from the switch 409 is the 25-bit register 111 and the inspection circuit 110.
Is output to. FIG. 6 is a block diagram showing the configuration of the inspection circuit 110.

In FIG. 6, the 0-run detection circuit 501 counts and outputs the longest continuous number of "0" in the input 25-bit data. The 1-run detection circuit 502 counts and outputs the longest continuous number of "1" in the input 25-bit data. The alternate bit detection circuit 503 counts and outputs the maximum number of "0" and "1" arranged alternately in the input 25-bit data.

The outputs of the circuits 501 and 502 are output to the comparison operation circuit 504, and the larger data is output to the comparison operation circuit 505. The comparison operation circuit 505 detects the output of the comparison operation circuit 504 and the alternate bit. The larger output of the circuit 503 is output to the comparison circuit 506, and "1" is output when the output of the comparison operation circuit 504 is larger, and "0" is output when the output of the alternate bit detection circuit 503 is larger. Is output to the AND circuit 507.

The comparison circuit 506 outputs "1" when the value of the signal supplied from the comparison operation circuit 505 is 10 or more,
Otherwise, "0" is output.

An AND circuit 507 takes the AND of the output of the comparison operation circuit 505 and the comparison circuit 506, and the synthesis circuit 10
9 to the 1-bit register 403 and the limiting circuit 112.

When the output of the AND circuit 507 is "0", the limiting circuit 112 outputs the data held in the 25-bit register 111 to the output terminal 113 as it is, and when it is "1", the synthesizing circuit 109 for the 25-bit data is used. Only odd-numbered data including the added 1-bit control data is inverted and output to the output terminal 113. Here, such processing is performed in order to prevent a specific bit from continuing in the modulation data for a long period of time and to prevent the direct current component from being included in the modulation data as much as possible.

Further, the check circuit result is output to the 1-bit register 403 of the synthesizing circuit 109, and the check result and the odd-numbered data of the input data before adding the control data are EXORed. Is the result of interleaved NRZI modulation performed on the input 24-bit data as output data in the present embodiment, and the influence of the above-described inversion operation is an odd number in the 24-bit data input later. This is to compensate for the appearance in the data.

Here, a method of determining control data in the determination circuit of this embodiment will be described.

In FIG. 7, assuming that B is the currently input 24-bit data and A is the 24-bit data one codeword before, and the control data to be added to the data one codeword before is determined. think of.

As described above, every time the processing of the odd-numbered 12-bit data is completed, the up / down counter in the determination circuit 106 is reset and the code check circuit operates to output the control data. This means that the control data to be added to the 24-bit data one codeword before is determined when the odd-numbered data in the currently input 24-bit data is processed.

That is, in the present embodiment, in the 24-bit data before one codeword, which is the data affected when the interleaved NRZI modulation is performed by adding the control data to the 24-bit data before the one codeword. 12 bits of even-numbered data and 24 currently input
12 bits of odd-numbered data in the bit data are extracted, and the control data to be added to the 24-bit data one codeword before is determined based on these 24-bit data.

Therefore, the control data to be added to the currently input 24-bit data is not determined until the processing of the discrimination circuit 106 for the odd-numbered 12-bit data of the next 24-bit data is completed. It will be.

As described above, in this embodiment, two codewords of data that are affected by the precoding with control data added are extracted, and one system operation is performed based on these data. Since the control data is determined by the circuit, the pilot signal component can be efficiently multiplexed with the recording data without increasing the circuit scale.

Further, when the control data is determined, the pilot signal component is determined by EXORing with the signal represented by a binary rectangular wave, so that the calculation for detecting the pilot signal component is extremely simple. become.

In the above-described embodiment, the EXOR of the binary rectangular wave signal and the input data is taken, but the present invention is not limited to this.
It is also possible to determine the control data by detecting the correlation with the three-valued signal or the four-valued signal with the same configuration.

Although the control data is determined based on the data of two codewords, it may be three or more codewords.

Further, in the above-described embodiment, the case where the interleaved NRZI modulation is performed on the input data has been described. However, the present invention is not limited to this, and the input data and the data subsequent thereto are changed according to the state of the control data to be added. Any modulation may be used as long as at least a part thereof is affected by inversion or the like, and the same effect can be obtained.

[0064]

As is apparent from the above description, according to the present invention, when the control data is added to the input data to perform the predetermined modulation, the control data is used when the input data and the data subsequent thereto are modulated. Since the specific frequency component in the modulation data is detected based on the data affected by, the specific frequency component in the modulation data can be accurately and effectively detected without increasing the size of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a modulation circuit in FIG.

3 is a block diagram showing a configuration of a precoder and a determination circuit in FIG.

FIG. 4 is a block diagram showing a configuration of a component extraction circuit in FIG.

5 is a block diagram showing a configuration of a synthesis circuit in FIG.

6 is a block diagram showing a configuration of an inspection circuit in FIG.

FIG. 7 is a diagram for explaining an operation of determining control data in the example of the present invention.

FIG. 8 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 105 1T precoder 106 Judgment circuit 109 Combining circuit 110 Inspection circuit 112 Limiting circuit 221 Code inspection circuit

Claims (12)

[Claims] 1. An apparatus for adding control data to each predetermined number of input data and performing predetermined modulation, wherein a part of the predetermined number of input data following the control data is affected by the state of the control data. A modulation means for modulating the input data so that a part of the other predetermined number of data following the predetermined number of input data is affected, and the predetermined number of input data and the other predetermined number. A data processing device for detecting a specific frequency component in the modulated data based on data that is affected by a single control data in both the data. 2. The data processing apparatus according to claim 1, further comprising a determining unit that determines and outputs control data to be added to the predetermined number of input data based on the output of the detecting unit. 3. The modulation means performs interleaved NRZI modulation on 2n + 1-bit data in which 1-bit control data is added to 2n-bit input data, which is the predetermined number of data. The data processing device according to claim 1. 4. The modulation circuit performs NRZI modulation on odd-numbered and even-numbered n-bit data of the 2n-bit input data, and each n-bit output from the modulation circuit. Inversion means for inverting the sign of the data, the control data from the determination means, the n-bit data output from the modulation circuit, and the n-bit data output from the inversion means. The data processing apparatus according to claim 3, further comprising a selecting unit that outputs the data. 5. The inverting means includes a first inverting circuit for inverting the sign of the even-numbered n-bit data output from the modulating circuit using the control data from the determining means, and the 2n-bit data. Second inversion circuit that inverts the sign of the odd-numbered n-bit data output from the modulating means by using the control data added to the 2n-bit data input immediately before the input data of The data processing device according to claim 4, further comprising: 6. The detection means relates to the predetermined number of input data and a predetermined number of data subsequent to the input data, extracting means for extracting data affected by the control data, and a signal of the specific frequency. Generating means for generating a binary signal; calculating means for logically calculating the output of the extracting means and the binary signal; and a multi-valued signal relating to the signal of the specific frequency according to the output of the calculating means. The data processing apparatus according to claim 5, further comprising a correlation detection unit that detects a correlation. 7. The data processing apparatus according to claim 6, wherein the arithmetic means is an exclusive OR circuit. 8. The extraction means extracts, from the output of the modulation circuit, data that is affected by the control data in the predetermined number of input data and the other predetermined number of data. Item 7. The data processing device according to item 6. 9. The data processing apparatus according to claim 2, wherein the determining unit determines the control data so that the output data of the modulating unit contains more of the specific frequency component. 10. An inspection unit for inspecting the states of the predetermined number of input data and the control data output from the modulation unit, and the predetermined number of output units from the modulation unit based on the output of the inspection unit. Control means for changing at least a part of the input data and the control data, and controlling the modulating means so as to change at least a part of the predetermined number of data following the input data. The data processing device according to claim 1. 11. An interleaved NRZI by adding 1-bit control data to the head of 2n-bit input data.
A device for performing modulation, wherein even-numbered n-bit data in the 2n-bit input data and 2n subsequent to the 2n-bit input data
Generating means for generating the control data by using odd-numbered n-bit data in the bit data. 12. Separation means for separating the 2n-bit input data into odd-numbered n-bit data and even-numbered n-bit data, and modulation means for subjecting each n-bit data to NRZI modulation. The data processing device according to claim 11, further comprising a selection unit that selectively outputs each n-bit data output from the modulation unit and the control data generated by the generation unit.