JPH09102737A - CMOS 3-value NOT circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ternary-valent NOT CIRCUIT of a simple constitution which outputs the voltage of a high level via a CMOS circuit. SOLUTION: The NOT circuit is provided with a pMOS transistor TR P1 and an nMOS TR N1 which have their gates connected in common to an input terminal 1, and a pMOS TR P2 and an nMOS TR N2 which have their drains connected in common to an output terminal 2 and are always turned on by the comparatively large internal resistance. Then the drain of the TR P1 and the source, of the TR P2 are connected together in common, the drain of the TR N1 and the source of the TR N2 are connected together in common, the source of the TR P1 is connected to a power supply, and the source of the TR N1 is grounded respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low level voltage ( _VL ) and a medium level voltage (V) depending on the level of an input voltage.
_M ) and a three-valued NOT circuit that outputs a high level voltage (V _H ), and particularly to a CMOS three-valued NOT circuit that uses a CMOS circuit and realizes this with a simple configuration.

[0002]

2. Description of the Related Art A conventional three-valued NOT circuit is shown in FIG. In this three-value NOT circuit, the input voltage Vin is the threshold voltage V
An inverter INV1 that outputs a low level voltage “L” when _T1 is exceeded, and an input voltage Vin is a threshold voltage V _T2 (> V
Inverter INV that outputs "L" when _T1 ) is exceeded
2, input the output voltage of both inverters INV1, 2 2
Input gates (logical product) G1 to G3 and its gate G1
Output voltage of ~G3 are each turned to the input side of the voltage V _H when the high level voltage "H", V _M, outputs the V _L voltage Vou
The analog switches S1 to S3 output as t.

First, when the input voltage Vin is 0≤Vin <V _T1
When, the output voltage of the inverters INV1, 2 is "H"
Therefore, the output voltage of the gate G1 is "H", and the output voltages of the gates G2 and G3 are "L".
Only 1 is turned on, and the voltage V _H is output as the output voltage Vout.

Next, when V _T1 ≤Vin <V _T2 , the output voltage of the inverter INV1 is "L" and the output voltage of INV2 is "H". Therefore, the gates G1 and G3 are off and G
2 is turned on, only the switch S2 is turned on, and the voltage V
_M outputs as the output voltage Vout.

Next, when V _T2 ≤Vin, the output voltages of the inverters INV1 and INV2 are both "L", so that the output voltages of the gates G1 and G2 are "L" and the output voltage of G3 is "H". Then, only the switch S3 is turned on, and the voltage V _L is output as the output voltage Vout.

Therefore, the input / output characteristic of this three-valued NOT circuit becomes a step-shaped characteristic curve as shown in FIG.
Depending on the level of the input voltage Vin, the level of the output voltage Vout is the voltage V _H, V _M, is converted into ternary V _L. FIG. 9 is an explanatory diagram of the truth value of the output of each part of the above circuit.

[0007]

However, in the circuit configuration as described above, it is necessary to configure an input circuit composed of inverters INV1 and INV2 for performing three-value detection and conversion into two-values, and gates G1 to G3. It is necessary to configure an intermediate circuit that performs a binary logical operation with
It is necessary to configure an output circuit composed of analog switches S1 to S3 for converting into values. Therefore, a large number of elements are required to form a circuit, which is not suitable for integration.

An object of the present invention is to solve the above-mentioned problems,
Three-valued NO realized with a simple configuration using a CMOS circuit
It is to provide a T circuit.

[0009]

To this end, the first invention comprises a pMOS transistor and an nMOS transistor whose gates are commonly connected to an input terminal.
The drain of the transistor is connected to the output terminal via the first resistance element, the drain of the nMOS transistor is connected to the output terminal via the second resistance element, and the source of the pMOS transistor is connected to the first power supply. A CM characterized in that it is connected to a terminal and the source of the nMOS transistor is connected to a second power supply terminal.
It is configured as an OS three-value NOT circuit.

[0010] The second invention is the above-mentioned first invention, wherein:
The resistance values of the first resistance element and the second resistance element are substantially the same, and are several ten times to several times the internal resistance when the pMOS transistor is on and the internal resistance when the nMOS transistor is on. The CMOS three-value NOT circuit is characterized in that the value is set to 100 times.

A third invention is characterized in that, in the first or second invention, each of the first resistance element and the second resistance element is constituted by a MOS transistor which is always on. It is configured as a CMOS three-value NOT circuit.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 shows a first embodiment C of the present invention.
It is a circuit diagram of a MOS three-value NOT circuit. In this circuit, a pMOSFET (hereinafter, MOSFET is referred to as a MOS transistor) P having a gate commonly connected to an input terminal 1 is provided.
1 and an nMOS transistor N1, a drain connected to the output terminal 2, a source connected to the drain of the MOS transistor P1, and a source connected to the drain of the MOS transistor N1, and a pMOS transistor P2 and n.
It is composed of a MOS transistor N2. This pM
The gate of the OS transistor P2 is grounded, and the source of the pMOS transistor P1 and the gate of the nMOS transistor N2 are connected to the power supply terminal 3. The source of the nMOS transistor N1 is grounded.

Therefore, in this circuit, the MOS transistors P2 and N2 are always on, and the drain and source thereof function as a fixed resistor. Also, MO
The S transistors P1 and N1 function as a CMOS inverter circuit that changes the internal resistance according to the level of the voltage applied to the input terminal 1.

In this circuit, the MOS transistor P2,
The internal resistance when N2 is turned on is the MOS transistor P1,
Compared with the internal resistance when N1 is on, it is several ten times to several hundred.
The W / L (size) is set so that it will be almost the same value as the doubled value. Thus, with respect to the input voltage Vin applied to the input terminal 1, an output voltage Vout appearing at the output terminal 2, the input voltage as shown in FIG. 2 Vin = V _T1,
It functions as a ternary NOT circuit that changes with V _T2 as a change point and outputs the voltages V _H , V _M , and V _L.

First, in FIG. 2, the input voltage Vin
Area A (0 ≦ Vin <Vtn) (where Vtn is the threshold voltage of the MOS transistor N1)
, The MOS transistor P1 is turned on and the MOS
Since the transistor N1 is cut off, its equivalent circuit becomes a circuit as shown in FIG. 3A, and the output terminal 2 is completely floating from the ground.

In this range, since the voltage applied between the source and drain of the MOS transistor P1 is small and the MOS transistor P1 operates in the linear region, its internal resistance Rp1 changes according to the input voltage Vin, but the output terminal 2 floats from the ground. Since it is in the state, the output voltage Vout becomes substantially equal to the voltage V _H (= Vdd). Rp2 is an internal resistance of the MOS transistor P2.

Next, in the range of the region B (Vtn≤Vin <Va) where the input voltage Vin is near the voltage V _T1 , the MOS transistor P1 still operates in the linear region (internal resistance R
p1), the MOS transistor N1 has a large voltage applied between its drain and source and operates in the saturation region.
Therefore, this MOS transistor N1 functions as a current source In1 that is not affected by the drain-source voltage,
The equivalent circuit is as shown in FIG. Rn2 is M
The internal resistance of the OS transistor N2.

In this range, as the input voltage Vin increases, the internal resistance Rp1 of the MOS transistor P1 increases and the current of the current source In1 of the MOS transistor N1 also increases, so that the input voltage Vin slightly increases. Output voltage Vout is from V _H to V _M (= Vdd / 2)
Greatly decreases.

Next, if the input voltage Vin is in the region C (Va≤V
In the range of in <Vb), the MOS transistors P1 and N
Both 1 operate in the saturation region. Therefore, this MOS transistor P1 also functions as a current source Ip1 that is not affected by the voltage between the source and the drain, and becomes an equivalent circuit as shown in FIG.

In this range, both transistors P1,
Even if the currents of the current sources Ip1 and In1 of N1 change differentially according to the input voltage Vin, the MOS transistor P2,
The output voltage Vout is not affected by the relatively large internal resistances Rp2 and Rn2 of N2, and becomes substantially constant V _M.

Next, a region D where the input voltage Vin is near the voltage V _T2 (Vb ≦ Vin <Vtp) (where Vtp is MO
In the range of (threshold voltage of S transistor P1), MO
The S transistor P1 still operates in the saturation region, while the MOS transistor N1 operates in the linear region. Therefore, this MOS transistor N1 has an internal resistance Rn1.
And becomes an equivalent circuit as shown in FIG.

In this range, as the input voltage Vin increases, the internal resistance Rn1 of the MOS transistor N1 decreases and the current of the current source Ip1 of the MOS transistor P1 decreases, so that the input voltage Vin slightly increases. The output voltage Vout greatly drops from V _M to V _L (= 0).

Next, in the range of the region E (Vtp≤Vin) where the level of the input voltage Vin is high, the MOS transistor P1 is cut off, so that its equivalent circuit becomes a circuit as shown in FIG. The output terminal 2 is completely separated from the power supply terminal 3.

In this range, since the MOS transistor N1 operates in the linear region, its internal resistance Rn1 changes according to the input voltage Vin, but since the output terminal 2 is separated from the power supply terminal 3, the output voltage is Vout becomes substantially equal to the voltage V _L (= 0).

In the circuit of FIG. 1 described above, the input voltages V _T1 and V _{T at which the} output voltage Vout in FIG. 2 greatly changes.
_T2 and the voltages Va and Vb in the vicinity thereof are determined by the threshold voltage Vtp of the MOS transistor P1, the threshold voltage Vtn of the MOS transistor N1, and the internal resistances Rp2, Rn2 of the MOS transistors P2, N2. A desired input / output characteristic can be obtained by appropriately setting.

[Second Embodiment] FIG. 4 is a diagram showing a CMOS three-value NOT circuit according to a second embodiment. Here, the nMOS transistor N2 in FIG.
The MOS transistor P3 is replaced with the source thereof, the source thereof is connected to the output terminal 2, the gate thereof is connected to the ground, and the drain thereof is connected to the drain of the MOS transistor N1. Therefore, also in this circuit, both the transistors P2 and P3 are always turned on and function as a fixed resistance, so that the resistance value of the transistors P1 and P3 is the same as that described above.
By setting the internal resistance when N1 is on to several ten times to several hundred times and substantially the same as each other, the same operation as the operation described in the first embodiment is performed.

[Third Embodiment] FIG. 5 is a diagram showing a CMOS three-value NOT circuit according to a third embodiment. Here, the pMOS transistor P2 in FIG.
The source of the MOS transistor N3 is connected to the output terminal 2, the drain thereof is connected to the drain of the transistor P1, and the gate thereof is connected to the high voltage Vdd.
Is applied. Therefore, even in this circuit,
Since both the transistors N2 and N3 are always turned on and function as a fixed resistor, the resistance value thereof is several ten times to several hundred times the internal resistance when the transistors P1 and N1 are turned on in the same manner as described above.
The same operation as the operation described in the first embodiment is performed by setting the doubled value and substantially the same value.

[Fourth Embodiment] FIG. 6 is a diagram showing a CMOS three-value NOT circuit according to a fourth embodiment. Here, a resistor Ro is connected between the drains of the CMOS transistors P1 and N1, and an arbitrary portion of the resistor Ro, for example, a substantially middle portion is connected to the output terminal 2 so that the resistor Ra is MO.
The S-transistor P1 side is provided, and the resistor Rb is provided on the transistor N1 side. Also in this circuit, the resistance values of the resistors Ra and Rb are the same as those of the transistor P.
The same operation as the operation described in the first embodiment is performed by setting the internal resistances of 1 and N1 to be several tens to several hundreds times the on-state internal resistance and are almost the same as each other. Become.

[0029]

As described above, according to the CMOS three-valued NOT circuit of the present invention, the circuit can be realized by using at most four elements, and the number of elements can be significantly reduced as compared with the conventional circuit, and it can be integrated. It has the advantage of being very suitable.

[Brief description of the drawings]

FIG. 1 is a CMOS tri-level N according to a first embodiment of the present invention.
It is a circuit diagram of an OT circuit.

FIG. 2 is an input / output characteristic diagram of the circuit of FIG.

FIG. 3 is a circuit diagram showing equivalent circuits (A) to (E) according to the level of the input voltage of the circuit of FIG.

FIG. 4 is a CMOS tri-level N according to the second embodiment of the present invention.
It is a circuit diagram of an OT circuit.

FIG. 5 is a CMOS tri-level N according to the third embodiment of the present invention.
It is a circuit diagram of an OT circuit.

FIG. 6 is a CMOS tri-level N according to the fourth embodiment of the present invention.
It is a circuit diagram of an OT circuit.

FIG. 7 is a circuit diagram of a conventional three-value NOT circuit.

8 is an input / output characteristic diagram of the circuit in FIG.

9 is an explanatory diagram showing a truth value of the circuit of FIG.

[Explanation of symbols]

 1: Input terminal, 2: Output terminal, 3: Power supply terminal.

Claims (3)

[Claims] 1. A pMOS having a gate commonly connected to an input terminal.
A transistor and an nMOS transistor, wherein the drain of the pMOS transistor is connected to the output terminal via the first resistance element, and the drain of the nMOS transistor is connected to the output terminal via the second resistance element, A CMOS three-valued NOT circuit characterized in that the source of the pMOS transistor is connected to a first power supply terminal and the source of the nMOS transistor is connected to a second power supply terminal. 2. The resistance values of the first resistance element and the second resistance element are substantially the same, and with respect to the internal resistance when the pMOS transistor is on and the internal resistance when the nMOS transistor is on. The CMOS three-value NOT circuit according to claim 1, wherein the value is set to be several tens to several hundreds of times. 3. The CMO according to claim 1, wherein each of the first resistance element and the second resistance element is composed of a MOS transistor which is always on.
S3 value NOT circuit.