JPH09116014A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: When forming a plurality of contact holes having different depths at the same time, it is possible to prevent the conductive layer at the bottom of the shallow contact hole from penetrating. A silicon nitride film 37 is formed above a polycrystalline silicon film 34 that should reach a shallow contact hole 44, and interlayer insulating films 33 and 36 made of a silicon oxide film are formed.
Etching is performed under the condition that the etching rate of the silicon nitride film 37 is slower than that of the BPSG film 42. Therefore, the time required to form the two contact holes 44 and 45 becomes substantially the same, and the penetration of the polycrystalline silicon film 34 does not occur.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a plurality of contact holes each having at least one of depth and diameter different from each other.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device, a plurality of contact holes having at least one of depth and diameter different from each other may be formed. 7 to 8 show a contact hole for connecting an impurity diffusion layer detected on the surface of a silicon substrate and a bit line, a wiring formed of a conductive layer in the same layer as the bit line, and a cell plate. A conventional example of a method of manufacturing a DRAM having a contact hole for connection at an end of a cell array is shown.

In this conventional example, first, as shown in FIG. 7A, an impurity diffusion layer 12 is formed on a silicon substrate 11, and an interlayer insulating film 13 made of a silicon oxide film is further formed on the silicon substrate 11. After the formation, the polycrystalline silicon film 14 having a film thickness of about 150 nm is formed by the low pressure CVD method on the interlayer insulating film 1.
3 is deposited on top.

Next, as shown in FIG.
_{By the} pre-deposition method in which phosphorus is thermally diffused from this vapor by exposing it to the vapor of ₃ , phosphorus of 6 × 10 ²⁰ (atoms / cm 2
Introduced into the polycrystalline silicon film 14 at a concentration of about ³ ),
The electrical resistance of this polycrystalline silicon film 14 is reduced.

Next, as shown in FIG. 7C, a resist 15 having a cell plate pattern is formed on the polycrystalline silicon film 14 by ordinary lithography.

Next, as shown in FIG. 7 (d), a microwave etching power 800 W, a high frequency power 20 W, and a pressure 3 m are used by using a dry etching apparatus using the ECR discharge method.
The polycrystalline silicon film 14 is etched using the resist 15 as a mask under the plasma generation conditions of Torr and gas Cl ₂ / O ₂ = 36/4 sccm. Then resist 1
5 is removed, an interlayer insulating film 16 made of a silicon oxide film having a film thickness of about 100 nm and a low impurity concentration is deposited, and subsequently, a film having a film thickness of 5 is formed by using O ₃ + TEOS as a raw material.
B ₂ O ₃ / P ₂ O ₅ = 13/14 wt% at about 00 nm
The BPSG film 17 is deposited by the atmospheric pressure CVD method. Then, the BPSG film 17 is reflowed at a temperature of 900 ° C. to flatten the surface of the BPSG film 17.

Next, as shown in FIG. 8A, in order to connect the wiring formed of the same conductive layer as the bit line and the polycrystalline silicon film 14 serving as the cell plate at the end of the memory cell array. Of the contact hole, that is, the resist 21 having a contact hole pattern with a relatively shallow depth,
It is formed on the SG film 17. Then, a contact hole 22 reaching the polycrystalline silicon film 14 is formed by normal dry etching using the resist 21 as a mask.

Next, as shown in FIG. 8B, after removing the resist 21, this time, the contact hole for connecting the impurity diffusion layer 12 in the memory cell and the bit line, that is, the depth is reduced. A resist 23 having a relatively deep contact hole pattern is formed on the BPSG film 17. Then, a contact hole 24 reaching the impurity diffusion layer 12 is formed by normal dry etching using the resist 23 as a mask, and further, through known steps, the DRAM is completed.

[0009]

By the way, as the miniaturization of semiconductor elements progresses, the diameter of the contact hole is reduced, but in order not to lower the breakdown voltage between wirings,
There is a limit in reducing the thickness of the interlayer insulating film. Therefore, with the progress of miniaturization, the aspect ratio of the contact hole formed in the interlayer insulating film is increasing.

On the other hand, in a semiconductor device such as a DRAM, a memory cell having a three-dimensional structure such as a stacked capacitance (stack) type is used in order to prevent the memory cell capacity from being reduced even if the miniaturization of elements progresses to increase the capacity. Structures have been adopted.
Therefore, the interlayer insulating film 13 and the BP depending on the position on the wafer
The SG film 17 has a large variation in thickness, and the contact hole 2
There may be a difference in depth of 3 to 4 between the shallowest one of the two and the deepest one of the contact holes 24.

As a result, if the contact holes 22 and 24 are
Is formed at the same time, by the time the contact hole 24 reaches the impurity diffusion layer 12, over-etching of 400 to 500% is applied to the polycrystalline silicon film 14 which the contact hole 22 has already reached. Therefore, a very high etching selection ratio of the interlayer insulating film 13 and the BPSG film 17 with respect to the polycrystalline silicon film 14 is required.

However, in order to increase the above-mentioned etching selection ratio, if the pressure and gas ratio during dry etching are optimized and the temperature of the lower electrode in a parallel plate discharge type dry etching apparatus is lowered, in particular, the aspect ratio If the ratio is high, the contact holes 22, 24 taper toward the bottom and the contact holes 22, 2
Deterioration of the shape occurs that the side surface of 4 is curved in an arch.

Therefore, the bottom areas of the contact holes 22 and 24 are reduced, and the coverage of wirings such as bit lines on the side surfaces of the contact holes 22 and 24 is reduced. As a result, the contact resistance is increased and the DRAM is Operation speed will decrease. On the contrary, if it is attempted to prevent the deterioration of the shapes of the contact holes 22 and 24, the etching selection ratio of the interlayer insulating film 13 and the BPSG film 17 to the polycrystalline silicon film 14 becomes low, and the etching amount of the polycrystalline silicon film 14 becomes 50%.
It will reach 0-1500Å.

As a result, as shown in FIG. 9, the contact hole 22 penetrates the polycrystalline silicon film 14, and the polycrystalline silicon film 14 and the polycrystalline silicon film 25 below the short circuit are short-circuited, or the contact is temporarily made. Even if the hole 22 does not penetrate the polycrystalline silicon film 14, the film thickness margin of the polycrystalline silicon film 14 is reduced when the portion (SiC layer) into which carbon is injected by etching is removed by light etching. , DR
It had reduced the reliability of AM.

For this reason, when a plurality of contact holes having different depths are formed, resists 21 and 23 having different patterns are formed by two or more lithography processes as in the above-mentioned conventional example. Form and 2
Contact holes 22 and 2 by etching process more than once
4 are formed separately. However, the contact hole 22,
Since the lithography process and the etching process are performed twice or more for forming 24, the total number of processes is large and it is difficult to manufacture the DRAM at low cost.

If resists 21 and 23 having different patterns are formed by two or more lithography processes,
The yield is reduced due to misalignment between the contact holes 22 and 24, which also makes it difficult to manufacture the DRAM at low cost.

The above-mentioned conventional example is the contact hole 2.
This is the case where the depths of 2 and 24 are different, but if the contact holes have the same depth but the diameters are different, if these contact holes are formed at the same time, the diameter is small due to the microloading effect. Until the contact hole reaches the polycrystalline silicon film or the like, overetching is similarly applied to the polycrystalline silicon film which has already reached the contact hole having a large diameter.

Therefore, an object of the present invention is to reach a contact hole having a shallow depth and a contact hole having a large diameter when manufacturing a semiconductor device having a plurality of contact holes each having at least one of depth and diameter different from each other. While reducing the amount of etching of the conductive layer and preventing the deterioration of the shape of the contact holes, the total number of processes can be reduced and the decrease in yield due to misalignment of the contact holes can be suppressed, resulting in high reliability. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having a high operating speed at low cost.

[0019]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is directed to a first contact hole and a first contact hole having a depth relatively shallower than that of the first contact hole. In a method of manufacturing a semiconductor device having two contact holes, a film thickness at a portion where the first contact hole is formed is larger than a film thickness at a portion where the second contact hole is formed. And a film made of a material different from that of the first film, and the film thickness at the portion where the second contact hole is formed is the film at the portion where the first contact hole is formed. Forming a second film having a thickness larger than the thickness; and using a mask having an opening pattern of the first contact holes and the second contact holes, the second film having a thickness larger than that of the first film. Conditions for slow etching rate Etched, and a step of simultaneously forming the first contact hole and the second contact hole in the first film and the second film.

In one aspect of the present invention, the second film is formed in a portion where the second contact hole is formed,
The first contact hole is not formed in the portion where it is formed.

In one aspect of the present invention, the first membrane is a composite membrane composed of a plurality of membranes.

In another aspect, in the method of manufacturing a semiconductor device of the present invention, the first contact hole reaching the lower conductive layer and the first contact hole reaching the upper conductive layer and having a depth relatively larger than that of the first contact hole. In a method of manufacturing a semiconductor device having a shallow second contact hole, a first insulating film and a second insulating film made of a material different from the first insulating film are sequentially formed on the lower conductive layer. A step, a step of patterning the upper conductive layer on the second insulating film, a step of forming a third insulating film over the entire surface, a step of forming the first contact hole and the second contact Using the mask having the hole opening pattern, the second insulating film in the first contact hole is completely removed under the condition that the etching rate of the upper conductive layer is slower than that of the third insulating film. Etch A step of performing, the first contact hole and a mask having an opening pattern of the second contact hole, the first insulating film than said second
Under the condition that the etching rate of the insulating film of
Etching is performed until all the first insulating film in the contact hole is removed and the lower conductive layer is exposed.

In one aspect of the present invention, the upper conductive layer is a polycrystalline silicon film, the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. .

In one aspect of the present invention, in the step of performing etching until all of the second insulating film in the first contact hole is removed, etching is performed using a gas containing no carbon monoxide. In the step of performing etching until the lower conductive layer is exposed, etching is performed using a gas containing carbon monoxide.

In one aspect of the present invention, it is detected that all of the second insulating film in the first contact hole has been removed by the attenuation of the emission intensity at the wavelength of 336 nm in plasma.

In one aspect of the present invention, the second contact hole is a contact hole having a relatively larger diameter than the first contact hole.

In the method of manufacturing a semiconductor device of the present invention, since a plurality of contact holes having different depths are simultaneously formed, the lithography step and the etching step for forming the plurality of contact holes are performed once. Good.

Moreover, according to the present invention, since the first and second films having different etching rates are formed by adjusting the film thickness, the etching time required to form the shallow contact hole is deep. It is longer than the etching time required to form the contact hole. Therefore, even if the etching selection ratio of the interlayer insulating film to the conductive layer at the bottom of the contact hole is not increased, the time for forming the plurality of contact holes having different depths (or the plurality of contact holes having different diameters) is formed. Can be equal to each other). Therefore, the etching amount of the conductive layer at the bottom of the shallow contact hole (or the contact hole having a large diameter) can be reduced,
It is also possible to increase the film thickness margin of the conductive layer when the portion into which carbon is injected by etching is removed by light etching.

Further, in the present invention according to another aspect, since the etching is first performed under the condition that the etching rate of the upper conductive layer is slower than that of the third insulating film, the second insulating film is the second insulating film.
Is removed earlier in the first contact hole than in the first contact hole. Then, after the second insulating film in the first contact hole is completely removed, etching is performed under the condition that the etching rate of the second insulating film is slower than that of the first insulating film. Therefore, even if the second contact hole penetrates the upper conductive layer, the second insulating film in the second contact hole functions as an etching stopper, so that another conductive layer is formed under the upper conductive layer. If so, the second contact hole hardly reaches the conductive layer.

The wavelength in the plasma is 336 nm.
When the removal of the second insulating film is detected by the attenuation of the light emission intensity of, it is possible to accurately detect the time when all the second insulating film such as the silicon nitride film is removed. Can be done accurately.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 2 are sectional views showing the first embodiment in which the present invention is applied to the manufacture of a DRAM in the order of steps. This DRAM has a contact hole for connecting one side of an impurity diffusion layer, which is a source / drain of a MOS transistor constituting a memory cell, to a bit line, and a wiring formed of a conductive layer in the same layer as the bit line. It has a contact hole for connecting the cell plate of the memory cell capacitor at the end of the memory cell array.

To manufacture the DRAM of this embodiment, first, as shown in FIG. 1A, a pair of impurities, which are the source and drain of a MOS transistor forming a DRAM memory cell, are formed on the surface of a silicon substrate 31. The diffusion layer 32 is formed. In the figure, only one of the pair of impurity diffusion layers 32 is shown, and the other impurity diffusion layer and the gate electrode of the MOS transistor are not shown. Then, after forming an interlayer insulating film 33 made of a silicon oxide film and having a film thickness of about 500 nm to 1000 nm on the silicon substrate 31,
The polycrystalline silicon film 34 having a thickness of about 150 nm is decompressed by CV.
It is deposited on the interlayer insulating film 33 by the D method. The polycrystalline silicon film 34 is formed on the impurity diffusion layer 3 in a region (not shown).
It is assumed that it is connected to the other side of No. 4 via a contact hole (not shown).

Next, as shown in FIG. 1 (b), POCl
_{By the} pre-deposition method of exposing phosphorus to vapor of ₃ and thermally diffusing phosphorus from the vapor, phosphorus of 12 × 10 ²⁰ (atoms /
It is introduced into the polycrystalline silicon film 34 at a concentration of about cm ³ ) to reduce the electric resistance of the polycrystalline silicon film 34.

Next, as shown in FIG. 1C, a resist (photoresist) 35 having a cell plate-shaped covering pattern is formed on the polycrystalline silicon film 34 by ordinary photolithography.

Next, as shown in FIG. 1 (d), a microwave etching power 800 W, a high frequency power 20 W, and a pressure 3 m were used by using a dry etching apparatus using the ECR discharge method.
The polycrystalline silicon film 34 is etched into a cell plate shape using the resist 35 as a mask under the plasma generation conditions of Torr and gas Cl ₂ / O ₂ = 36/4 sccm.

Next, as shown in FIG. 2A, after removing the resist 35, an interlayer insulating film 36 made of a silicon oxide film having a film thickness of about 100 nm and having a low impurity concentration is deposited, and subsequently a film thickness of 100 nm is formed. Silicon nitride film 3
7 is deposited.

Next, as shown in FIG. 2B, in order to connect the wiring formed of the conductive layer of the same layer as the bit line and the polycrystalline silicon film 34 which is the cell plate at the end portion of the memory cell array. Contact hole, that is, 0.7 × 0 on each side of the silicon nitride film 37 where a relatively shallow depth is to be formed, which is 0.2 μm larger on each side than the contact hole diameter of 0.5 μm. A resist 41 having a square pattern of 0.7 μm ² is formed.

Then, using a parallel plate discharge type dry etching apparatus, high frequency power 100 W and pressure 5
00 mTorr, gas SF ₆ / He = 30/100 sc
Only the silicon nitride film 37 is etched using the resist 41 as a mask under the plasma generation condition of cm.

Next, as shown in FIG. 2C, after removing the resist 41, B ₂ O ₃ / P ₂ O ₅ = 500 nm in thickness is formed as an interlayer insulating film made of a silicon oxide film.
A 13/14 wt% BPSG film 42 is deposited on the entire surface by the CVD method. Then, the BPSG film 42 is reflowed at a temperature of 900 ° C., the surface of the BPSG film 42 is flattened, and the workability of bit lines and other wirings to be formed later is improved.

After that, the wiring formed of the same conductive layer as the bit line and the polycrystalline silicon film 34 as the cell plate are formed.
And a contact hole for connecting at the end of the memory cell array, that is, a contact hole having a relatively shallow depth (second contact hole), a contact hole for connecting the impurity diffusion layer 32 and the bit line, That is, a resist 43 having both opening patterns of a contact hole (first contact hole) having a relatively deep depth is formed on the BPSG film 42 by ordinary lithography.

Next, as shown in FIG. 2D, a parallel plate discharge type dry etching apparatus is used to form a vertical shape even in a contact hole having a deep and high aspect ratio like the first contact hole. Conditions that can be processed, for example, high frequency power 750 W, pressure 500 mTorr, gas A
Contact holes 44 and 45 are formed by etching using the resist 43 as a mask under the plasma generation condition of r / CF ₄ / CHF ₃ = 800/60/60 sccm.

By the way, under the above etching conditions for forming the contact holes 44 and 45, the etching rates of the interlayer insulating films 33 and 36 made of silicon oxide films and the BPSG film 42 are 1 μm / min, and the silicon nitride film 3 is formed.
7 has an etching rate of 0.2 μm / min.

Therefore, considering the ratio of these etching rates, the contact holes 44, 45 having the same diameter as each other.
Then, if the silicon nitride film 37 having a film thickness of ⅕ of the difference in depth is formed, the formation times of the contact holes 44 and 45 become equal to each other. Then, the silicon nitride film 37
The contact hole 4 has a thickness of about 100 nm.
Even if there is a difference of about 500 nm between the depths of 4 and 45, the formation times of the contact holes 44 and 45 are equal to each other.

After that, the resist 43 is removed, and further,
This DRAM is completed through conventionally known processes such as forming wirings such as bit lines in the contact holes 44 and 45.

In this embodiment, instead of the silicon nitride film 37, a film made of a material different from the silicon oxide film, for example, a conductive film such as a tungsten silicide film or a polycrystalline silicon film can be used. By using a film made of a material different from that of the silicon oxide film, it is possible to set a condition that the etching rate of the film is slower than that of the silicon oxide film.

Further, in this embodiment, the contact hole 44
The silicon nitride film 37 is formed in the portion where the contact hole 45 is formed, and the silicon nitride film 37 is formed in the portion where the contact hole 45 is formed.
Did not form. However, the silicon nitride film 37 may be formed also in the portion where the contact hole 45 is formed. In this case, the film thickness of the silicon nitride film 37 in the portion where the contact hole 44 is formed may be made larger. When the silicon nitride film 37 is continuously formed in the portion where the contact hole 44 is formed and the portion where the contact hole 45 is formed, in order to prevent a short circuit between wirings, the silicon nitride film 37 is formed. An insulating film must be formed.

As described above, according to the present embodiment, since the lithography process and the etching process for forming the plurality of contact holes 44 and 45 having different depths may be performed once, the total number of processes is small. I'm sorry. Therefore,
Since it is possible to suppress a decrease in yield due to misalignment between the contact holes 44 and 45 caused by performing the lithography process a plurality of times, the DRAM can be manufactured at low cost.

Moreover, since the etching amount of the polycrystalline silicon film 34 at the bottom of the shallow contact hole 44 can be reduced, the contact hole 44 penetrates through the polycrystalline silicon film 34 and the polycrystalline silicon film 34. It is possible to prevent an electrical short circuit between the conductive layer and the conductive layer therebelow. Also,
Since almost no over-etching of the polycrystalline silicon film 34 needs to be performed, a film thickness margin of the polycrystalline silicon film 34 when removing the portion into which carbon has been injected by the etching for forming the contact hole 44 by light etching is provided. It can also be expanded. Therefore, a highly reliable DRAM
Can be obtained.

Further, the etching amount of the polycrystalline silicon film 34 at the bottom of the shallow contact hole 44 is reduced without increasing the etching selection ratio of the interlayer insulating films 33 and 36 and the BPSG film 42 with respect to the polycrystalline silicon film 34. Therefore, the deterioration of the shape of the contact hole 44 can be prevented, and the contact resistance can be prevented from increasing, so that a DRAM having a high operation speed can be obtained.

Next, a second embodiment in which the present invention is applied to the manufacture of DRAM will be described with reference to FIGS.

To manufacture the DRAM of the second embodiment, first, as shown in FIG. 3A, the silicon substrate 5 is used.
1, an impurity diffusion layer 52 is formed, and an interlayer insulating film 53 made of a silicon oxide film is further formed on the silicon substrate 51. Then, a polycrystalline silicon film 54 having a film thickness of about 150 nm is formed by the low pressure CVD method on the interlayer insulating film 53. Deposit on top.

Next, as shown in FIG. 3B, POCl
_{By the} pre-deposition method of exposing phosphorus to vapor of ₃ and thermally diffusing phosphorus from the vapor, phosphorus of 12 × 10 ²⁰ (atoms /
It is introduced into the polycrystalline silicon film 34 at a concentration of about cm ³ ) to reduce the electric resistance of the polycrystalline silicon film 34.

Next, as shown in FIG. 3C, a film thickness of 20
A silicon nitride film 55 having a thickness of about 0 nm is deposited on the entire surface of the polycrystalline silicon film 54 by a low pressure CVD method, and then a resist 56 having a cell plate-shaped covering pattern is formed on the insulating film 55 by ordinary lithography.
Then, the silicon nitride film 55 and the polycrystalline silicon film 54 are etched in two steps using the resist 56 as a mask by using a dry etching apparatus using the ECR discharge method.

At this time, in order to etch the silicon nitride film 55, microwave power 800 W, high frequency power 20 W, pressure 3 mTorr, gas CF ₄ = 40 scc.
m plasma generation conditions are used. Further, in order to etch the polycrystalline silicon film 54, the microwave power 80
0W, high frequency power 20W, pressure 3mTorr, gas C
A plasma generation condition of l ₂ / O ₂ = 36/4 sccm is used.

Next, as shown in FIG. 4A, after removing the resist 56, an interlayer insulating film 57 made of a silicon oxide film having a film thickness of about 100 nm and a low impurity concentration is deposited, and subsequently, the silicon oxide film is formed. As an interlayer insulating film made of B ₂ O ₃ / P ₂ O ₅ = 13 /
A 14% by weight BPSG film 61 is deposited by the CVD method. Then, the BPSG film 61 is reflowed at a temperature of 900 ° C., the surface of the BPSG film 61 is flattened, and the workability of bit lines and other wirings to be formed later is improved.

Next, as shown in FIG. 4B, in order to connect the wiring formed of the same conductive layer as the bit line and the polycrystalline silicon film 54, which is the cell plate, at the end of the memory cell array. Contact hole, that is, a contact hole having a relatively shallow depth (second contact hole), and a contact hole for connecting the impurity diffusion layer 52 and the bit line, that is, a relatively deep contact hole (first contact hole). Resist 62 having both opening patterns (contact holes)
Are formed on the BPSG film 61 by ordinary lithography.

Next, as shown in FIG. 4C, a parallel plate discharge type dry etching apparatus is used to form a vertical shape even in a contact hole having a deep and high aspect ratio like the first contact hole. Conditions that can be processed, for example, high frequency power 750 W, pressure 500 mTorr, gas Ar / CF ₄ / CHF ₃ = 800/60/60 sccm
Under the plasma generation conditions, the resist 62 is used as a mask for etching to form the contact holes 63 and 64.

By the way, under the above-described etching conditions for forming the contact holes 63 and 64, the etching rates of the interlayer insulating films 53 and 57 made of silicon oxide film and the BPSG film 61 are 0.5 μm / min, and the silicon nitriding is performed. The etching rate of the film 55 is 0.2 μm / min.

Therefore, considering the ratio of these etching rates, the contact holes 63, 64 having the same diameter are provided.
Then, if the silicon nitride film 55 having a film thickness of 2/5 of the depth difference is formed, the formation times of the contact holes 63 and 64 become equal to each other. Then, the silicon nitride film 55
The contact hole 6 has a thickness of about 200 nm.
Even if the depths of 3 and 64 differ by about 500 nm, the formation times of the contact holes 63 and 64 are equal to each other.

After that, the resist 62 is removed, and further,
This DRAM is completed through conventionally known processes such as forming wirings such as bit lines in the contact holes 44 and 45.

In the first and second embodiments described above,
Shallow contact holes 44, 63 and deep contact holes 45,
No. 64 and two contact holes with a depth of 64 are formed, but contact holes with three or more kinds of depth are formed, and as the depth of the contact holes becomes shallower, silicon nitride formed above the contact holes is formed. The film thickness may be increased.

Next, regarding the third embodiment of the present invention,
This will be described with reference to FIGS.

To manufacture the semiconductor device according to the third embodiment, first, as shown in FIG. 5A, a silicon substrate 71 is used.
After the impurity diffusion layer 72 is formed on the surface of the substrate, the film thickness of 0.
A silicon oxide film 73 of about 2 to 1.2 μm is deposited on the entire surface of the silicon substrate 71. Then, a polycrystalline silicon film 74 having a film thickness of about 100 to 300 nm is patterned on the silicon oxide film 73, and then a silicon nitride film 75 having a film thickness of about 20 to 200 nm is deposited on the entire surface.

After that, a film thickness of 10 is formed on the silicon nitride film 75.
After patterning the polycrystalline silicon film 76 having a thickness of about 0 to 300 nm, a silicon oxide film 77 having a thickness of about 0.2 to 1.2 μm is deposited on the entire surface. At this time, the polycrystalline silicon film 76 is formed so as to partially overlap the polycrystalline silicon film 74. Thereafter, a resist 81 having a film thickness of about 1.0 to 2.0 μm and having a contact hole opening pattern to reach the polycrystalline silicon film 76 and the impurity diffusion layer 72 is formed on the silicon oxide film 77.

Next, as shown in FIG. 5B, using the resist 81 as a mask, the contact holes 82 and 83 to reach the polycrystalline silicon film 76 and the impurity diffusion layer 72.
The etching for forming the film is started.

This etching consists of two steps. In the first step until the silicon nitride film 75 in the contact hole 83 is completely removed, the high frequency power is 600 to 1000.
W, pressure 200 to 500 mTorr, gas CHF ₃ / C
_{F 4 / Ar = 5~20 / 5~20} / 50~300scc
Etching is performed under the condition of m. At this time, the etching selection ratio of the silicon oxide film 77 to the polycrystalline silicon film 76 is about 5 to 20, and the etching selection ratio of the silicon oxide film 77 to the silicon nitride film 75 is about 1 to 2.

Further, as shown in FIG. 5C, in the second step after the silicon oxide film 75 in the contact hole 83 is completely removed, the gas contains 10 to 100 sccm of CO 2.
Etching is performed under the same conditions as the above-described first-stage etching except that (carbon monoxide) is added. At this time, the etching selection ratio of the silicon oxide film 73 to the silicon nitride film 75 is about 10 to 20.

Therefore, by the first-stage etching, the silicon nitride film 75 is completely removed in the contact holes 83 earlier than the contact holes 82, and the silicon oxide film 73 is exposed. Further, when the silicon oxide film 73 is exposed at the bottom of the contact hole 83, the polycrystalline silicon film 76 is excessively etched more than that shown in FIG. 5B, and the contact hole 82 penetrates the polycrystalline silicon film 76. Even in this case, the silicon nitride film 75 serves as an etching stopper in the second-stage etching. Therefore, the contact hole 82
Does not reach the polycrystalline silicon film 74 (that is, the silicon nitride film 75 in the contact hole 82 is not completely removed), and an electrical short circuit occurs between the polycrystalline silicon film 76 and the polycrystalline silicon film 74. Can be prevented.

The switching from the first-stage etching to the second-stage etching, that is, the detection of the end point of the first-stage etching is performed by observing the emission intensity of the wavelength 336 nm in plasma, that is, the emission intensity of NH. .

That is, during the etching of the silicon oxide film 77, the emission intensity at the wavelength of 336 nm is weak, as indicated by the data a in FIG. Then, when the etching of the silicon nitride film 75 in the contact hole 83 is started, the emission intensity at the wavelength of 336 nm becomes strong as shown by the data b in FIG.

After that, if the contact hole 83 does not penetrate the silicon nitride film 75 and the contact hole 82 does not penetrate the polycrystalline silicon film 76 as shown in FIG. 5B, the silicon nitride film 75 is etched. Because there is no
As indicated by the data c in FIG. 6, the emission intensity at the wavelength of 336 nm is attenuated. Therefore, when this attenuation is detected,
Switching from the first-stage etching to the second-stage etching is performed.

On the other hand, if the contact hole 82 penetrates the polycrystalline silicon film 76 when the contact hole 83 penetrates the silicon nitride film 75, the contact hole 82
Since the silicon nitride film 75 is etched therein, FIG.
As indicated by the data d therein, there is little attenuation of the emission intensity at the wavelength of 336 nm. However, since there is some attenuation,
When this attenuation is detected, the first-stage etching is switched to the second-stage etching. in this way,
By detecting the attenuation of the emission intensity at the wavelength of 336 nm in the plasma, it is possible to accurately switch between the first stage and the second stage of etching. The etching may be switched by monitoring the time.

As described above, according to the present embodiment, the two contact holes 8 having different depths are formed by one etching process without causing the shallow contact holes 82 to penetrate.
Since 2 and 83 can be formed at the same time, a highly reliable semiconductor device can be manufactured at low cost.

In any of the above first to third embodiments, the present invention is applied to the manufacture of a semiconductor device having contact holes having different depths, but contact holes having different diameters are used. The present invention can be applied to the manufacture of a semiconductor device having the semiconductor device.

[0076]

According to the present invention, since the lithography process and the etching process for forming a plurality of contact holes having at least one of the depth and the diameter different from each other may be performed once, the total number of processes may be small. Since it is also possible to suppress a decrease in yield due to misalignment of contact holes due to execution of a plurality of lithography processes, a semiconductor device can be manufactured at low cost.

Moreover, since the amount of etching of the conductive layer at the bottom of the shallow (or large diameter) contact hole can be reduced, the contact hole also penetrates the insulating film underlying these conductive layers. Therefore, it is possible to prevent electrical short circuit between these conductive layers and the conductive layers therebelow. Further, since it is possible to increase the film thickness margin of the conductive layer when the portion into which carbon is injected by etching is removed by light etching, it is possible to manufacture a highly reliable semiconductor device.

Further, it is possible to reduce the etching amount of the conductive layer at the bottom of the contact hole having a shallow depth (or a large diameter) without increasing the etching selection ratio of the interlayer insulating film to the conductive layer. Therefore, it is possible to prevent the shape of the contact hole from being deteriorated, prevent the contact resistance from increasing, and manufacture a semiconductor device having a high operation speed.

In the present invention according to another aspect, since the etching is first performed under the condition that the etching rate of the upper conductive layer is slower than that of the third insulating film, the second insulating film has a second contact hole rather than the second contact hole. One contact hole removes everything quickly. Then, after the second insulating film in the first contact hole is completely removed, etching is performed under the condition that the etching rate of the second insulating film is slower than that of the first insulating film. Therefore, even if the second contact hole penetrates the upper conductive layer, the second insulating film in the second contact hole functions as an etching stopper, so that another conductive layer is formed under the upper conductive layer. Even in such a case, the second contact hole does not reach this conductive layer, and a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in process order.

FIG. 3 is a cross-sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a second embodiment of the present invention in process order.

FIG. 5 is a cross-sectional view showing a third embodiment of the present invention in process order.

FIG. 6 is a graph showing the relationship between etching time and emission intensity in the third embodiment.

FIG. 7 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device in the order of steps.

FIG. 8 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 9 is a cross-sectional view for explaining a problem in a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 32 Impurity Diffusion Layer 33, 36 Interlayer Insulating Film 34 Polycrystalline Silicon Film 37 Silicon Nitride Film 42 BPSG Film 44 Contact Hole (Second Contact Hole) 45 Contact Hole (First Contact Hole)

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device having a first contact hole and a second contact hole having a depth relatively smaller than that of the first contact hole, wherein the first contact hole is formed. A first film having a film thickness at a portion where the second contact hole is formed is larger than a film thickness at a portion where the second contact hole is formed; and a film made of a material different from the first film. A step of forming a second film having a film thickness at a portion where the second contact hole is formed is larger than a film thickness at a portion where the first contact hole is formed; Using the mask having the opening pattern of the second contact holes, etching is performed under the condition that the etching rate of the second film is slower than that of the first film, and the first film and the second film are etched. The first contact on the membrane And a method of manufacturing a semiconductor device characterized by a step of forming a second contact hole at the same time. 2. The second film is formed in a portion in which the second contact hole is formed, and is not formed in a portion in which the first contact hole is formed. 1. The method for manufacturing a semiconductor device according to 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first film is a composite film including a plurality of films. 4. Manufacturing of a semiconductor device having a first contact hole reaching a lower conductive layer and a second contact hole reaching an upper conductive layer and having a depth relatively shallower than the first contact hole. In the method, a step of sequentially forming a first insulating film and a second insulating film made of a material different from the first insulating film on the lower conductive layer, and the upper layer on the second insulating film. Patterning a conductive layer, then forming a third insulating film on the entire surface, and using a mask having an opening pattern of the first contact hole and the second contact hole, Etching under the condition that the etching rate of the upper conductive layer is slower than that of the third insulating film, until the second insulating film in the first contact hole is completely removed; Hole and Using the mask having the opening pattern of the second contact hole, the first contact hole in the first contact hole is etched under the condition that the etching rate of the second insulating film is slower than that of the first insulating film. A step of performing etching until the insulating film is completely removed and the lower conductive layer is exposed. 5. The upper conductive layer is a polycrystalline silicon film, the first insulating film is a silicon oxide film, and
The method for manufacturing a semiconductor device according to claim 4, wherein the second insulating film is a silicon nitride film. 6. In the step of performing etching until all of the second insulating film in the first contact hole is removed, etching is performed using a gas containing no carbon monoxide, and the lower conductive layer is formed. The method for manufacturing a semiconductor device according to claim 5, wherein in the step of performing etching until the exposed portion is exposed, the etching is performed using a gas containing carbon monoxide. 7. The method according to claim 6, wherein it is detected that all of the second insulating film in the first contact hole is removed by attenuating the emission intensity at a wavelength of 336 nm in plasma. Of manufacturing a semiconductor device of. 8. The semiconductor according to claim 1, wherein the second contact hole is a contact hole having a diameter relatively larger than that of the first contact hole. Device manufacturing method.