JPH0916539A - Shared memory applying system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save the address space of a main storage by sharing an address with two kinds of main memory circuits and switching the selection of a main storage space by a data transfer direction between the main storage space and a control processor. SOLUTION: A transfer mode setting circuit 5 receives a read-in signal 16 and a write signal 17 from the control processor 1, and outputs the transfer mode signal 18 of either a read-in mode signal or write mode signal to a switching circuit 6. The switching circuit 6 receives a shared memory selection signal 10, and outputs a shared memory selection signal 14(15) in accordance with the transfer mode signal 18 to a shared memory circuit 2(3). Namely, the shared memory selection signal 10 inputted to the switching circuit 6 is outputted as the shared memory selection signal 14 to the shared memory circuit 2 in a read-in mode. Also, the shared memory selection signal 10 inputted to the switching circuit 6 is outputted as the shared memory selection signal 15 to the shared memory circuit 3 in a write mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory use method for sharing the main memory contents of a control processor with a shared memory space secured on a main memory space as a medium.

[0002]

2. Description of the Related Art Conventionally, when a main memory content is shared between control processors, a main memory capable of bidirectional information transfer from the control processor to the main memory circuit and from the main memory circuit to the control processor. The circuit was used as shared memory.

[0003]

In the above-mentioned shared memory use system by the main memory circuit capable of bidirectional information transfer, it is necessary to arrange the write main memory circuit and the read main memory circuit in different address spaces. Therefore, there is a problem that the main memory space is pressed down as the capacity of the shared memory increases.

It is an object of the present invention to provide a shared memory use system which saves the address space of the main memory circuit shared by the control processors.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention is a memory use system in which a part of a main memory space is used as a shared memory space and a main memory space is shared by a control processor. It is characterized in that an address is shared by two kinds of dedicated main memory circuits and the selection of the main memory space is switched depending on the direction of data transfer between the main memory space and the control processor.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a shared memory using method according to an embodiment of the present invention. As shown in FIG. 1, the shared memory using method of the present invention has a basic configuration including a control processor 1, a shared memory circuit 2, a shared memory circuit 3, and an address decoder 4, a transfer mode setting circuit 5, The switching circuit 6 is added.

The transfer mode setting circuit 5 sets a data transfer mode, receives a read signal 16 and a write signal 17 from the control processor 1, and transfers a transfer mode signal 18 which is either a read mode signal or a write mode signal. Is output to the switching circuit 6. Between the control processor 1 and the shared memory circuits 2 and 3, the data signal 7
Is sent and received. The control processor 1 gives an address signal 8 to the shared memories 2 and 3, and gives an address signal 9 to the address decoder 4.

The switching circuit 6 receives the shared memory selection signal 10 and outputs the shared memory selection signal 14 or 15 corresponding to the transfer mode signal 18 to the shared memory circuit 2 or 3. That is, in the read mode, the shared memory selection signal 10 input to the switching circuit 6 is output as the shared memory selection signal 14 to the shared memory circuit 2. In the write mode, the shared memory selection signal 10 input to the switching circuit 6 is transferred to the shared memory selection signal 15 to the shared memory circuit 3.
Output as Therefore, the shared memory circuits 2 and 3
, Which are arranged in the same address space, operate as independent read-only and write-only shared memories.

FIG. 2 is a block diagram showing another embodiment of the present invention in the case where the above-mentioned shared memory use method is applied to a plurality of control processors.

As shown in FIG. 2, the shared memory using method of the present invention includes control processors 21 and 22, shared memory circuits 23 and 24, address decoders 25 and 26, and transfer mode setting circuits 27 and 28. And switching circuits 29 and 30.

A data signal 31 is supplied from the shared memory circuit 23 to the control processors 21 and 22, and a data signal 32 is supplied from the shared memory circuit 24 to the control processors 21 and 22.
22. Address signal 33 is applied from control processor 21 to control processors 21 and 22 and address decoder 25, and address signal 34 is applied from control processor 22 to control processors 21 and 22 and address decoder 26. A read signal 35 is given from the control processor 21 to the shared memory circuit 23 and the transfer mode setting circuit 27. A read signal 36 is given from the control processor 22 to the shared memory circuit 24 and the transfer mode setting circuit 28. A write signal 37 is given from the control processor 21 to the shared memory circuit 23 and the transfer mode setting circuit 27. A write signal 38 is applied from the control processor 22 to the shared memory circuit 24 and the transfer mode setting circuit 28.

The control processor 21 selects the shared memory circuit 23 in the read mode, and selects the shared memory circuit 24 in the write mode. On the other hand, the control processor 22 uses the shared memory circuit 2 in the read mode.
4 is selected and the shared memory circuit 2 is used in the write mode.
Select 3.

FIG. 3 shows the control processor 21 in FIG.
And FIG. 22 is a diagram showing an address space of main memory circuits 22 and 22. The control processors 21 and 22 share the address space of the two shared memory circuits 23 and 24, and operate one shared memory circuit as a read-only memory and the other shared memory circuit as a write-only memory. Memory transfer between 22 is realized on the same address space. That is, the shared memory 23 is used for the memory transfer from the control processor 21 to the control processor 22, and the shared memory 24 is used for the memory transfer from the control processor 22 to the control processor 21.

[0015]

According to the present invention, a shared memory space is provided in a fixed area of the main memory space, and a read-only main memory circuit and a write-only main memory circuit arranged in the same address space are selected and used. The address space of the main memory can be saved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment in which the shared memory use system of the present invention is applied to a plurality of control processors.

FIG. 3 is a diagram showing an address space of a main memory of each control processor in the shared memory using system shown in FIG.

[Explanation of symbols]

 1 control processor 2,3 shared memory circuit 4 address decoder 5 transfer mode setting circuit 6 switching circuit 7 data signal 8,9 address signal 10,14,15 shared memory selection signal 11-13 main memory selection signal 16 read signal 17 write signal 18 transfer mode signal 21,22 control processor 23,24 shared memory (circuit) 25,26 address decoder 27,28 transfer mode setting circuit 29,30 switching circuit 31,32 data signal 33,34 address signal 35,36 read signal 37 , 38 Write signal

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[Procedure amendment]

[Submission date] September 4, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

A data signal 31 is applied from the shared memory circuit 23 to the control processor 21, and a data signal 32 is applied from the shared memory circuit 24 to the control processor 22. A data signal 31 is applied from the control processor 21 to the shared memory circuit 24, and a data signal 32 is applied from the control processor 22 to the shared memory circuit 23.
The control processor 21 supplies the address signal 33 to the shared memory circuits 23 and 24 and the address decoder 25, and the control processor 22 outputs the address signal 34 to the shared memory circuits 23 and 24 and the address decoder 26.
Given to. Read signal 3 from control processor 21
5 is a shared memory circuit 23 and a transfer mode setting circuit 27
Given to. Read signal 3 from control processor 22
6 is a shared memory circuit 24 and a transfer mode setting circuit 28
Given to. Write signal 3 from control processor 21
7 is a shared memory circuit 23 and a transfer mode setting circuit 27.
Given to. Write signal 3 from control processor 22
8 is a shared memory circuit 24 and a transfer mode setting circuit 28
Given to.

Claims (2)

[Claims] 1. In a shared memory use method in which a part of the main memory space is used as a shared memory space and the control processor shares the main memory space, two types of main memory circuits, a write-only and a read-only, share an address, A shared memory usage method characterized by switching the selection of the main storage space according to the direction of data transfer between the space and the control processor. 2. The shared memory using method according to claim 1, further comprising means for setting a data transfer mode for determining an access mode to the shared memory space secured in a part of the main memory space, and reading. It has a means for sharing an address of a dedicated shared memory space and an address of a shared memory space for writing only, and a means for selecting one of the read-only or write-only shared memory space depending on the data transfer mode. Shared memory usage method characterized by.