JPH0917334A - Method for forming field emission electron source array - Google Patents

Abstract

PURPOSE: To provide a forming method of a field emission electron source array by which a distance between emitter and gate electrodes can be shortened. CONSTITUTION: An insulating mask 14 is formed on a backing 10. Next, etching is performed by using the insulating mask, and a cone is formed on the backing. Next, an insulating layer 18 is formed on a surface of the backing containing the insulating mask 14. Next, metallic electrode layers 20 (20a and 20b) are formed on the insulating mask and the insulating layer by using a magnetron sputtering method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a field emission electron source array.

[0002]

2. Description of the Related Art A conventional method for forming a field emission electron source array is disclosed in, for example, Japanese Patent Laid-Open No. 5-94762.

According to Japanese Patent Laid-Open No. 5-94762, first, a silicon dioxide layer is formed on the surface of an n-type silicon substrate by a thermal oxidation method. Next, a resist is applied on the silicon dioxide layer and the silicon dioxide layer is etched by photolithography to form a circular mask pattern. Then, using this mask pattern as a mask, the surface of the silicon substrate is isotropically etched by a dry etching method to form a convex portion having a conical shape which is the basis of the cold cathode. Then, a silicon dioxide layer is formed on the surface of the silicon substrate including the convex portion by a thermal oxidation method.

Next, while rotating the center of the convex portion, vapor deposition is performed from an oblique direction to form a metal electrode layer on the surface of the silicon dioxide layer, and the silicon dioxide layer is removed by selective etching to expose the tip of the convex portion. Let

[0005]

However, the above-described method of forming a field emission electron source array has the following problems.

FIGS. 4A and 4B are views for explaining the conventional method of forming a metal electrode layer and the distance between the tip of the convex portion (also referred to as the tip of the emitter) and the gate electrode. Is.

Conventionally, when forming the metal electrode layer 54,
The metal electrode layer 54 is formed by the oblique vapor deposition method while rotating the sample.
In order to form, the vapor deposition is performed at a vapor deposition angle θ from the vertical direction of the outer periphery of the insulating mask 56. Therefore, the metal electrode layer 54 is formed on the wall surface of the emitter 51 and the surface of the Si wafer 50, which are separated from the bottom surface of the insulating mask 56, and the insulating layer 52 is etched to expose the tip of the emitter 51. In this case, the distance (b) between the tip of the emitter 51 and the metal electrode layer 54 becomes long. For this reason, when the field emission electron source array is operated to emit electrons, the electrons cannot be emitted unless the gate voltage applied between the gate electrode and the Si wafer is increased. To reduce the gate voltage and increase the electron emission efficiency, the emitter 5
It is necessary to shorten the distance between the tip portion of 1 and the gate electrode.

Therefore, there has been a demand for a method of forming a field emission electron source array which can shorten the distance between the tip of the emitter and the gate electrode.

[0009]

Therefore, according to the method of forming a field emission electron source array of the present invention, a cone is formed on a base, and the cone is surrounded by an insulating layer and a metal electrode layer. In forming a field emission electron source array with, a step of forming an insulating mask on the base, a step of forming a cone on the base by etching using the insulating mask, and an insulating layer on the surface of the base including the cone. And a step of forming a metal electrode layer on the insulating mask and the insulating layer by using a magnetron sputtering method.

In implementing the present invention, the magnetron sputtering conditions are a high frequency power density of 0.1 to 5.0.
(W / cm) ² and the pressure is preferably 1 to 10 (Pa).

[0011]

As described above, according to the method for forming the field emission electron source array of the present invention, after forming the insulating mask on the base, etching is performed to form the pyramid on the base. After that, an insulating layer is formed on the surface of the base including the cone, and the high frequency power density is set to 0.1 to 0.1 as a condition of magnetron sputtering.
The metal electrode layer is formed on the insulating mask and the insulating layer by setting the pressure to 5.0 (W / cm ² ) and the pressure to 1 to 10 (Pa). By forming the metal electrode layer using the magnetron sputtering method, the metal electrode layer can be formed up to the tip of the cone, that is, near the boundary between the cone and the insulating mask. After that, the insulating mask on the lower side in contact with the insulating mask is removed by etching by selective etching to expose the cone, whereby the insulating mask is removed and an opening is formed in the metal electrode layer. Since the distance between the inner wall of the opening of the metal electrode layer and the tip of the cone is shorter than in the conventional case, the gate voltage can be reduced.

[0012]

Embodiments of the method of forming a field emission electron source array (hereinafter referred to as FEA) of the present invention will be described below with reference to the drawings. FIGS. 1 to 3 merely show the shapes, sizes, and arrangements of the components so that the present invention can be understood. Further, the materials used, the processing time, the temperature, the film thickness and other numerical conditions described in the following description are only suitable examples within the scope of the present invention.

1. Method of Forming FEA Next, a method of forming FEA will be described with reference to FIGS. 1A to 1C and 2A to 2B are process drawings for explaining the forming process of this embodiment.

In this embodiment, a silicon (Si) wafer is used as the base 10. This Si wafer 10 has n-type conductivity, and the surface orientation of the Si wafer surface is (10
0) plane, and the resistivity of the Si wafer 10 is about 0.1 to 0.
2 Ω · cm.

Next, the surface of the Si wafer 10 is thermally oxidized (1100 ° C., 2 ° C.) in a dry oxygen (O ₂ ) atmosphere.
Then, the insulating layer 12 is formed (FIG. 1A).
In this embodiment, the insulating layer 12 is made of silicon dioxide (S
Also referred to as an iO ₂ ) layer, the thickness of the SiO ₂ layer 12 is about 2 μm.
And

After that, S is formed by photolithography.
The iO ₂ layer 12 is etched to form an insulating mask 14 (FIG. 1B). Further, in this embodiment, the insulating mask 14 has a circular shape and the mask diameter is about 2 μm.

Next, anisotropic etching is performed to form the cones 16 on the Si wafer 10 ((C) of FIG. 1). In this embodiment, since the Si wafer 10 is etched using the circular insulating mask 14, the cone 16 has a conical shape. Further, when the cone 16 is formed, the tip of the cone 16 is preferably formed to have an acute angle so as to have a diameter as small as possible so that the insulating mask 14 is not detached.
Here, the diameter of the tip of the cone 16 is set to about 0.1 to 0.5.
Set to about μm. Further, here, the cone 16 is also referred to as an emitter cone, and the Si wafer 10 and the emitter cone 16 are collectively referred to as a cone-attached Si wafer 17. The etching conditions for forming the emitter cone 16 are as follows.

Etchant liquid: 10 wt% KOH aqueous solution + 20 wt% isopropyl alcohol (IPA) + water (H ₂ O) Etchant temperature: 39 to 41 ° C. Etching rate: 2.5 to 3 μm / hour Si wafer using the above etching liquid When 10 is etched, the inclination angle of the emitter cone 16 (angle from the Si wafer to the wall surface of the emitter cone) is about 55 degrees. In this embodiment, the Si wafer 10 is etched by wet etching to form the emitter cone, but the reactive ion etching method may be used instead of the wet etching to form the emitter cone by dry etching. .

Next, the gate insulating layer 18 is formed on the surface of the Si wafer 10 including the emitter cone 16 by the thermal oxidation method ((A) of FIG. 2). The conditions of thermal oxidation at this time are
It is as follows.

Atmosphere gas: Dry oxygen (O ₂ ) gas Heating temperature: 1100 ° C., heating time: 10 hours In this embodiment, the thickness of the gate insulating layer 18 is about 0.5 μm.
m. By forming the gate insulating layer 18, the tip of the emitter cone 16 can have an acute angle.
Note that, here, the emitter cone covered with the gate insulating layer 18 after the gate insulating layer 18 is formed is referred to as a second emitter cone 16a.

Next, the metal electrode layer 20 is formed on the gate insulating layer 18 by using the magnetron sputtering method (FIG. 2B). The film forming conditions by the magnetron sputtering method are as follows.

Target electrode: Tungsten (W) Atmosphere gas: Argon (Ar) gas, Ar flow rate: 2
0 sccm RF power density: 2 W / cm ² pressure: 2.0 Pa Substrate temperature: 200 ° C. The above-mentioned film forming conditions are the optimum conditions of this embodiment, and the RF power density is preferably 0.1 to 5. 0W / c
m ² and the pressure is preferably in the range of 1 to 10 Pa.
Further, here, the metal electrode layer 20 formed on the insulating mask 14 is indicated by a reference numeral 20a, and the second emitter cone 16
The metal electrode layer 20 formed on a and the plane area extending from the second emitter cone 16a is indicated by the reference numeral 20b. In addition, in this embodiment, the insulating mask 14
The metal electrode layer 20a formed in the above and the metal electrode layer 20b formed in the second emitter cone 16a and the planar region are collectively referred to as the metal electrode layer 20. Further, in this embodiment, the metal electrode layer 20 is also referred to as a tungsten (W) layer.

When the metal electrode layer 20 is formed by magnetron sputtering, argon (Ar) ions accelerated in vacuum collide with the target, and the tungsten atoms and molecules of the ejected target are isolated mask 14. The W layer 20 is formed by wrapping around to a region extremely close to the tip of the second emitter cone 16a on the lower side.

Next, the insulating mask 14 and the gate insulating layer 18 are removed by etching by a selective etching method to obtain a second
The emitter cone 16a is exposed. At this time, the insulating mask 14 is removed and the opening 24 is formed in the W layer 20 ((C) of FIG. 2). In this embodiment, the W layer 20 having the opening 24 is referred to as a gate electrode 22. At this time, it is preferable to use an etching solution prepared by adding an aqueous ammonia solution (about 5% by weight) to an aqueous hydrofluoric acid solution (5% by weight).

FIG. 3 is an enlarged sectional view of the structure of FIG. 2 (C). According to the FEA forming method of this embodiment, the gate electrode 2 when the insulating mask 14 is removed
Since the diameter (L) of the second opening 24 is approximately the same as the diameter of the tip of the emitter cone 16 formed on the lower side of the insulating mask 14, the diameter of the gate electrode 22 from the tip of the second emitter cone 16a. The distance (a) to the wall surface of the opening can be shortened. Here, the distance from the second emitter cone 16a to the wall surface of the opening of the gate electrode 22 is defined as
It is also called the distance between gate electrodes.

For comparison with this embodiment, FIG.
With reference to (B) and (B), a conventional example (JP-A-5-9476)
No. 2) emitter-gate electrode distance will be described.

In the conventional example, the insulating layer 52 is formed after the convex portion (emitter) 51 is formed on the Si wafer 50. After that, the metal electrode layer 54 is formed by oblique vapor deposition. Therefore, the metal electrode layer 54 is formed in a region of the insulating layer 54 which is separated from the insulating mask 56 ((A) of FIG. 4).

Next, the insulating layer 52 is selectively etched to expose the tip of the emitter 51. At this time, the insulating mask 56 is also removed by etching the insulating layer 52. FIG. 4B is a cross-sectional view showing the FEA structure after the insulating layer 52 is removed by etching.

As can be understood from the structure of FIG. 4B, in the conventional example, the distance (b) from the tip of the emitter 51 to the metal electrode layer 54 is such that the metal electrode layer 54 is away from the mask 56. It will be longer.

As described above, the emitter of this embodiment
Since the distance (a) between the gate electrodes is shorter than the conventional distance (b), the gate voltage can be reduced when the FEA is operated.

FIG. 5 is a diagram for explaining the operation of the FEA.

A positive voltage side terminal (not shown) of the DC power supply 25 is connected to the surface of the gate electrode 22. Further, a terminal (not shown) on the negative voltage side of the DC power supply 25 is connected to the back surface of the Si wafer 10. Further, the negative voltage side of the DC power supply 25 is grounded (0V). When this FEA is installed in a vacuum and a positive voltage is applied to the gate electrode 22, electrons are emitted from the tip of the second emitter cone 16a by a tunnel phenomenon under a predetermined gate voltage. In the above-described embodiment, the example in which the cone is used as the emitter cone has been described, but the cone is not limited to any cone, and may be a cone having a polyhedron, for example.

Further, although tungsten is used as the material of the metal electrode layer in this embodiment, a refractory metal such as molybdenum (Mo) or niobium (Nb) may be used instead.

[0034]

As is apparent from the above description, according to the method of forming the field emission electron source array of the present invention, the metal electrode layer is formed by the magnetron sputtering method.
Therefore, the metal electrode layer can be formed up to the vicinity of the tip of the cone. After that, the insulating layer covering the cone is removed by selective etching to expose the cone. At this time, part of the metal electrode layer is also removed, and an opening is formed in the metal electrode layer. The size (diameter) of the opening of the metal electrode layer is approximately the same as the diameter of the tip of the cone formed using the insulating mask. Therefore, in the present invention, the distance between the tip of the cone and the inner wall of the opening of the metal electrode is shorter than in the conventional case, so that the gate voltage of the field emission electron source array can be reduced.

[Brief description of the drawings]

1A to 1C are process drawings provided for explaining a method of forming a field emission electron source array of the present invention.

2A to 2C are process drawings for explaining the forming method, following FIG.

FIG. 3 is a diagram for explaining a distance between an emitter and a gate electrode of the present invention.

4A to 4B are views for explaining a distance between a conventional emitter and gate electrode.

FIG. 5 is an operation diagram for explaining the electron emission principle of the field emission electron source array used in the present invention.

[Explanation of symbols]

 10: Si wafer 12: Insulating layer 14: Insulating mask 16: Emitter cone 16a: Second emitter cone 17: Si wafer with cone 18: Gate insulating layer 20: Metal electrode layer 22: Gate electrode 24: Opening 25: DC power supply 27: Ground

Claims (3)

[Claims] 1. When forming a cone on a lower surface and surrounding the cone with an insulating layer and a metal electrode layer to form a field emission electron source array, (a) forming an insulating mask on a base And (b) etching using the insulating mask to form a cone on the base, (c) forming an insulating layer on the surface of the base including the cone, (d) And a step of forming a metal electrode layer on the insulating mask and the insulating layer by using a magnetron sputtering method. 2. The method for forming a field emission electron source array according to claim 1, wherein a radio frequency (RF) power density is 0.1 to 5.0 (W / cm) as a magnetron sputtering condition in the step (d). ² )
And a pressure of 1 to 10 (Pa), the method for forming a field emission electron source array. 3. The method for forming a field emission electron source array according to claim 1, wherein after the step (d), the insulating layer covering the cone is removed by a selective etching method. A method of forming a field emission electron source array, comprising: exposing the substrate.