JPH0917874A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE: To provide a semiconductor device capable of obtaining a normal logic output even if an insulation film is destroyed under the fuse when a laser is emitted by enough energy to accurately cut a fuse, and its manufacturing method. CONSTITUTION: This embodiment comprises an insulation film 4 provided in a main face of an N type silicon substrate 1; a fuse 5 of a polycrystalline silicon structure for laser trimming which is provided on the insulation film 4; N type element areas 12, 13 formed in a first P well area 2; means 9, 32 for fixing a second P well area 3 formed in a location of the silicon substrate under the fuse 5 having the same depth as the first P well area 2 to a grounding potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a fuse of polycrystalline silicon for laser trimming and a manufacturing method thereof.

[0002]

2. Description of the Related Art Polycrystalline silicon fuses for laser trimming in semiconductor devices are used as switches for switching redundancy bits in semiconductor memories.

For example, in FIG. 4, a fuse 5 having a polycrystalline silicon structure and an N-channel insulated gate field effect transistor (hereinafter, referred to as NMOS) 10 are connected in series.
One end of the fuse 5 is connected to a high-potential-side power supply voltage (hereinafter referred to as VDD) line (terminal) 31 for supplying a positive voltage, and the other end of the fuse 5 is connected to an inverter (hereinafter referred to as INV, ) 33, and connects the source 12 of the NMOS 10 to a low-potential-side power supply voltage (hereinafter, referred to as ground voltage) line (terminal).
32, and the gate of the NMOS 10 is connected to the output terminal 35 of the INV 33.

In such a circuit, when the fuse 5 is not blown, the input terminal 34 of the INV 33 goes to a high level (H) and the output terminal 35 of the INV 33 goes to a low level (L), whereby the gate 14 goes to a low level. As a result, the NMOS 10 is turned off, and the output from this circuit goes low.

When the fuse 5 is cut by laser trimming, the input terminal 34 of the INV 33 goes low and the output terminal 35 of the INV 33 goes high, whereby the gate 14 goes high and the NMOS 10 is turned on. Is high level.

FIG. 7 shows a prior art structure of this circuit.
A field insulating film 4 is provided on a main surface of an N-type silicon substrate 1, and a P well region 2 is formed at a position where an NMOS 10 is formed. An N-type source 12 and an N-type drain 13 are formed in the P-well 2, and a polysilicon 14 is formed on the channel region 11 via a gate insulating film 15 to configure the NMOS 10. Further, a P-type source 22 and an N-type drain 23 are formed on the N-type silicon substrate 1, that is, the N-type main surface of the silicon substrate, and a polysilicon gate 24 is formed on the channel region 21 via a gate insulating film 25.
Are formed to form a P-channel insulated gate field effect transistor (hereinafter, referred to as PMOS) 20.
The NMOS 10 and the PMOS 20 form a semiconductor device having a CMOS structure, and the logic circuit of FIG.
OS10 is used.

A fuse 5 of a polycrystalline silicon structure for laser trimming is formed on the field insulating film 4, and a laser 8 is formed on the portion of the fuse 5 exposed at the opening 7 of the insulating layer 6.
, The fuse 5 is cut.

The P-well region 2 and the N-type source 12 are connected to a ground voltage line 32 and fixed at a ground potential (0 volt).
4 is connected to 1 to fix the substrate potential of the PMOS 20 to the VDD potential (positive potential), one end of the fuse 5 is connected to the VDD line 32, and the other end is connected to the N-type drain 13. I am configuring.

[0009]

In the semiconductor device shown in FIG. 7, the fuse 5 cannot be reliably cut unless the laser 8 is irradiated with sufficient energy.

For this reason, even if the fuse 5 can be cut, the field insulating film 4 thereunder is broken, and an accident that the cut end of the fuse 5 is short-circuited to the N-type silicon substrate 1 often occurs. At this time, if the cut end of the fuse 5 connected to the N-type drain 13 is short-circuited to the N-type silicon substrate 1, the input terminal 34 of the INV 33 in FIG. 4 goes high, and the output of this circuit goes low.

That is, although the fuse 5 is cut to set the output to a high level, the output is set to a low level, so that laser trimming becomes impossible.

On the other hand, Japanese Patent Laid-Open No. 3-83361 discloses that
A fuse is formed on a diffusion layer of the opposite conductivity type to the substrate via an insulating film, and even if the insulating film is broken during laser trimming, the fuse and the substrate are short-circuited due to a pn junction between the substrate and the diffusion layer. There is disclosed a technique for preventing such a situation and protecting the substrate surface. However, in this publication, there is no idea to obtain a normal logic output even if the insulating film is broken, so that there is no means for setting the diffusion layer to a fixed potential, and the potential of this diffusion layer is in a floating state. . Therefore, even when the surface of the substrate can be protected when the insulating film is broken, a normal logical output cannot be output. Also, since the diffusion layer of the publication is not specifically disclosed,
It is as shallow as normal source and drain. The pn junction of such a diffusion layer is easily destroyed by a laser having high energy that destroys the insulating film.

Therefore, an object of the present invention is to provide a semiconductor device capable of obtaining a normal logic output even if the insulating film under the fuse is broken when the fuse is surely cut by irradiating the laser with sufficient energy. It is to provide the manufacturing method.

[0014]

The present invention is characterized in that an insulating film provided on a main surface of a semiconductor substrate of a first conductivity type and a polycrystalline silicon structure for laser trimming provided on the insulating film. A fuse, a first well region of a second conductivity type opposite to the first conductivity type, formed in the substrate from the main surface, and a first well formed in the first well region.
A conductive type element region and a second conductive type second well region formed at the same depth as the first well region on the semiconductor substrate below the fuse and inside the substrate from the main surface. And means for fixing the second well region to a well potential different from the potential of the semiconductor substrate of the first conductivity type. Alternatively, an insulating film provided on the main surface of the semiconductor substrate of the first conductivity type, and a well region of the second conductivity type opposite to the first conductivity type and formed inside the substrate from the main surface. A first region formed in the well region;
A conductive element region, a fuse formed of polycrystalline silicon for laser trimming formed on the insulating film over the well region, and the well region having a potential different from that of the semiconductor substrate of the first conductive type And a means for fixing to a potential.

Here, the first conductivity type is N-type, the second conductivity type is P-type, the element region is an N-type source and drain region of NMOS, and the well potential is ground voltage supply. It can be fixed to the ground potential of zero potential by means.

Alternatively, the first conductivity type is a P type,
The second conductivity type is N-type, and the element region is RMOS.
And the well potential can be fixed to the positive potential VDD by the VDD supply means.

The element region is a source and drain region of an NMOS (or PMOS), and a PMOS (or NMOS) is formed at another portion of the semiconductor substrate.
A semiconductor device having a CMOS structure can be formed by using S (or NMOS).

Further, in manufacturing the semiconductor device having the first and second well regions, the second conductivity type is selectively and simultaneously applied to the first and second portions of the semiconductor substrate of the first conductivity type. Impurities are introduced, and then the insulating film is formed, whereby the first and second well regions having the same impurity concentration profile in the depth direction and the same depth are formed in the first and second portions, respectively. Can be formed.

[0019]

As described above, according to the present invention, the well region fixed to the ground potential or the VDD potential is provided under the insulating film below the fuse. Therefore, when the laser is irradiated with sufficient energy to surely cut the fuse, Even if the insulating film under the fuse is broken and the cut end of the fuse on the INV input side is short-circuited with the insulating film, the ground potential or the VDD potential is supplied from the well region, and the intended normal output level is obtained.

When the junction depth of the element regions such as the source and drain regions in the well region is, for example, 1 μm, the junction depth of the well region is 10 μm. In the case of 0.2 μm, the junction depth of the well region is 2 μm, and the junction depth of the well region is about 5 to 10 times the junction depth of the element region. Therefore, the above-mentioned normal output level is ensured without breaking the junction of the well region even with the irradiation of strong laser energy that breaks the insulating film.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 and 2 show the first embodiment of the present invention used for the logic circuit of FIG.
FIG. 3 is a diagram showing a semiconductor device according to an example of the present invention.

First, in FIG. 1, a P-type impurity is selectively introduced from the main surface of an N-type silicon substrate 1 to form a first P-type impurity region in each of a first portion and a second portion of the N-type silicon substrate. 2 'and the second P-type impurity region 3' are simultaneously formed. Thereafter, the first and second P layers are formed by heat treatment such as high-temperature oxidation when forming the field oxide film 4.
Type impurity regions 2 'and 3' are similarly expanded to obtain first P-well region 2 and second well region 3 in FIG.
Therefore, the first and second P-well regions 2 and 3 have the same impurity concentration profile in the depth direction and have the same deep junction depth, for example, 2 to 10 μm. .

In FIG. 2, an NMOS 10 and a PMOS 20 are formed in a region defined and surrounded by the field insulating film 4 to form a CMOS structure.

That is, the NMOS 10 has N-type source and drain regions 12 and 13 formed in the first P-well region 2 and having a shallow junction depth of 0.2 to 1.0 μm, and a gate insulating film on the channel region 11. It has a polysilicon 14 formed through the gate 15.

On the other hand, the PMOS 20 is a P-type source / drain region 22 having a shallow junction depth of 0.2 to 1.0 μm formed inside the N-type silicon substrate 1, that is, the N-type main surface of the silicon substrate 1. 23 and a polysilicide 2 formed on the channel region 21 with a gate insulating film 25 interposed therebetween.
4.

By thus forming the NMOS 10 and the PMOS 20, a semiconductor device having a CMOS structure is obtained.

Further, a fuse 5 of polycrystalline silicon is formed on the field insulating film 4 on the second P-well region 3, and an opening 7 is formed in the insulating layer 6 covering the whole.
Laser 8 through aperture 7 when needed for programming
Is applied to cut the fuse 5.

The first P well region 2 forming the NMOS 10 and the second P well region 3 formed below the fuse 5 are connected to the well electrode through contact holes provided in the insulating layer 6 and the field insulating film 4. The wires 9 are connected to the ground voltage lines 32, respectively. Therefore, similarly to the first P well 2, the second P well 3
Are also fixed to the ground potential (0 volt). Also, the N-type silicon substrate 1 is connected to the VDD line 31 and connected to the PMOS
The substrate potential of the fuse 20 is set to VDD, one end of the fuse 5 is connected to the VDD line 31, and the other end is connected to the N
Connected to the input terminal 34 of the INV (inverter) 33 (FIG. 4).
0 is connected to the output terminal 35 of the INV 33,
The N-type source 12 of the MOS 10 is connected to the ground voltage line 32.

When the fuse 5 is not blown, the input terminal 34 of the INV 33 goes high, the output terminal 35 of the INV 33 goes low in the logic circuit of FIG.
As a result, the gate 14 becomes low level and the NMOS 1
0 is turned off, and the output from this circuit goes to low level.

When the fuse 5 is cut by laser trimming, the input end 34 of the INV 33 becomes low level and the output end 35 of the INV 33 becomes high level, whereby the gate 14 becomes high level and the NMOS 10 is turned on. The output from is high level.

Referring to FIG. 2, when fusing fuse 5, it is necessary to increase the energy of laser 8 and reliably cut it. Therefore, the field insulating film 4 is broken and connected to the N-type drain 13 of the NMOS 10, that is, the cut end of the fuse connected to the input terminal of INV is short-circuited to the silicon region below the broken field insulating film.

However, in this embodiment, since this silicon region is the second P-well 3 fixed to the ground potential, even if this short circuit occurs, the ground potential from the second P-well region 3 causes INV Is at a low level and its output is at a high level.

That is, in a circuit in which the output is to be set to a high level by cutting a fuse, a predetermined programming can be performed since the output is set to a high level even if a short circuit occurs due to the destruction of the field insulating film.

Further, since the diffusion layer under the fuse is a well region having a junction depth approximately ten times as deep as the junction depth of the element regions such as the source and the drain, a laser having a strong energy enough to break the filled insulating film is obtained. The junction is not destroyed even by irradiation, and the high level can be reliably maintained.

FIG. 3 is a diagram showing a second embodiment of the present invention. Note that, in FIG. 3, the same or similar portions as those in FIG. 2 are denoted by the same reference numerals, and the duplicate description will be omitted.

In the first embodiment shown in FIG. 2, the first P well region 2 forming the NMOS 10 and the second P well region 3 formed below the fuse 5 are formed. However, in the second embodiment shown in FIG. 3, the NMOS 10 is formed in one P-well region 42, and the fuse 5 is located thereon.

In the first embodiment, the relative positional relationship between the NMOS 10 and the fuse 5 can be freely set, so that there is an advantage that the restriction on the layout design is reduced. On the other hand, in the second embodiment, one P-well region is provided. Since the formation of the NMOS 10 and the formation of the fuse 5 on the NMOS 10 are performed, the integration is advantageously improved.

Next, a third embodiment of the present invention will be described with reference to FIGS. 5 and FIG. 6, the same or similar parts as those in FIG. 2, FIG. 3 and FIG. 4 are indicated by the same reference numerals, and duplicate description will be omitted as much as possible.

In FIG. 5, a first N-type
Forming a well region 42 and a second well region 43;
The PMOS 20 is formed in the first N-well region 42 and the second
A fuse 5 having a polycrystalline silicon structure is formed on the field insulating film 4 on the N well region 43 of FIG. This first
N well region 42 and second N well region 43
As in the case of the first P-well region 2 and the second P-well region 3 in the embodiment of FIG.
The concentration profiles and the junction depth in the depth direction of the well region 42 and the second well region 43 are the same.

The first N well 42 and the second N well 43 are connected to the VD by the well electrode wiring 9 through the contact holes provided in the insulating layer 6 and the field insulating film 4.
The second N well 43 is connected to the VDD potential (positive voltage) similarly to the first N well 42. The P-type silicon substrate 41 is connected to the ground voltage line 32 to set the substrate potential of the NMOS 10 to the ground voltage. One end of the fuse 5 is connected to the ground voltage line 32, and the other end is connected to the P-type drain 2 of the PMOS 20.
3, its node is connected to the input terminal of INV (inverter), the gate 24 of the PMOS 20 is connected to the output terminal of INV, and the P-type source 22 of the PMOS 20 is connected to the VDD line 32.

When the fuse 5 is not blown, the input terminal 34 of the INV 33 goes low and the output terminal 35 of the INV 33 goes high in the logic circuit of FIG.
As a result, the gate 24 becomes high level and the PMOS2
0 is turned off, and the output from this circuit becomes high level.

When the fuse 5 is cut by laser trimming, the input terminal 34 of the INV 33 goes high, the output terminal 35 of the INV 33 goes low, the gate 24 goes low, and the PMOS 20 is turned on. Is low level.

In FIG. 5, in order to surely blow the fuse 5, the energy of the laser 8 is increased to break the field insulating film 4 and the P-type drain 23 of the PMOS 20.
, That is, if the cut end of the fuse connected to the input terminal of INV is short-circuited to the silicon region below the broken field insulating film, this silicon region remains at V
Since the second N well 43 is fixed to the DD potential,
By the VDD potential from the second N-well region 43, IN
The input terminal of V is at a high level, and its output is at a low level.

That is, in a circuit in which the output is to be set to a low level by cutting a fuse, the output is set to a low level even if a short circuit occurs due to destruction of the field insulating film, so that predetermined programming can be performed.

Also, as in the relationship between the first and second embodiments, the first and second N-well regions 42 and 43 of the third embodiment are integrated into one N-well. You can also.

[0046]

As described above, according to the present invention, a well of the opposite conductivity type to the substrate is formed under a laser trimming fuse made of polycrystalline silicon, and this well is set to a predetermined fixed potential. In addition, even if a high-energy laser is irradiated to ensure that the fuse is blown and the insulating film thereunder is broken, the potential of the circuit after laser trimming has the expected value.

Further, since a well having a junction several times to 10 times deeper than an element region such as a source and a drain is used,
Even if the laser irradiation is such that the insulating film is broken, the junction is not broken, and the fixed potential is reliably maintained.

Also, a CMOS NMOS or PM
Since it can be formed simultaneously with the well for forming the OS, even if the well of the present invention is provided, the normal manufacturing flow can be used as it is.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing some steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view including a partial circuit diagram showing the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a sectional view including a partial circuit diagram showing a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing a logic circuit used in the semiconductor devices of the first and second embodiments of the present invention.

FIG. 5 is a sectional view including a partial circuit diagram showing a semiconductor device according to a third embodiment of the present invention;

FIG. 6 is a circuit diagram showing a logic circuit used in a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view including a partial circuit diagram showing a conventional semiconductor device for obtaining the logic circuit of FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 N-type silicon substrate 2 P-well region (first P-well region) 2 ′ first P-type impurity region 3 second P-well region 3 ′ second P-type impurity region 4 field insulating film 5 polycrystalline silicon Fuse of configuration 6 Insulating layer 7 Opening 8 Laser 9 Well electrode wiring 10 NMOS 11 Channel region 12 N-type source 13 N-type drain 14 Polysilicon 15 Gate insulating film 20 NMOS 21 Channel region 22 P-type source 23 N-type drain 24 Polysilicon 25 Gate insulating film 31 VDD line 32 Ground voltage line 33 INV 34 Input terminal 35 Output terminal 41 P-type silicon substrate 42 First N-well region 43 Second N-well region

Claims (6)

[Claims] An insulating film provided on a main surface of a semiconductor substrate of a first conductivity type; a fuse having a polycrystalline silicon structure for laser trimming provided on the insulating film; A first well region of a second conductivity type formed of a conductivity type opposite to the first conductivity type, an element region of a first conductivity type formed in the first well region; A second well region of a second conductivity type formed at a location on the semiconductor substrate below the fuse and from the main surface to the inside of the substrate, having the same depth as the well region of Means for fixing a well potential different from the potential of the semiconductor substrate of the first conductivity type. 2. An insulating film provided on a main surface of a semiconductor substrate of a first conductivity type and a second conductivity type formed on the inside of the substrate from the main surface and having a conductivity type opposite to the first conductivity type. A well region;
A first-conductivity-type element region formed in the well region, and a fuse having a polycrystalline silicon structure for laser trimming formed on the insulating film on the well region,
Means for fixing the well region to a potential different from the potential of the semiconductor substrate of the first conductivity type. 3. The method according to claim 2, wherein the first conductivity type is N-type, and the second conductivity type is N-type.
2. The device according to claim 1, wherein the conductivity type is P-type, the element region is an N-type source and drain region of an N-channel insulated gate field effect transistor, and the well potential is a low potential side power supply potential. Alternatively, the semiconductor device according to claim 2. 4. The first conductivity type is P-type, and the second conductivity type is P-type.
2. The device according to claim 1, wherein the conductivity type is N-type, said element region is a P-type source and drain region of a P-channel insulated gate field-effect transistor, and said well potential is a power supply potential on a high potential side. Alternatively, the semiconductor device according to claim 2. 5. The element region is a source and drain region of a first insulated gate field effect transistor of a first conductivity type channel, and a second insulated gate of a second conductivity type channel in another part of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein a field effect transistor is formed, and the first and second transistors form a semiconductor device having a CMOS configuration. 6. When manufacturing the semiconductor device according to claim 1, the first and second semiconductor substrates of the first conductivity type are provided.
Of the second conductivity type is selectively and simultaneously introduced into the portion of the first and second portions, and then the insulating film is formed, whereby the impurity concentration profile in the depth direction and the first and second portions having the same depth are formed. The well region as the first and second
A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed on each of the above.