JPH09200041A - Majority processing circuit - Google Patents

Abstract

Kind Code: A1 Abstract: The present invention enables majority decision processing of a data block without using a majority logic operation circuit and the like, while reducing the number of shift registers by half, circuit scale, and power consumption. , Reduce manufacturing costs. A first arithmetic circuit 2 _-1 and a second arithmetic circuit 2 _-2
And the first data block or the third data block input to the data input terminal 4 are sequentially taken in and shifted, and the majority operation is performed to shift
After determining whether each bit forming the third data block or the third data block is "1" or "0" and taking the final bit of the third data block to perform the determination, the second arithmetic circuit 2 _-The data stored in _-2 is output as parallel data that has undergone the majority logic decision.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a majority operation processing circuit used in digital communication, and more particularly to a majority operation processing circuit which takes in a plurality of identical data and reproduces correct data by majority.

[0002]

2. Description of the Related Art As a majority arithmetic processing circuit used in digital communication, the circuit shown in FIG. 7 is conventionally known.
The majority arithmetic processing circuit 101 shown in this figure has a capacity of a received data block length, has a first shift register 102 that takes in received data and sequentially shifts it, and the same capacity as this first shift register 102. The second shift register 103 that fetches the data output from the first shift register 102 and sequentially shifts it, and the data that has the same capacity as this second shift register 103 and fetches the data output from the second shift register 103 A third shift register 104 that sequentially shifts, and a fourth shift register 105 that has the same capacity as that of the third shift register 104 and that captures data output from the third shift register 104 and sequentially shifts the data are provided. There is. Further, the majority arithmetic processing circuit 101 includes a received fifth data block and a fourth data block output from the first shift register 102 to a first data block output from the fourth shift register 105. On the other hand, a majority decision is performed for each bit to decide whether each bit constituting the first data block to the fifth data block is "1" or "0", and output the decision result. Logical operation circuit 106
A block of data having the same capacity as the first shift register 102 to the fourth shift register 105 and showing the determination result output from the majority logic operation circuit 106, and sequentially shifting the data block; And a shift register 107 for outputting as.

In this configuration, the first data block to the fifth data block having the same contents are received, and the first data block to the fifth data block are received.
When performing the majority logic operation of the second data block, 1
The first data block to the fourth data block are sequentially fetched, and the first data block to the fourth data block are sequentially shifted by the first shift register 102 to the fourth shift register 105 to obtain the same data as the first data block to the fourth data block. When fetching the fifth data block that is the content, the majority logic operation circuit 106 outputs the fifth data block and the first data block or the first shift register 102 output from the fourth shift register 105. A majority operation is performed for each bit with respect to the output fourth data block to determine whether each bit forming the first data block to the fifth data block is "1" or "0". To do. In parallel with this operation, the shift register 107 sequentially shifts the determination result output from the majority logic operation circuit 106 in units of "1" bits while fetching the final bit of the data block. , The stored data is output as parallel data for which the majority logic determination has been completed for the first data block to the fifth data block. However, in the majority arithmetic processing circuit 101 shown in FIG.
When the fifth data block is taken in with the first data block to the fourth data block stored in the first shift register 102 to the fourth shift register 105, the majority logic operation circuit 106 causes the first data block Since it is determined whether each bit forming the data block or the fifth data block is "1" or "0", the determination result is sequentially stored in the shift register 107 to be parallel data. , Not only need shift register for the number of data blocks,
The majority logic operation circuit 106 and the like are required, and there is a problem that the circuit scale, power consumption, manufacturing cost, etc. increase correspondingly. In view of the above circumstances, the present invention is
A majority decision operation that can perform a majority decision process for a data block without using a majority decision logic operation circuit and reduce the number of shift registers by half, and reduce circuit scale, power consumption, manufacturing cost, etc. It is intended to provide a processing circuit.

[0004]

In order to achieve the above-mentioned object, a majority arithmetic processing circuit according to the present invention comprises:
(2N-1) data blocks (where N is an integer greater than 1) having the same content of 1 bit or more input to the data input terminal are taken in and these (2N-1) data blocks are constructed. A majority decision processing circuit for making a majority decision on whether each bit is "1" or "0" has a shift register having the same length as the length of the data block, and a data block input to the data input terminal. A first arithmetic circuit for taking a logical sum of the data blocks held up to now in the shift register in its own circuit and holding the result of the logical sum again in the shift register in its own circuit;
A logic having a shift register having the same length as the length of the data block, and the logic of the data block input to the data input terminal and the previous data block held in the shift register in the arithmetic circuit of the previous stage. After taking the product, after taking the logical sum of this logical product result and the previous data block held in the shift register in the own circuit, the result of the logical sum is held again in the shift register in the own circuit The second to Nth operation circuits for
The data block held in the shift register of the arithmetic circuit is a data block after error correction.

According to a second aspect of the present invention, in the majority arithmetic processing circuit according to the first aspect, a shift register with reset is used as each shift register constituting the first to Nth arithmetic circuits, and the data input is performed. Of the (2N-1) data blocks to be error-corrected that are input to the terminals, a reset signal is supplied to each shift register before the first data block is input, and each shift register is supplied. It is characterized by resetting.

According to a third aspect of the present invention, in the majority arithmetic processing circuit according to the first aspect, a shift register having no reset function is used as each shift register forming the first to Nth arithmetic circuits. An AND gate that takes the logical product of the output of the shift register and the initialization signal and returns it to the input side of the shift register is used and is the error correction target input to the data input terminal (2).
When N-1) data blocks are input, while the first data block is being input, an initialization signal is input to each of the AND gates to input data of value "0" to the input side of the shift register. Characterized by returning the block.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. FIG. 1 is a block diagram showing a first embodiment of a majority arithmetic processing circuit according to the present invention.

The majority arithmetic processing circuit 1 shown in this figure comprises a first arithmetic circuit 2 _-1 and a second arithmetic circuit 2 _-2 ,
The first arithmetic circuit 2 _-1 and the second arithmetic circuit 2 _-2 sequentially take in the first data block to the third data block input to the data input terminal 4 or the third data block to shift the majority operation. Then, it is determined whether each bit constituting the first data block to the third data block is "1" or "0", and the final bit of the third data block is fetched and determined.
The data stored in the second arithmetic circuit 2 _-2 is output as the parallel data which has undergone the majority logic determination. First arithmetic circuit 2 _-1
Has a capacity of the same length as the block length of the data block to be processed, and when the reset signal is input to the reset terminal 5 _-1r , the content stored up to that point is "0".
To initialize, when the clock signal is inputted, sequentially each bit of the input data blocks to an input terminal 5 _-1I, shifted while taking a shift register _5-1 to be output from the output terminal 5 _-10 ORs the respective bit data blocks output from the output terminal 5 _-10 of the each bit of the input data blocks to the data input terminal 4 shift register _5-1, the shift register 5 _-1 It is provided with an OR gate 6 _-1 which is supplied to the input terminal 5 _-1i .

Then, when the clock signal is input, each bit of the data block stored in the shift register 5 _-1 up to that time is sequentially output from the output terminal 5 _-10 to output the second arithmetic circuit 2 _-2, and at the same time, each bit of the data block input to the data input terminal 4 and each bit of the previous data blocks stored in the shift register _5-1 are ORed and this is shifted. The data is sequentially stored in the register _5-1 . Second arithmetic circuit 2
_-2 has a capacity of the same length as the block length of the data block to be processed, and when a reset signal is input to reset terminal 5 _-2r , the contents stored up to that point are initialized to "0". , When the clock signal is being input, each bit of the data block input to the input terminal 5 _-2i is sequentially _fetched and shifted to output the output terminal 5
_-20 , the shift register 5 _-2, and each bit of the data block input to the data input terminal 4 and each bit of the data block output from the first arithmetic circuit 2 _-1 are ANDed. taking an aND gate 7 _-2, the logical sum of the respective bits of the data block output from the output terminal 5 _-20 of the shift register _5-2 and each bit of the data block output from the aND gate 7 _-2 , OR gate 6 _-2 supplied to the input terminal 5 _-2i of the shift register 5 _-2 .

When the clock signal is input, each bit of the data block stored in the shift register _5-2 up to that point is sequentially output from the output terminal _5-20 , and the data input terminal 4 is also connected. and each bit of the data block input to the ANDs the respective bit data blocks output from the first arithmetic circuit 2 _-1, and the bits obtained by further logical product, the shift register 5 _- The logical sum of each bit of the data block stored up to that point in ₂ is stored in the shift register 5 _-2 in sequence, and when the last bit is processed, it is stored in the shift register 5 _-2 . The stored data is output as parallel data that has undergone the majority logic determination.

Next, the operation of this embodiment will be described with reference to the block diagram shown in FIG. 1 and the table shown in FIG.
First, the shift register 5 _{-1 of} the first arithmetic circuit 2 _-1 , and the second
Reset signal to the shift register _5-2 arithmetic circuit _2-2 is the supply, each of these shift registers _{5-1, 5-2} are stored in the data is initialized to all "0", the processing target Preparations are made to accept the data blocks that have become. After that, the first data block (hereinafter, this data block is referred to as data block A) of the data blocks having the same number of bits set in advance and inputted to the data input terminal 4 is a bit block. sequentially in units, while being input, the shift register _5-2 which constitutes the first arithmetic circuit 2 _-1, if the clock signal to the shift register _5-2 of the second arithmetic circuit 2 _-2 inputted, first Arithmetic circuit 2
_-1 OR gate 6 _-1 , all bits stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 are "0".
Each bit of the data block and the bit of the data block A input to the data input terminal 4 are ORed, and the operation result (all bits are the same as the bits of the data block A). Data block) is stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 .

In parallel with this operation, each bit of the data block output from the first arithmetic circuit 2 _-1 , that is, the data block in which all the bits are "0", and the data input terminal 4 are connected. Input data block A
AND of each bit of is calculated, and the calculation result (data block in which all bits are “0”) and all of the _values stored in the shift register 5 _-2 of the second calculation circuit 2 _-2 . The logical sum of the data blocks whose bits are "0" is calculated, and the result of this calculation (the data blocks whose all bits are "0") is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2. Remembered. As a result, the data input terminal 4
After the last bit of data block A is input to,
As shown in the “column A” in the table of FIG. 2, the first arithmetic circuit 2 ₋₁
The contents of the data block A are stored in the shift register 5 _-1, and the data block in which all the bits are "0" are stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 .

Next, if a second data block having the same contents as the data block A (hereinafter, this data block is referred to as a data block B) is sequentially input to the data input terminal 4 bit by bit. , the OR gate _6-1 of the first arithmetic circuit 2 _-1, and each bit of the data block a is stored in the shift register _25-1 of the first arithmetic circuit 2 _-1, is input to the data input terminal 4 is logical OR operation between each bit of the data block B are, the calculation result (logical sum of opposing bit (a + B) data block indicating the (a + B)) shift of the first arithmetic circuit 2 _-1 registers _25-1 Memorized in. Further, in parallel with this operation, the data block A output from the first arithmetic circuit 2 _-1
And each bit of the data block B input to the data input terminal 4 are ANDed, and the operation result (data block (A · B) indicating the AND (A · B) of the opposing bits) is calculated. -B)) and each bit of the data block in which all the bits stored in the shift register 5 _-2 of the second operation circuit 2 _-2 are "0", the logical sum is calculated, This calculation result (data block (A
B)) is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 . As a result, after the last bit of the data block B has been input to the data input terminal 4, the shift register 5 _-1 of the first arithmetic circuit 2 _{-1 is transferred to} the first arithmetic circuit 2 _-1 as shown in "B column" in the table of FIG. Data block (A + B) is stored,
The data block (A / B) is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 .

Next, at the data input terminal 4, a third data block having the same contents as the data block A and the data block B (hereinafter, this data block is referred to as a data block C) is provided in bit units. sequentially, if the input of the first arithmetic circuit 2 _-1 OR gate _6-1
According to each bit of the data block (A + B) stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 ,
The logical sum of each bit of the data block C input to the data input terminal 4 is calculated, and the calculation result (the data block (A + B + C) indicating the logical sum (A + B + C) of the opposite bits) is the first calculation circuit. It is stored in the 2 ₋₁ shift register 5 ₋₁ . In parallel with this operation, the data blocks output from the first arithmetic circuit 2 _-1 (A +
The logical product of each bit of B) and each bit of the data block C input to the data input terminal 4 is operated, and the operation result (logical product of opposing bits (A + B)
The logical sum of each bit of the data block (A + B) and C) indicating C and each bit of the data block (A and B) stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 The data block (A that indicates the logical sum (A / B + B / C + C / A) of the calculated bits
B + B * C + C * A)) is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 .

As a result, after the last bit of the data block C has been input to the data input terminal 4, the data block shown in FIG.
Of as shown in "C field" in the table, the contents of the first arithmetic circuit 2 _-1 of the shift register _5-1 to the data blocks (A + B + C) is stored, the second arithmetic circuit 2 _-2 shift register _5-2
A data block (A.B + B.C + C.A) is stored in the memory, and this is output as parallel data for which majority logic has been determined for the data block A, the data block B, and the data block C. In this case, if all the corresponding bits of the respective bits of the data block A, the respective bits of the data block B, and the respective bits of the data block C, for example, the first bit are “1”, the shift register of the second arithmetic circuit _{2-2 5-2}
Data block stored in (A ・ B + B ・ C + C
As the value of the first bit of A), the bit having the value shown in the following expression is output. A · B + B · C + C · A = 1 · 1 + 1 · 1 + 1 · 1 = 1 + 1 + 1 = 1 Further, any one of these 1st bit, for example, the 1st bit of the data block A is “0”. ", The value of the first bit of the data block (A · B + B · C + C · A) stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2 ,
The bit with the value shown in the following expression is output. A • B + B • C + C • A = 0 • 1 + 1 • 1 + 1 • 0 = 0 + 1 + 0 = 1 Further, any two of these 1-bit bits, for example, the 1-bit bit of the data block A and the data If the 1st bit of the block B is "0", the data block ( _AB) stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2.
As the value of the first bit of (+ B * C + C * A), the bit having the value shown in the following expression is output. A • B + B • C + C • A = 0 • 0 + 0 • 1 + 1 • 0 = 0 + 0 + 0 = 0 Further, these first bit, that is, the first bit of the data block A and the first bit of the data block B , If the first bit of the data block C is all “0”, the data block (A · B + B · C + C ·) stored in the shift register 5 _-2 of the second operation circuit 2 _-2. As the value of the first bit in A), the bit having the value shown in the following expression is output. A · B + B · C + C · A = 0 · 0 + 0 · 0 + 0 · 0 = 0 + 0 + 0 = 0 As is clear from these results, the data block A and the data block B input to the data input terminal 4 are
In each bit of the data block C, if the bit information of at least two data blocks is common, the content of the common bit of each of these bits, that is, each bit of the data block A, the data block B, and the data block C, is supported. The result of the majority decision for each bit
It is stored in the shift register 5 _-2 of the arithmetic circuit 2 _-2 , and this is output as parallel data.

As described above, in this embodiment, the first arithmetic block 2 _-1 and the second arithmetic circuit 2 _-2 input the first data block to the third data block to the data input terminal 4.
While sequentially taking in and shifting the second data block, a majority operation is performed to determine whether each bit constituting the first data block to the third data block is "1" or "0", and the third data block is determined. After the final bit of the data block of (1) is fetched and the determination is performed, the data stored in the second arithmetic circuit 2 _-2 is output as parallel data that has undergone the majority logic determination. It is possible to reduce the circuit scale, power consumption, manufacturing cost, etc. by enabling majority decision processing of the data block without using the shift register and halving the number of shift registers.

FIG. 3 is a block diagram showing a second embodiment of the majority decision processing circuit according to the present invention. In this figure, the same parts as those shown in FIG. 1 are designated by the same reference numerals. The majority decision processing circuit 1b shown in this figure
Arithmetic circuit 2 _-1 , second arithmetic circuit 2 _-2, and third arithmetic circuit 2
_-3 and the first arithmetic circuit 2 _{-1 through} the third arithmetic circuit
The arithmetic circuit _2-3, to the first data block no input to the data input terminal 4 sequentially fifth data block, uptake, while shifting, by performing majority operation, the fifth to the free first data block each bit constituting the data block determines whether "1" or "0", after performing the determination by taking the last bit of the fifth data block, stored in the third arithmetic circuit 2 _-3 The data is output as parallel data that has undergone the majority logic determination. The first arithmetic circuit 2 _-1 has a capacity of the same length as the block length of the data block to be processed, and when a reset signal is input to the reset terminal 4, the content stored up to that point is set to "0". to initialize, when the clock signal is inputted, sequentially each bit of the input data blocks to an input terminal 5 _-1R, shifted while taking a shift register _5-1 to be output from the output terminal 5 _-10 ORs the respective bit data blocks output from the output terminal 5 _-10 of the each bit of the input data blocks to the data input terminal 4 shift register _5-1, the shift register 5 _-1 It is provided with an OR gate 6 _-1 which is supplied to the input terminal 5 _-1i .

When the clock signal is input, each bit of the data block stored in the shift register 5 _-1 up to that time is sequentially output from the output terminal 5 _-10 to output the second arithmetic circuit 2 _-2, and at the same time, each bit of the data block input to the data input terminal 4 and each bit of the previous data blocks stored in the shift register _5-1 are ORed and this is shifted. The data is sequentially stored in the register _5-1 . Second arithmetic circuit 2
_-2 has a capacity of the same length as the block length of the data block to be processed, and when a reset signal is input to reset terminal 5 _-2r , the contents stored up to that point are initialized to "0". , When the clock signal is being input, each bit of the data block input to the input terminal 5 _-2i is sequentially _fetched and shifted to output the output terminal 5
_-20 to output the shift register 5 _-2 , each bit of the data block input to the data input terminal 4, and the first
An AND gate 7 _-2 that takes the logical product of each bit of the data block output from the arithmetic circuit 2 _-1 , and each bit of the data block output from this AND gate 7 _-2 and the shift register 5 _-2 . An OR gate 6 which takes the logical sum of each bit of the data block output from the output terminal 5 _-20 and supplies it to the input terminal 5 _-2i of the shift register 5 _-2.
-2 and.

Then, when the clock signal is input, each bit of the data blocks stored in the shift register _5-2 up to that point is sequentially output from the output terminal 5 _-20 to output the third arithmetic circuit 2 _-3, and performs a logical product of each bit of the data block input to the data input terminal 4 and each bit of the data block output from the first arithmetic circuit 2 _-1 , and further calculates the logical product. and each bit obtained by taking the logical sum of the respective bits of it to the data block stored in the shift register _5-2, which sequentially shift register _5-2 to be stored therein. The third arithmetic circuit _2-3 has the capacity of the same length as the block length of the data block to be processed, when the reset signal is input to the reset terminal 5 _-3R, the settings stored until then " The shift register 5 which is initialized to 0 "and sequentially shifts while fetching each bit of the data block input to the input terminal 5 _-3i when the clock signal is input, and outputs from the output terminal 5 _-3O
-3 and the AND gate 7 _-3 which takes the logical product of each bit of the data block input to the data input terminal 4 and each bit of the data block output from the second arithmetic circuit 2 _-2.
And each bit of the data block output from the AND gate 7 _-3 and the output terminal 5 of the shift register 5 _-3.
-3O is provided with an OR gate 6 _-3, which is _ORed with each bit of the data block and supplied to the input terminal 5 _-3i of the shift register 5 _-3 .

Then, when the clock signal is input, each bit of the data block stored in the shift register 5 _-3 up to that time is sequentially output from the output terminal 5 _-3O, and at the same time, is input to the data input terminal 4. A logical product of each bit of the input data block and each bit of the data block output from the second operation circuit 2 _-2 is obtained, and each bit obtained by the logical product is obtained with the shift register 5 _-3. When the last bit is processed, the logical sum of each bit of the data blocks stored up to then is stored in the shift register 5 _-3 , and the last bit is processed.
The data stored in the shift register 5 _-3 is output as parallel data which has undergone the majority logic determination.

Next, the operation of this embodiment will be described with reference to the block diagram shown in FIG. 3 and the table shown in FIG.
First, the shift register 5 _{-1 of} the first arithmetic circuit 2 _-1 , and the second
The shift register 5 _-3 of the arithmetic circuit 2 _-2 and the third arithmetic circuit 2
_-3 is supplied with a reset signal to the shift register 5 _-3, and all the data stored in these shift registers 5 _-1 , 5 _-2 , 5 _-3 are initialized to "0", and the processing is performed. The target data block is prepared for acceptance. After that, the first data block (hereinafter, this data block is referred to as data block A) of the data blocks having the same number of bits set in advance and inputted to the data input terminal 4 is a bit block. sequentially in units, while being input, the shift register 5 _-1 constituting the first arithmetic circuit 2 _-1, a shift register _5-2 of the second arithmetic circuit 2 _-2, third arithmetic circuit _2-3 of the shift register If a clock signal is input to 5 _-3 , similarly to the operation of the majority arithmetic processing circuit 1 shown in FIG. 1, after the final bit of the data block A is input, the first arithmetic circuit 2 _-1 , a second arithmetic circuit 2 _-2, 3 the data block a is processed by an arithmetic circuit _2-3, as shown in "a column" in the table of FIG. 4, the first arithmetic circuit 2 _-1 data block a stores of the shift register 5 _-1 , The shift register 5 of the second arithmetic circuit 2 _-2 shift register _5-2 and the third arithmetic circuit 2 _-3
The data block in which all the bits are "0" is stored in _-3 .

Next, if a second data block having the same contents as the data block A (hereinafter, this data block is referred to as a data block B) is sequentially input to the data input terminal 4 bit by bit, After the last bit of the data block B is input, the data block (A + B) is stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 , as shown in the "B column" in the table of FIG. The data block (A) is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2.
· B) is stored, additionally all bits in the shift register 5 _-3 third arithmetic circuit _2-3 is "0" since the data blocks are stored. Thereafter, if a third data block having the same content as the data blocks A and B (hereinafter, this data block is referred to as a data block C) is sequentially input to the data input terminal 4 in bit units, After the last bit of the data block C has been input, FIG.
As shown in the "C column" in the table, the data block (A + B + C) is stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 , and the data block is stored in the shift register 5 _-2 of the second arithmetic circuit 2 _-2. The block (A · B + B · C + C · A) is stored, and further, the data block (A · B · C) is stored in the shift register 5 _-3 of the third arithmetic circuit 2 _-3 .

Next, a fourth data block having the same contents as the data blocks A, B, and C (hereinafter, this data block is referred to as data block D) is sequentially input to the data input terminal 4 bit by bit. If so, after the last bit of the data block D is input, the data block (A + B + C + D) is stored in the shift register 5 _-1 of the first arithmetic circuit 2 _-1 as shown in "D column" in the table of FIG. Is stored, and the data block {(A · B + A · C + A · D) + (B · C is stored in the shift register 5 ₋₂ of the second arithmetic circuit 2 _−2.
+ B · D) + C · D} is stored, further third arithmetic circuit _2-3 shift register _5-3 to the data block of {(A · B
C + A / B / D + A / C / D) + B / C / D} is stored. After that, a fifth data block (hereinafter, this data block is referred to as a data block E) having the same contents as the data blocks A, B, C and D is sequentially input to the data input terminal 4 bit by bit. Then, after the last bit of the data block E is input, the data block (A + B + C + D +) is _added to the shift register 5 _-1 of the first arithmetic circuit 2 _-1 as shown in the "E column" in the table of FIG.
E) is stored in the shift register 5 of the second arithmetic circuit 2 _-2.
-2 in the data block {(A ・ B + A ・ C + A ・ D + A ・
E) + (B ・ C + B ・ D + B ・ E) + (C ・ D + C ・
E) + D · E} is stored, further third arithmetic circuit _2-3 shift register _5-3 to the data block of {(A · B · C +
A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A
・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E)
+ C · D · E} is stored, the third arithmetic circuit _2-3 of the shift register _5-3 to the data block stored {(A · B · C + A · B · D + A · B · E + A · C · D
+ A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・
E + B • D • E) + C • D • E} is output as parallel data for which majority decision has been made for the data block A, the data block B, the data block C, the data block D, and the data block E.

In this case, each bit of the data block A, each bit of the data block B, each bit of the data block C, each bit of the data block D,
Wherein among the bits of the data block E, if so the corresponding bit, for example, the first bit of the bits are all "1", stored in the shift register 5 _-3 of the third arithmetic circuit 2 _-3 Data block {(A ・ B ・ C + A ・ B ・
D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・
E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・
As the value of the first bit of D · E}, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 +1 ・ 1 ・ 1) + (1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 + 1 ・ 1 ・ 1) +1 ・ 1 1 = {(1 + 1 + 1 + 1 + 1 + 1) + (1 + 1 + 1) +1} = {(1) + (1) +1} = 1 Further, of these 1-bit bits, for example, the 1-bit bit of the data block A is "0". , The data block stored in the shift register 5 _-3 of the third arithmetic circuit 2 _-3 {(A ・ B ・ C + A ・ B ・ D
+ A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E)
+ (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・
As the value of the first bit of E}, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(0 ・ 1 ・ 1 + 0 ・ 1 ・ 1 + 0 ・ 1 ・ 1 + 0 ・ 1 ・ 1 + 0 ・ 1 ・ 1 +0 ・ 1 ・ 1) + (1 ・ 1 ・ 1 + 1 ・ 1 ・ 1 + 1 ・ 1 ・ 1) +1 ・ 1 1} = {(0 + 0 + 0 + 0 + 0 + 0) + (1 + 1 + 1) +1} = {(0) + (1) +1} = 1 Further, of these 1st bit, for example, the 1st bit and data of the data block A If the first bit of the block B is "0", the data block {(A ・ B ・ C + A ・ B ・ D + A) stored in the shift register 5 _-3 of the third arithmetic circuit 2 _-3.・ B
・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・
C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E} 1
As the bit value, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(0 · 0 · 1 + 0 · 0 · 1 + 0 · 0 · 1 + 0 · 1 · 1 + 0 · 1 · 1 + 0 · 1 · 1) + (0 · 1 · 1 + 0 · 1 · 1 + 0 · 1 · 1) +1.1 1} = {(0 + 0 + 0 + 0 + 0 + 0) + (0 + 0 + 0) +1} = {(0) + (0) +1} = 1 Further, of these 1-bit bits, for example, the 1-bit bit of the data block A, the data If the first bit of the block B and the first bit of the data block C are "0", the data block stored in the shift register 5 _-3 of the third arithmetic circuit 2 _-3 { (A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C
・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・
As the value of the first bit of (C • E + B • D • E) + C • D • E}, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(0,0,0 + 0,0,1 + 0,0,1 + 0,0,1 + 0,0,1 +0,1,1) + (0,0,1 + 0,0,1 + 0,1,1) +0.1 1} = {(0 + 0 + 0 + 0 + 0 + 0) + (0 + 0 + 0) +0} = {(0) + (0) +0} = 0 Among these 1-bit bits, for example, the 1-bit bit of the data block A, the data 1 bit of bits of the block B, if set to 1 bit of the bits of the bit and the data block D of the first bit of the data block C is "0", the shift register 5 of the third arithmetic circuit 2 _{-3 -3} stored in the data block {(A ·
B / C + A / B / D + A / B / E + A / C / D + A / C
・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・
As the value of the first bit of (D · E) + C · D · E}, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(0,0,0 + 0,0,0 + 0,0,1 + 0,0,0 + 0,0,1 +0,0,1) + (0,0,0 + 0,0,1 + 0,0,1) +0,0 1} = {(0 + 0 + 0 + 0 + 0 + 0) + (0 + 0 + 0) +0} = {(0) + (0) +0} = 0 Among these 1-bit bits, for example, the 1-bit bit of the data block A, the data If the first bit of the block B, the first bit of the data block C, the first bit of the data block D, and the first bit of the data block E are all “0”, the third is stored in the shift register 5 _-3 arithmetic circuit 2 _-3 Data blocks {(A · B · C +
A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A
・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E)
As the value of the first bit of + C · D · E}, the bit having the value shown in the following expression is output. {(A ・ B ・ C + A ・ B ・ D + A ・ B ・ E + A ・ C ・ D + A ・ C ・ E + A ・ D ・ E) + (B ・ C ・ D + B ・ C ・ E + B ・ D ・ E) + C ・ D ・ E } = {(0,0,0 + 0,0,0 + 0,0,0 + 0,0,0 + 0,0,0 +0,0,0) + (0,0,0 + 0,0,0 + 0,0,0) +0,0 0} = {(0 + 0 + 0 + 0 + 0 + 0) + (0 + 0 + 0) +0} = {(0) + (0) +0} = 0 As is clear from these results, the data block A and the data block input to the data input terminal 4 In each bit of B, data block C, data block D, and data block E, if the bit information of at least three data blocks is common, the content of the common bit of each bit, that is, data block A, data block B, Data block , Data block D, the data for each bit of the block E, for each corresponding bit, majority judgment result third arithmetic circuit _2-3 of the shift register 5 _-3
Is stored in, and this is output as parallel data. As described above, in this embodiment, the first arithmetic circuit 2 _{-1 to} the third arithmetic circuit 2 _-3 sequentially take in the first data block to the fifth data block input to the data input terminal 4. While shifting, a majority operation is performed to determine whether each bit constituting the first data block to the fifth data block is "1" or "0", and the final bit of the fifth data block is determined. after performing the judgment is taken, since the output the data stored in the third arithmetic circuit _2-3 as a majority logic decision already parallel data, without the use of such majority logic operation circuit, and a shift It is possible to reduce the circuit scale, power consumption, and manufacturing cost by enabling majority decision processing of data blocks while reducing the number of registers by half.

FIG. 5 is a block diagram showing a third embodiment of the majority arithmetic processing circuit according to the present invention. In this figure, the same parts as those shown in FIGS. 1 and 3 are designated by the same reference numerals. Majority processing circuit 1 shown in this figure
c includes a first arithmetic circuit 2 _-1 , ..., An Nth arithmetic circuit 2 _-N , and these first arithmetic circuit 2 _{-1 through} Nth arithmetic circuit 2
_{By -N} , the first data block or the (2N-1) th data block input to the data input terminal 4 is sequentially fetched and shifted, and a majority operation is performed while shifting to obtain the first data block or the (2N-1) th data block. 2N-1)
After determining whether each bit constituting the th data block is "1" or "0" and fetching the final bit of the (2N-1) th data block to make a decision, the Nth operation circuit 2 _-N The data stored in is output as parallel data that has been subjected to majority logic determination.

The first arithmetic circuit 2 _-1 has a capacity of the same length as the block length of the data block to be processed, and when the reset signal is input to the reset terminal 2 _-1r , the data is stored until then. When the contents are initialized to "0" and the clock signal is input, the bits of the data block input to the input terminal 5 _-1i are sequentially _fetched and shifted, and output from the output terminal 5 _-1O. Register 5
_-1 and each bit of the data block input to the data input terminal 4 and each bit of the data block output from the output terminal 5 _-1O of the shift register 5 _-1 are _ORed to _{obtain the} shift register 5 _-1 input terminal 5 _{-1i or} OR gate 6 _-1 . Then, when the clock signal is input, each bit of the data block stored in the shift register 5 _-1 up to that time is sequentially output from the output terminal 5 _-1O and supplied to the second arithmetic circuit 2 _-2 . At the same time, each bit of the data block input to the data input terminal 4 is logically ORed with each bit of the data blocks stored in the shift register until then,
This is sequentially stored in the shift register _5-1 .

Each of the second arithmetic circuit 2 _{-2 to} the (N-1) th arithmetic circuit 2- _(N-1) has a capacity equal to the block length of the data block to be processed, and has a reset terminal 5
_{-1r, ..., 5 - (N} -1) when a reset signal is input to _r, so far it is initialized to "0" the contents stored therein when the clock signal is input, the input terminal 5 _{- 1i} ,
..., each bit of the data block input to 5- _{(N-1) i} is sequentially _fetched and shifted, and output terminal 5 _-1O ,
... 5- _{(N-1) o} output shift register 5 _-1 , ...
AND gate 7 _-1 , ..., which takes the logical product of 5- _(N-1) and each bit of the data block input to the data input terminal 4 and each bit of the data block output from the arithmetic circuit at the previous stage 7- _(N-1) and these AND gates 7 _-1 ,
..., 7 - the _(N-1) each bit of the data blocks output from the shift register _5-1, ..., 5 - output terminal 5 of the _(N-1)
−1O , ..., 5 _{− (N−1) o is} output to the respective bits of the data block, and the shift register 5 ₋₁ ,
, 5- _(N-1) input terminals 5 _-1i , ..., 5- _{(N-1) i or} OR _gates 6 _-1 , ..., 6- _(N-1) .

When the clock signal is input, each bit of the data blocks stored in the shift register 5 _-1 , ..., 5- _(N-1) up to that point is output to the output terminal 5.
_-1O , ..., 5- _{(N-1) o} are sequentially output and supplied to the arithmetic circuit in the _subsequent stage, and each bit of the data block input to the data input terminal 4 and the arithmetic circuit in the preceding stage are output. The logical product of each bit of the data block is calculated, and each bit obtained by this logical product and the data block of the previous data block stored in the shift register 5 _-1 , ..., 5- _(N-1) The logical sum of each bit is taken and stored in each shift register 5 _-1 , ..., 5- _(N-1) in sequence. The Nth arithmetic circuit 2 _-N has a capacity of the same length as the block length of the data block to be processed, and when the reset signal is input to the reset terminal 5 _-N r, the contents stored until then are stored. Initialized to “0” and when a clock signal is input, shifts while sequentially fetching each bit of the data block input to the input terminal 5- _Ni ,
The shift register 5 _-N output from the output terminal 5 _-No , each bit of the data block input to the data input terminal 4, and the data block output from the (N-1) th arithmetic circuit 2- _(N-1) AND gate 7 _-N taking the logical product with each bit of
And each bit of the data block output from the AND gate 7 _-N and the output terminal 5 of the shift register 5 _-N
-OR gate 6- _N which is logically ORed with each bit of the data block output from _No and is supplied to the input terminal 5- _Ni of the shift register 5- _N .

Then, when the clock signal is input, each bit of the data block stored in the shift register 5- _N up to that time is sequentially output from the output terminal 5- _No , and at the same time, to the data input terminal 4. Each bit of the input data block and the (N-1) th arithmetic circuit 2
-The logical product of each bit of the data block output from _(N-1) is calculated, and each bit obtained by this logical product and each of the data blocks stored in the shift register 5 _-N The logical sum of the bits is stored in the shift register 5 _-N sequentially, and when the last bit is processed, the data stored in the shift register 5 _-N is converted into parallel data which has been subjected to majority decision. Output as.

In this case, (2N-
1) If the data blocks are sequentially input bit by bit, the first arithmetic circuit 2 _{-1 to} the Nth arithmetic circuit 2 _-N are _operated in the same procedure as in the first and second embodiments. The shift register 5 _{-1 to} the N th of the first arithmetic circuit 2 _-1
After the intermediate result of the majority decision operation is stored in the shift register 5 _-N of the arithmetic circuit 2 _-N and the last bit of the last data block is input, for the same reason as in the first and second embodiments described above, In the shift register 5 _-N forming the Nth arithmetic circuit 2 _-N , the data blocks for which the majority logic decision has been made for the (2N-1) data blocks are stored and output as parallel data. in this way,
In this embodiment, 1 input to the data input terminal 4 by the first arithmetic circuit 2 _{-1 to} the Nth arithmetic circuit 2 _-N
The second data block to the (2N-1) th data block are sequentially taken in and shifted, and a majority operation is performed to shift the first data block to the (2N-1) th data block.
After determining whether each bit forming the (N-1) th data block is "1" or "0", and taking the final bit of the (2N-1) th data block to perform determination,
Since the data stored in the Nth operation circuit 2 _-N is output as parallel data which has been subjected to majority logic determination, the majority logic operation circuit and the like are not used as in the above-described embodiments. In addition, it is possible to reduce the number of shift registers by half and enable majority decision processing of data blocks to reduce the circuit scale, power consumption, manufacturing cost, and the like.

FIG. 6 is a block diagram showing a fourth embodiment of the majority decision processing circuit according to the present invention. In this figure, the same parts as those shown in FIG. 1 are designated by the same reference numerals. The majority operation processing circuit 1d shown in this figure differs from the majority operation processing circuit 1 shown in FIG. 1 in that it constitutes a shift register of the first operation circuit 2 _{-1 and} a shift register of the second operation circuit 2 _-2 . Instead of the shift registers 5 _-1 , 5 _-2 with reset function, ordinary shift registers 8 _-1 , 8 _-2
And the output terminals 8 _{-1O of} the shift registers 8 _-1 , 8 _-2 by AND gates 9 _-1 , 9 _-2 ,
This is to take the logical product of each bit of the data block output from 8 _-2 o and the initialization signal and return it to the input side of the corresponding shift register 8 _-1 , 8 _-2 . By doing so, the data input terminal 4 only when the first data block is input, the shift register _28-1 of the first arithmetic circuit 2 _-1, the second arithmetic circuit 2 _-2 shift register _8-2 The initial _value of the shift register 8 _{-1 of} the first arithmetic circuit 2 _-1 and the initial value of the shift register 8 _-2 of the second arithmetic circuit 2 _-2 are undefined only by supplying the clock signal while supplying the initialization signal to However, the bit whose value becomes “0” can be returned to the input side of the shift registers 8 ₋₁ and 8 ₋₂ , whereby the first arithmetic circuit 2 ₋₁ and the second arithmetic circuit 2 _{− 2} is operated in the same manner as in the above-described first embodiment to sequentially fetch and shift the first data block to the third data block input to the data input terminal 4 and perform a majority operation while shifting. The first data block or the third Each bit forming the data block is "1"
Or "0" is determined, the final bit of the third data block is fetched and the determination is performed, and then the second operation circuit 2 _-2
The data stored in can be output as parallel data that has undergone the majority logic determination.

As a result, the above-mentioned first, second and third
Similar to the embodiment, the majority decision processing of the data block is enabled without using the majority logic operation circuit and the number of shift registers is halved, and the circuit scale, power consumption, manufacturing cost, etc. are reduced. Can be made. Further, the shift registers 8 _-1 , 8 _-2 with AND gates used in the fourth embodiment are the majority operation processing circuits other than the majority operation processing circuit 1 shown in the first embodiment, that is, the second embodiment. It may be applied to the majority arithmetic processing circuits 1b and 1c shown in the third embodiment. Even in this case, the majority voting operation processing circuits 1b and 1c shown in the second and third embodiments are operated by a procedure similar to that of the majority voting operation processing circuit 1d shown in the fourth embodiment. , The same effect can be obtained.

[0033]

As described above, according to the present invention, the majority decision processing of a data block is enabled without using a majority decision logical operation circuit or the like, and the number of shift registers is reduced by half. The scale, power consumption, manufacturing cost, etc. can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a majority arithmetic processing circuit according to the present invention.

FIG. 2 is a table showing an operation example of the majority arithmetic processing circuit shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of a majority arithmetic processing circuit according to the present invention.

FIG. 4 is a table showing an operation example of the majority decision processing circuit shown in FIG.

FIG. 5 is a block diagram showing a third embodiment of a majority arithmetic processing circuit according to the present invention.

FIG. 6 is a block diagram showing a fourth embodiment of a majority decision processing circuit according to the present invention.

FIG. 7 is a block diagram showing an example of a conventionally-known majority arithmetic processing circuit.

[Explanation of symbols]

1, 1b, 1c, 1d Majority arithmetic processing circuit 2 _-1 , ..., 2- _N first arithmetic circuit, ..., Nth arithmetic circuit 4 Data input terminal 5 _-1 , ..., 5- _N shift register 5 _-1i , ..., 5 _-Ni input terminal ₅ -1r, ..., 5 _-N r reset terminal 5 _-1O, ..., 5 _-No output terminal 6 _-1, ..., 6 _-N gate 7 _-2, ..., 7 _-N and Gate 8 _-1 , 8 _-2 shift register 8 _-1O , 8 _-2 o Output terminal 9 _-1 , 9 _-2 AND gate

Claims (3)

[Claims] 1. A (2N-1) number of data blocks (where N is an integer greater than 1) having the same content of 1 bit or more input to a data input terminal are taken and these (2N
-1) Each bit forming one data block is "1"
Or a "0" majority decision processing circuit, which has a shift register having the same length as the length of the data block, the data block input to the data input terminal and the shift register in its own circuit. A first arithmetic circuit for taking a logical sum of the data blocks held up to then and holding the logical sum result again in the shift register in its own circuit; and a shift having the same length as the length of the data block. It has a register, and after taking the logical product of the data block input to the data input terminal and the data block held up to then in the shift register in the arithmetic circuit of the previous stage, this logical product result and After taking the logical sum with the previous data blocks held in the shift register in the circuit, the logical sum result is stored in the shift register in the own circuit. Includes a second through N arithmetic circuit for holding, the said first N majority arithmetic processing circuit, characterized in that the data block after the error correction data block held in the shift register arithmetic circuit. 2. The majority arithmetic processing circuit according to claim 1, wherein a shift register with reset is used as each shift register forming the first to Nth arithmetic circuits, and the shift register is input to the data input terminal. Error correction target (2
N-1) A majority operation process characterized by supplying a reset signal to each shift register to reset each shift register before the first data block is input from the N-1) data blocks. circuit. 3. The majority arithmetic processing circuit according to claim 1, wherein a shift register having no reset function is used as each shift register forming the first to Nth arithmetic circuits, and outputs of these shift registers. And an initialization signal are ANDed and returned to the input side of the shift register, and (2N-1) data blocks to be error-corrected which are input to the data input terminal are input. At that time, while the first data block is being input, an initialization signal is input to each of the AND gates to return the data block having the value "0" to the input side of the shift register. .