JPH0927573A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0927573A JPH0927573A JP7177682A JP17768295A JPH0927573A JP H0927573 A JPH0927573 A JP H0927573A JP 7177682 A JP7177682 A JP 7177682A JP 17768295 A JP17768295 A JP 17768295A JP H0927573 A JPH0927573 A JP H0927573A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- resin
- semiconductor chip
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 樹脂パッケージの耐久性，加工性，成形性を
低下させることなく、樹脂の剥離及びクラックによって
封止が破れることを防止し得る半導体装置を提供する。
【解決手段】 ダイパッド３，半導体チップ４，ボンデ
ィングワイヤ５，５，…及びリード６，６，…の一部
は、それらを成形用のキャビティ内の所定位置に配置
し、エポキシ樹脂にフィラ又は可撓性付与剤を添加して
所要の熱膨張係数，弾性率又は粘度を調整したモールド
樹脂を充填・硬化させた第１樹脂層１で封止してある。
硬化した第１樹脂層１は、型抜きした後に前述したキャ
ビティより大きいキャビティ内の所定位置に配置し、第
１樹脂層１より大きい熱膨張係数，弾性率又は粘度とな
るように調整したモールド樹脂を充填・硬化させた第２
樹脂層２で封止してある。
(57) Abstract: Provided is a semiconductor device capable of preventing sealing from being broken by peeling and cracking of a resin without lowering durability, processability and moldability of a resin package. A part of the die pad 3, the semiconductor chip 4, the bonding wires 5, 5, ... And the leads 6, 6, ... Are arranged at predetermined positions in a cavity for molding, and a filler or an epoxy resin is used. It is sealed with a first resin layer 1 which is filled and hardened with a molding resin having a required coefficient of thermal expansion, elastic modulus or viscosity adjusted by adding a flexibility-imparting agent.
The cured first resin layer 1 is placed in a predetermined position in the cavity larger than the above-mentioned cavity after die-cutting, and is adjusted to have a coefficient of thermal expansion, elastic modulus or viscosity larger than that of the first resin layer 1. Second filled and cured
It is sealed with the resin layer 2.
Description
【０００１】[0001]
【発明が属する技術分野】本発明は半導体チップを樹脂
製のパッケージで封止した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is sealed with a resin package.
【０００２】[0002]
【従来の技術】図６は半導体チップを樹脂製のパッケー
ジで封止した従来の半導体装置を示す模式的正断面図で
あり、図中13は平面視が略正方形状のダイパッドであ
る。ダイパッド13の対向する２辺の外側にはそれぞれ、
ダイパッド13から所定距離を隔てて短冊状のリード16，
16，…複数がダイパッド13と同じ高さとなるように、各
辺に沿って所定の間隔で配してある。ダイパッド13上に
は複数の電極が形成された半導体チップ14がダイボンデ
ィングによって固定してあり、半導体チップ14の各電極
とリード16，16，…の一端とはボンディングワイヤ15，
15，…によって接続してある。ダイパッド13，半導体チ
ップ14，ボンディングワイヤ15，15，…及びリード16，
16，…の一端側は、それらを成形用のキャビティ内の所
定位置に配置した後にエポキシ樹脂を充填・硬化させた
パッケージ20で封止してある。パッケージ20の側面から
はリード16，16，…の他端側が突出しており、リード1
6，16，…の突出した部分はその途中から略直角に曲げ
てある。2. Description of the Related Art FIG. 6 is a schematic front sectional view showing a conventional semiconductor device in which a semiconductor chip is sealed with a resin package, and 13 in the figure is a die pad having a substantially square plan view. Outside the two opposite sides of the die pad 13,
Strip-shaped leads 16 separated from the die pad 13 by a predetermined distance,
16, ... Arranged at predetermined intervals along each side so that a plurality of them have the same height as the die pad 13. A semiconductor chip 14 having a plurality of electrodes formed thereon is fixed on the die pad 13 by die bonding. Each electrode of the semiconductor chip 14 and one end of the leads 16, 16, ...
It is connected by 15, ... Die pad 13, semiconductor chip 14, bonding wires 15, 15, ... And leads 16,
One end side of 16, ... Is sealed with a package 20 in which epoxy resin is filled and cured after placing them at a predetermined position in a molding cavity. From the side surface of the package 20, the other ends of the leads 16, 16, ...
The protruding parts of 6, 16, ... Are bent at a substantially right angle from the middle.
【０００３】[0003]
【発明が解決しようとする課題】しかし、従来の半導体
装置にあっては、半導体チップの発熱によって樹脂製の
パッケージが膨張すると、パッケージと半導体チップと
の熱膨張係数、又はパッケージとダイパッドとの熱膨張
係数が異なるため、半導体チップ又はダイパッドから樹
脂が剥離し、そこからクラックが生じてパッケージによ
る封止が破れて半導体チップが劣化するという問題があ
った。そのため、エポキシ樹脂にフィラと呼ばれる添加
剤を混入してパッケージの熱膨張係数を低下させること
によって、又は、エポキシ樹脂に可撓性付与剤を混入し
てパッケージの弾性率を低下させることによって、樹脂
の剥離を防止していた。しかしながら、フィラ又は可撓
性付与剤の添加量を多くするとパッケージの耐久性，加
工性，成形性が低下するため、添加量には限度があり、
熱膨張係数又は弾性率を十分低下させることができず、
樹脂の剥離及びクラックによるパッケージの封止破壊を
十分に防止することができないという問題があった。However, in the conventional semiconductor device, when the resin package expands due to the heat generation of the semiconductor chip, the coefficient of thermal expansion between the package and the semiconductor chip or the heat between the package and the die pad is increased. Since the expansion coefficients are different, the resin is peeled off from the semiconductor chip or the die pad, and cracks are generated from the resin to break the sealing by the package and deteriorate the semiconductor chip. Therefore, by adding an additive called filler to the epoxy resin to reduce the thermal expansion coefficient of the package, or by adding a flexibility-imparting agent to the epoxy resin to reduce the elastic modulus of the package, Was prevented from peeling. However, if the amount of filler or flexibility-imparting agent added is increased, the durability, workability, and moldability of the package will deteriorate, so there is a limit to the amount added,
The thermal expansion coefficient or elastic modulus cannot be lowered sufficiently,
There is a problem that it is not possible to sufficiently prevent the package from being broken due to peeling and cracking of the resin.
【０００４】本発明はかかる事情に基づいてなされたも
のであって、その目的とするところは外側の樹脂層より
内側の樹脂層が熱膨張率，弾性率又は粘度を低くしてあ
る複数の樹脂層で半導体チップを包囲することによっ
て、パッケージの耐久性，加工性，成形性を低下させる
ことなく、樹脂の剥離及びクラックによって封止が破れ
ることを防止し得る半導体装置を提供することにある。The present invention has been made in view of the above circumstances, and an object thereof is to provide a plurality of resins in which the inner resin layer has a lower coefficient of thermal expansion, elastic modulus or viscosity than the outer resin layer. An object of the present invention is to provide a semiconductor device in which the semiconductor chip can be prevented from being broken by peeling and cracking of the resin without lowering the durability, workability, and moldability of the package by surrounding the semiconductor chip with the layer.
【０００５】[0005]
【課題を解決するための手段】第１発明に係る半導体装
置は、半導体チップを樹脂製のパッケージで封止してあ
る半導体装置において、前記パッケージは、前記半導体
チップを包囲する複数の樹脂層を備えており、内側の樹
脂層は外側の樹脂層より膨張率を低くしてあることを特
徴とする。A semiconductor device according to a first invention is a semiconductor device in which a semiconductor chip is sealed with a resin package, wherein the package includes a plurality of resin layers surrounding the semiconductor chip. The inner resin layer has a lower expansion coefficient than the outer resin layer.
【０００６】第２発明に係る半導体装置は、半導体チッ
プを樹脂製のパッケージで封止してある半導体装置にお
いて、前記パッケージは、前記半導体チップを包囲する
複数の樹脂層を備えており、内側の樹脂層は外側の樹脂
層より弾性率を低くしてあることを特徴とする。A semiconductor device according to a second aspect of the present invention is a semiconductor device in which a semiconductor chip is sealed with a resin package, and the package includes a plurality of resin layers surrounding the semiconductor chip. The resin layer has a lower elastic modulus than the outer resin layer.
【０００７】第３発明に係る半導体装置は、半導体チッ
プを樹脂製のパッケージで封止してある半導体装置にお
いて、前記パッケージは、前記半導体チップを包囲する
複数の樹脂層を備えており、内側の樹脂層は外側の樹脂
層より粘度を低くしてあることを特徴とする。A semiconductor device according to a third aspect of the present invention is a semiconductor device in which a semiconductor chip is sealed with a resin package, and the package includes a plurality of resin layers surrounding the semiconductor chip. The resin layer is characterized by having a lower viscosity than the outer resin layer.
【０００８】第４発明に係る半導体装置は、第１，第２
又は第３発明において、前記半導体チップの近傍には放
熱部材が設けてあることを特徴とする。A semiconductor device according to a fourth aspect of the present invention is the first and second aspects.
Alternatively, in the third invention, a heat dissipation member is provided in the vicinity of the semiconductor chip.
【０００９】第５発明に係る半導体装置は、第４発明に
おいて、前記放熱部材には熱導伝部材の一端が接続して
おり、該熱導伝部材の他端はパッケージから突出してい
ることを特徴とする。According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, one end of a heat conducting member is connected to the heat dissipation member, and the other end of the heat conducting member projects from the package. Characterize.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施例の形態を、
図面に基づいて具体的に説明する。図１は本発明に係る
半導体装置を示す模式的正断面図であり、図中３は平面
視が略正方形状のダイパッドである。ダイパッド３は正
断面視が両縁部にテーパが形成してある矩形状の樹脂製
のパッケージ10の略中央に設けてあり、ダイパッド３の
対向する２辺の外側にはそれぞれ、ダイパッド３から所
定距離を隔てて複数のリード６，６，…が配してある。
各リード６，６，…はダイパッド３と同じ高さとなるよ
うに、両辺に沿って所定の間隔で配してあり、各リード
６，６，…は中央付近から略直角下方に曲げてある。ダ
イパッド３上には複数の電極が形成された半導体チップ
４がダイボンディングによって固定してあり、半導体チ
ップ４の各電極とリード６，６，…とはボンディングワ
イヤ５，５，…によってそれぞれ接続してある。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
A specific description will be given based on the drawings. FIG. 1 is a schematic front cross-sectional view showing a semiconductor device according to the present invention. In the figure, 3 is a die pad having a substantially square shape in plan view. The die pad 3 is provided substantially in the center of a rectangular resin package 10 having a taper formed on both edges in a front sectional view. A plurality of leads 6, 6, ... Are arranged at a distance.
The leads 6, 6, ... Are arranged at predetermined intervals along both sides so that they have the same height as the die pad 3, and the leads 6, 6 ,. A semiconductor chip 4 having a plurality of electrodes formed thereon is fixed on the die pad 3 by die bonding, and each electrode of the semiconductor chip 4 and the leads 6, 6, ... Are connected by bonding wires 5, 5 ,. There is.
【００１１】ダイパッド３，半導体チップ４，ボンディ
ングワイヤ５，５，…及びリード６，６，…の一部は、
それらを成形用のキャビティ内の所定位置に配置し、エ
ポキシ樹脂にフィラ又は可撓性付与剤を添加して所要の
熱膨張係数，弾性率又は粘度を調整したモールド樹脂を
充填・硬化させた第１樹脂層１で封止してある。硬化し
た第１樹脂層１は、型抜きした後に前述したキャビティ
より大きいキャビティ内の所定位置に配置し、第１樹脂
層１より大きい熱膨張係数，弾性率又は粘度となるよう
に調整したモールド樹脂を充填・硬化させた第２樹脂層
２で封止してある。A part of the die pad 3, the semiconductor chip 4, the bonding wires 5, 5, ... And the leads 6, 6 ,.
They are placed in a predetermined position in the molding cavity, and a filler or flexibility-imparting agent is added to the epoxy resin to fill and cure the mold resin with the required coefficient of thermal expansion, elastic modulus or viscosity adjusted. It is sealed with one resin layer 1. The cured first resin layer 1 is placed in a predetermined position in the cavity larger than the above-mentioned cavity after die-cutting, and is adjusted to have a coefficient of thermal expansion, elastic modulus or viscosity larger than that of the first resin layer 1. Is sealed with the second resin layer 2 filled and cured.
【００１２】前述した第１樹脂層１は、フィラとして溶
融性シリカを９０〜８５重量％添加したモールド樹脂を
用いて、熱膨張係数が６〜１０×１０-6／℃となるよう
にしてある。これによって、第１樹脂層１の熱膨張係数
は半導体チップ４の熱膨張係数，２．６〜３．６×１０
-6／℃に近く、半導体チップ４の発熱によっても第１樹
脂層１の半導体チップ４からの剥離及びクラックの発生
が防止される。The above-mentioned first resin layer 1 is made of a mold resin containing 90 to 85% by weight of fusible silica as a filler and has a coefficient of thermal expansion of 6 to 10 × 10 -6 / ° C. . Accordingly, the coefficient of thermal expansion of the first resin layer 1 is equal to the coefficient of thermal expansion of the semiconductor chip 4, which is 2.6 to 3.6 × 10.
Since the temperature is close to −6 / ° C., the peeling and cracking of the first resin layer 1 from the semiconductor chip 4 are prevented even when the semiconductor chip 4 generates heat.
【００１３】また、熱膨張係数を調整する代わりに、第
１樹脂層１は、可撓性付与剤としてシリコンを１０〜５
重量％添加して弾性率を１０００〜１５００ｋｇｆ／ｍ
ｍ2にしてもよい。これによって、半導体チップ４の膨
張・収縮を第１樹脂１の弾性によって吸収し、第１樹脂
層１の半導体チップ４からの剥離及びクラックの発生が
防止される。Further, instead of adjusting the coefficient of thermal expansion, the first resin layer 1 contains 10 to 5 silicon as a flexibility-imparting agent.
Elasticity of 1000 to 1500 kgf / m
It may be m 2 . As a result, the expansion and contraction of the semiconductor chip 4 are absorbed by the elasticity of the first resin 1, and the peeling and cracking of the first resin layer 1 from the semiconductor chip 4 are prevented.
【００１４】一方、半導体チップ４の寸法が小さい場合
は半導体チップ４の発熱による影響が小さいため、熱膨
張係数を調整する代わりに、第１樹脂層１は、溶融性シ
リカを４０〜７０重量％添加して粘度を２０〜１００ｐ
にする。これによって、加工・成形性を損なうことな
く、半導体チップ４の膨張・収縮を第１樹脂１の粘性に
よって吸収し、第１樹脂層１の半導体チップ４からの剥
離及びクラックの発生が防止される。On the other hand, when the size of the semiconductor chip 4 is small, the influence of heat generation of the semiconductor chip 4 is small. Therefore, instead of adjusting the thermal expansion coefficient, the first resin layer 1 contains 40 to 70% by weight of fusible silica. Add viscosity to 20-100p
To As a result, the expansion / contraction of the semiconductor chip 4 is absorbed by the viscosity of the first resin 1 without impairing the processability / formability, and peeling and cracking of the first resin layer 1 from the semiconductor chip 4 are prevented. .
【００１５】第２樹脂層２は、前述した如く第１樹脂層
１より大きい熱膨張係数，弾性率又は粘度となるように
調整してある。即ち、第１樹脂層１が熱膨張係数を調整
してある場合、第２樹脂層２は溶融性シリカを８５〜７
０重量％添加して熱膨張係数を１０〜２２×１０-6／℃
にする。また、第１樹脂層１が弾性率を調整してある場
合、第２樹脂層２はシリコンを５〜１重量％添加して弾
性率を１５００〜２０００ｋｇｆ／ｍｍ2 にする。更
に、第１樹脂層１が粘度を調整してある場合、第２樹脂
層２は溶融性シリカを７０〜８５重量％添加して粘度を
１００〜７００ｐにする。The second resin layer 2 is adjusted so as to have a coefficient of thermal expansion, an elastic modulus or a viscosity larger than that of the first resin layer 1 as described above. That is, when the first resin layer 1 has a coefficient of thermal expansion adjusted, the second resin layer 2 contains fusible silica of 85 to 7
Add 0% by weight to obtain a coefficient of thermal expansion of 10-22 × 10 -6 / °
To In addition, when the elastic modulus of the first resin layer 1 is adjusted, the second resin layer 2 has an elastic modulus of 1500 to 2000 kgf / mm 2 by adding 5 to 1% by weight of silicon. Further, when the viscosity of the first resin layer 1 is adjusted, the second resin layer 2 has a viscosity of 100 to 700 p by adding 70 to 85% by weight of fusible silica.
【００１６】これによって、第１樹脂層１にクラックが
発生した場合であっても、該クラックは第１樹脂層１と
第２樹脂層２との境界で止まり、パッケージ10による半
導体チップ４の封止は破れない。一方、前述した第２樹
脂層２は前述した如き組成であるためその耐久性が高
く、また加工・成形性も良好である。As a result, even if a crack occurs in the first resin layer 1, the crack stops at the boundary between the first resin layer 1 and the second resin layer 2, and the package 10 seals the semiconductor chip 4. You can't break it. On the other hand, since the above-mentioned second resin layer 2 has the composition as described above, its durability is high and its workability and moldability are also good.
【００１７】図２は本発明に係る半導体装置における封
止破壊の防止を説明する説明図である。第１樹脂層１の
熱膨張係数はダイパッド３の熱膨張係数に近いため、半
導体チップが発熱した場合であっても、ダイパッド３か
ら第１樹脂層１が剥離することは防止されるが、例えば
半導体チップ４が過大に発熱した場合は、ダイパッド３
の熱膨張係数と第１樹脂層１の熱膨張係数との僅かな差
によって剥離部Ｅが形成される虞がある。FIG. 2 is an explanatory view for explaining prevention of sealing breakage in the semiconductor device according to the present invention. Since the coefficient of thermal expansion of the first resin layer 1 is close to the coefficient of thermal expansion of the die pad 3, peeling of the first resin layer 1 from the die pad 3 is prevented even when the semiconductor chip generates heat. If the semiconductor chip 4 generates excessive heat, the die pad 3
The peeled portion E may be formed due to a slight difference between the coefficient of thermal expansion of the first resin layer 1 and the coefficient of thermal expansion of the first resin layer 1.
【００１８】この剥離が発生すると、膨張・収縮の繰り
返しによって剥離部Ｅにおける僅かな割れ目からクラッ
クＫが成長するが、このクラックＫは第２樹脂層２に達
するとそれ以上成長し得ない。これは、第１樹脂層１と
第２樹脂層２との間でクラックＫによる応力が分散され
るからである。When this peeling occurs, a crack K grows from a slight crack in the peeled portion E due to repeated expansion and contraction, but when the crack K reaches the second resin layer 2, it cannot grow any more. This is because the stress due to the crack K is dispersed between the first resin layer 1 and the second resin layer 2.
【００１９】図３は本発明の他の実施例の形態を示す模
式的正断面図であり、熱を均一に拡散するようになして
ある。半導体チップ４はダイパッド３の下面に固定して
あり、ダイパッド３の上面には該ダイパッド３の寸法よ
り少し大きい寸法である銅製の放熱板７が固定してあ
る。ダイパッド３，半導体チップ４，放熱板７，ボンデ
ィングワイヤ５，５，…及びリード６，６，…の一端側
は第１樹脂層１によって包囲されており、該第１樹脂層
１は第２樹脂層２によって包囲されている。そして、第
１樹脂層１及び第２樹脂層２は熱膨張係数，弾性率又は
粘度が前述した如く調整してある。なお、第１樹脂層１
の熱膨張係数を調整する場合、放熱板７の熱膨張係数も
考慮して行う。FIG. 3 is a schematic front sectional view showing another embodiment of the present invention, in which heat is uniformly diffused. The semiconductor chip 4 is fixed to the lower surface of the die pad 3, and the upper surface of the die pad 3 is fixed with a radiator plate 7 made of copper, which is slightly larger than the dimension of the die pad 3. One end sides of the die pad 3, the semiconductor chip 4, the heat dissipation plate 7, the bonding wires 5, 5, ... And the leads 6, 6, ... Are surrounded by the first resin layer 1, and the first resin layer 1 is the second resin layer. Surrounded by layer 2. The first resin layer 1 and the second resin layer 2 are adjusted in the coefficient of thermal expansion, elastic modulus or viscosity as described above. The first resin layer 1
When adjusting the coefficient of thermal expansion of, the coefficient of thermal expansion of the heat sink 7 is also taken into consideration.
【００２０】このような半導体装置にあっては、半導体
チップ４の熱を放熱板７に吸収しそれを第１樹脂層１へ
導伝させるため、半導体チップ４の動作特性が保証され
る。このとき、第１樹脂層１及び第２樹脂層２の熱膨張
係数，弾性率又は粘度は前述した如く調整してあるた
め、第１樹脂層１の放熱板７からの剥離及びクラックの
発生が防止される。これによって、従来より放熱効率が
高い放熱板７を用いることが可能となり、高集積されて
発熱量が多い半導体チップに対しても、比較的安価な樹
脂製のパッケージを用いてその動作特性を保証すること
ができる。In such a semiconductor device, the heat of the semiconductor chip 4 is absorbed by the heat dissipation plate 7 and conducted to the first resin layer 1, so that the operating characteristics of the semiconductor chip 4 are guaranteed. At this time, since the thermal expansion coefficient, the elastic modulus or the viscosity of the first resin layer 1 and the second resin layer 2 are adjusted as described above, the peeling of the first resin layer 1 from the heat sink 7 and the occurrence of cracks are prevented. To be prevented. As a result, it becomes possible to use the heat dissipation plate 7 having a higher heat dissipation efficiency than the conventional one, and the operation characteristics of the semiconductor chip, which is highly integrated and generates a large amount of heat, are guaranteed by using a relatively inexpensive resin package. can do.
【００２１】図４及び図５は本発明の更に他の実施例の
形態を示す模式的正断面図であり、図４は放熱用のフィ
ンを設けた場合を、また、図５はフィンを取付け可能に
なした場合をそれぞれ示している。図４の如く、放熱板
７上には平板状のフィン８，８，８が互いに所定距離を
隔てて放熱板７と直角に設けてあり、各フィン８，８，
８は第１樹脂層１及び第２樹脂層２を貫通してパッケー
ジ10の外に突出させてある。FIGS. 4 and 5 are schematic front sectional views showing still another embodiment of the present invention. FIG. 4 shows a case where a fin for heat dissipation is provided, and FIG. 5 shows a case where the fin is attached. Each shows the case where it becomes possible. As shown in FIG. 4, plate-shaped fins 8, 8 and 8 are provided on the heat dissipation plate 7 at right angles to the heat dissipation plate 7 with a predetermined distance from each other.
The numeral 8 penetrates the first resin layer 1 and the second resin layer 2 and is projected to the outside of the package 10.
【００２２】また、図５の如く、放熱板７上には熱伝導
率が高いフィン支持棒９，９，９が互いに所定距離を隔
てて起立して設けてあり、各フィン支持棒９，９，９は
第１樹脂層１及び第２樹脂層２を貫通してパッケージ10
の外に突出させてある。フィン支持棒９，９，９の突出
した部分には螺合部9a，9a，9aがそれぞれ形成してあ
り、該螺合部9a，9a，9aにフィン（図示せず）を螺着す
ることによって放熱効率を向上させる。Further, as shown in FIG. 5, fin supporting rods 9, 9, 9 having a high thermal conductivity are provided on the heat dissipation plate 7 so as to be upright at a predetermined distance from each other. , 9 penetrate the first resin layer 1 and the second resin layer 2 to form the package 10
It is projected outside. Threaded portions 9a, 9a, 9a are formed on the protruding portions of the fin support bars 9, 9, 9 respectively, and a fin (not shown) may be screwed onto the threaded portions 9a, 9a, 9a. Improves heat dissipation efficiency.
【００２３】このような半導体装置にあっては、フィン
８，８，８のパッケージ10から突出した部分，又はフィ
ン支持棒９，９，９の螺合部9a，9a，9aが急冷されるた
め、第２樹脂層２がフィン８，８，８又はフィン支持棒
９，９，９から剥離してクラックが発生する虞がある
が、該クラックは第２樹脂層２と第１樹脂層１との境界
で止まり、第１樹脂層１の内部まで進入しない。In such a semiconductor device, the portions of the fins 8, 8, 8 protruding from the package 10 or the screwed portions 9a, 9a, 9a of the fin support rods 9, 9, 9 are rapidly cooled. , The second resin layer 2 may be peeled off from the fins 8, 8, 8 or the fin support rods 9, 9, 9 to generate a crack. The crack is generated in the second resin layer 2 and the first resin layer 1. Of the first resin layer 1 and does not enter the inside of the first resin layer 1.
【００２４】なお、上述した実施例の形態にあっては第
１樹脂層及び第２樹脂層の２層構造にしてあるが、本発
明はこれに限らず、３層以上の多層構造にしてもよい。
この場合、外側の樹脂層より内側の樹脂層の方が熱膨張
率，弾性率又は粘度を低くする。これによって、クラッ
クによってパッケージの封止が破れることを更に防止す
ることができる。In the embodiment described above, the two-layer structure of the first resin layer and the second resin layer is used, but the present invention is not limited to this, and a multi-layer structure of three or more layers is also possible. Good.
In this case, the inner resin layer has a lower thermal expansion coefficient, elastic modulus or viscosity than the outer resin layer. This can further prevent the package from being broken due to cracks.
【００２５】[0025]
【発明の効果】以上詳述した如く第１〜第３発明に係る
半導体装置にあっては、樹脂の剥離及びクラックによっ
て樹脂製のパッケージの封止が破れることが防止される
ため、半導体装置の信頼性及び耐久性が向上する。As described above in detail, in the semiconductor device according to the first to third inventions, it is possible to prevent the resin package from being broken by the peeling and cracking of the resin. Reliability and durability are improved.
【００２６】第４及び第５発明に係る半導体装置にあっ
ては、従来より放熱効率が高い放熱板を封入し、また樹
脂製のパッケージの外に突出するフィン等を設けて放熱
効率を更に向上させても、樹脂製のパッケージによる封
止が破れることが防止される。このため、より高集積さ
れて発熱量が多い半導体チップに対しても樹脂製のパッ
ケージで対応することができ、低いコストで半導体装置
を製造することができる等、本発明は優れた効果を奏す
る。In the semiconductor device according to the fourth and fifth aspects of the invention, a heat dissipation plate having a higher heat dissipation efficiency than before is enclosed, and fins protruding outside the resin package are provided to further improve the heat dissipation efficiency. Even if it does, it is possible to prevent the sealing by the resin package from being broken. Therefore, the present invention has excellent effects such that a semiconductor package that is highly integrated and generates a large amount of heat can be handled with a resin package, and a semiconductor device can be manufactured at low cost. .
【図１】 本発明に係る半導体装置を示す模式的正断面
図である。FIG. 1 is a schematic front sectional view showing a semiconductor device according to the present invention.
【図２】 本発明に係る半導体装置における封止破壊の
防止を説明する説明図である。FIG. 2 is an explanatory diagram illustrating prevention of sealing destruction in the semiconductor device according to the present invention.
【図３】 本発明の他の実施例の形態を示す模式的正断
面図である。FIG. 3 is a schematic front sectional view showing a form of another embodiment of the present invention.
【図４】 本発明の更に他の実施例の形態を示す模式的
正断面図である。FIG. 4 is a schematic front sectional view showing a form of still another embodiment of the present invention.
【図５】 本発明の更に他の実施例の形態を示す模式的
正断面図である。FIG. 5 is a schematic front sectional view showing a form of still another embodiment of the present invention.
【図６】 半導体チップを樹脂製のパッケージで封止し
た従来の半導体装置を示す模式的正断面図である。FIG. 6 is a schematic front sectional view showing a conventional semiconductor device in which a semiconductor chip is sealed with a resin package.
１ 第１樹脂層、２ 第２樹脂層、３ ダイパッド、４
半導体チップ、６ リード、７ 放熱板、８ フィ
ン、９ フィン支持棒。1 1st resin layer, 2 2nd resin layer, 3 die pad, 4
Semiconductor chip, 6 leads, 7 heat sink, 8 fins, 9 fin support rod.
Claims (5)
止してある半導体装置において、 前記パッケージは、前記半導体チップを包囲する複数の
樹脂層を備えており、内側の樹脂層は外側の樹脂層より
膨張率を低くしてあることを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip is sealed with a resin package, wherein the package includes a plurality of resin layers surrounding the semiconductor chip, and an inner resin layer is an outer resin layer. A semiconductor device having a lower expansion coefficient.
止してある半導体装置において、 前記パッケージは、前記半導体チップを包囲する複数の
樹脂層を備えており、内側の樹脂層は外側の樹脂層より
弾性率を低くしてあることを特徴とする半導体装置。2. A semiconductor device in which a semiconductor chip is sealed with a resin package, wherein the package includes a plurality of resin layers surrounding the semiconductor chip, and an inner resin layer is an outer resin layer. A semiconductor device having a lower elastic modulus.
止してある半導体装置において、 前記パッケージは、前記半導体チップを包囲する複数の
樹脂層を備えており、内側の樹脂層は外側の樹脂層より
粘度を低くしてあることを特徴とする半導体装置。3. A semiconductor device in which a semiconductor chip is sealed with a resin package, wherein the package includes a plurality of resin layers surrounding the semiconductor chip, and an inner resin layer is an outer resin layer. A semiconductor device having a lower viscosity.
設けてある請求項１，請求項２又は請求項３記載の半導
体装置。4. The semiconductor device according to claim 1, wherein a heat dissipation member is provided near the semiconductor chip.
続しており、該熱導伝部材の他端はパッケージから突出
している請求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein one end of a heat transfer member is connected to the heat dissipation member, and the other end of the heat transfer member projects from the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7177682A JPH0927573A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7177682A JPH0927573A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0927573A true JPH0927573A (en) | 1997-01-28 |
Family
ID=16035269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7177682A Pending JPH0927573A (en) | 1995-07-13 | 1995-07-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0927573A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006245989A (en) * | 2005-03-03 | 2006-09-14 | Matsushita Electric Ind Co Ltd | Surface acoustic wave device |
| US7170188B2 (en) | 2004-06-30 | 2007-01-30 | Intel Corporation | Package stress management |
| US7425727B2 (en) | 2004-09-16 | 2008-09-16 | Sharp Kabushiki Kaisha | Optical semiconductor device, method for fabricating the same, lead frame and electronic equipment |
| US7435625B2 (en) * | 2005-10-24 | 2008-10-14 | Freescale Semiconductor, Inc. | Semiconductor device with reduced package cross-talk and loss |
| JP2011014863A (en) * | 2009-06-03 | 2011-01-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP2011210759A (en) * | 2010-03-29 | 2011-10-20 | Casio Computer Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2015095655A (en) * | 2013-11-14 | 2015-05-18 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Semiconductor package and manufacturing method thereof |
| WO2016074176A1 (en) * | 2014-11-12 | 2016-05-19 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| CN106711098A (en) * | 2016-12-10 | 2017-05-24 | 无锡中微高科电子有限公司 | IC plastic packaging structure and production method thereof |
-
1995
- 1995-07-13 JP JP7177682A patent/JPH0927573A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7170188B2 (en) | 2004-06-30 | 2007-01-30 | Intel Corporation | Package stress management |
| US7179689B2 (en) * | 2004-06-30 | 2007-02-20 | Intel Corporation | Package stress management |
| US7425727B2 (en) | 2004-09-16 | 2008-09-16 | Sharp Kabushiki Kaisha | Optical semiconductor device, method for fabricating the same, lead frame and electronic equipment |
| JP2006245989A (en) * | 2005-03-03 | 2006-09-14 | Matsushita Electric Ind Co Ltd | Surface acoustic wave device |
| US7435625B2 (en) * | 2005-10-24 | 2008-10-14 | Freescale Semiconductor, Inc. | Semiconductor device with reduced package cross-talk and loss |
| JP2011014863A (en) * | 2009-06-03 | 2011-01-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP2011210759A (en) * | 2010-03-29 | 2011-10-20 | Casio Computer Co Ltd | Semiconductor device and method of manufacturing the same |
| JP2015095655A (en) * | 2013-11-14 | 2015-05-18 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Semiconductor package and manufacturing method thereof |
| WO2016074176A1 (en) * | 2014-11-12 | 2016-05-19 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| US9778688B2 (en) | 2014-11-12 | 2017-10-03 | Intel Corporation | Flexible system-in-package solutions for wearable devices |
| CN106711098A (en) * | 2016-12-10 | 2017-05-24 | 无锡中微高科电子有限公司 | IC plastic packaging structure and production method thereof |
| CN106711098B (en) * | 2016-12-10 | 2019-04-12 | 无锡中微高科电子有限公司 | IC plastic capsulation structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7671453B2 (en) | Semiconductor device and method for producing the same | |
| US6967126B2 (en) | Method for manufacturing plastic ball grid array with integral heatsink | |
| JP2509607B2 (en) | Resin-sealed semiconductor device | |
| KR101398404B1 (en) | Plastic overmolded packages with mechanically decoupled lid attach attachment | |
| KR100726902B1 (en) | Circuit device and manufacturing method thereof | |
| JP4385324B2 (en) | Semiconductor module and manufacturing method thereof | |
| US6538321B2 (en) | Heat sink with collapse structure and semiconductor package with heat sink | |
| JPH0927573A (en) | Semiconductor device | |
| KR20080015724A (en) | Plastic Overmolded Packages with Molded Lead Attachment | |
| JP5098301B2 (en) | Power semiconductor device | |
| JP3568402B2 (en) | Semiconductor device | |
| JP2958380B2 (en) | Semiconductor device | |
| JPS5879739A (en) | Sheath for semiconductor | |
| JP2007027261A (en) | Power module | |
| JPH1126634A (en) | Semiconductor device | |
| JP3147157B2 (en) | Electronic circuit device including semiconductor element | |
| JPH0334863B2 (en) | ||
| JP2710207B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0476944A (en) | Heat radiating structure of semiconductor device and mounting method for same | |
| CN120977954A (en) | Power semiconductor module device and manufacturing method thereof | |
| KR100362225B1 (en) | electronic semiconductor module | |
| JPH11317491A (en) | Semiconductor device | |
| JPH02202042A (en) | Resin-sealed semiconductor device | |
| JPH0682763B2 (en) | Semiconductor device | |
| JPH07106469A (en) | Semiconductor device and manufacturing method thereof |