JPH0927800A - Synchronization circuit and synchronization device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To prevent the continuous pull-in of pseudo synchronization and improve the reliability of pull-in of synchronization. SOLUTION: The synchronization circuit 1 ₂ is based on an error detection signal when an error of a certain level or more occurs in an error correction circuit _2.
In begins a new synchronization acquisition by releasing the I synchronization retracted, or on the basis of the synchronization acquisition impossible signal indicating that no retraction synchronization from the synchronization circuit 1 ₀ in the subsequent stage, the previous stage of the synchronization circuit 1 ₂ Then, the pulled-in synchronization is released and a new synchronization acquisition is started.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention recognizes the beginning of data (or a specified position) so that a receiver can correctly demodulate transmitted data in communication such as video, audio, and data, or broadcasting. The present invention relates to a synchronizing circuit and a synchronizing device for doing so.

[0002]

2. Description of the Related Art In data communication or the like, in order to accurately receive data, a synchronization pattern is captured, synchronization is pulled in, and then an error in the data generated in a transmission line is detected and error correction is performed. There is something I did.

[0003] Figure 10 is a diagram showing such a conventional configuration, in the figure, 1 ₀ is a synchronization circuit which is given the digital data from the demodulation unit (not shown) of the previous stage, 2
Is an error correction circuit that detects and corrects an error in the data generated on the transmission path.

[0004] synchronize draw synchronous circuit 1 ₀ includes a synchronization pattern detection unit 3 for detecting a predetermined synchronization pattern contained in the data, the period generating unit for generating a capture cycle of a fixed period in response to the detection timing of the synchronization pattern 4 _0, and the forward protection unit 5 for counting the number of synchronization patterns that are captured by the capturing cycle, a rear protection portion 6 for counting the number of times the at capturing cycle synchronization pattern has not been captured, the pull or synchronous release and a synchronization establishing unit 7 ₀ for controlling.

The error correction circuit 2 detects and corrects an error and outputs it to a signal processing unit (not shown) in a subsequent stage.
And an error detection signal output section 9 for outputting an error detection signal indicating that an error has occurred above a certain level to the signal processing section.

[0006] Figure 11 is a block diagram showing an example of a cycle generator 4 ₀ in FIG.

[0007] In the figure, 10 ₀ holds the acquisition period of the synchronization pattern, a periodic hold-abandonment unit to give up, 11
Based on the output of the period holding and abandonment portion 10 _0, the period generating unit for generating a capture cycle of the synchronizing pattern in response to the detection timing of the synchronization pattern. Cycle holding / abandoning unit 10 ₀
The synchronous circuit 1 ₀ various internal signals, i.e., the synchronization pattern detection unit 3, by utilizing the output signals of the front protective portion 5 and the backward protection unit 6, holds or abandon the capture period of the synchronization pattern. In the period generating unit 11 generates the acquisition period of the synchronization pattern based on a signal from the periodic holding and abandonment unit 10 _0.

Namely, the period generating unit 4 ₀ in response to the detection timing of the synchronization pattern from the synchronization pattern detection unit 3 generates a capturing period of a constant period, the front protection unit 5, the synchronization pattern in the capture cycle When the acquisition is interrupted or when the rear protection unit 6 cannot acquire the synchronization pattern a certain number of times, the acquisition cycle is abandoned and the acquisition cycle based on a new detection timing is generated.

Next, the operation will be described.

First, when the sync pattern detector 3 detects a sync pattern, the cycle generator 4 ₀ is based on the timing.
Then, the acquisition period of the synchronization pattern is generated as described above. In forward protection unit 5, it counts the number of times the synchronization pattern is successively capturing with the capture cycle generated by the cycle generation unit 4 _0. After a certain number of times the synchronization pattern is captured, the front protection unit 5 sends a signal to the synchronization establishing unit 7 _0, performs synchronization pull in synchronization establishing unit 7 ₀ (synchronization establishment).

[0011] After the synchronization has been retracted, the rear protection portion 6, when counting the number of times the synchronization pattern is not captured at the capture cycle generated by the cycle generation unit 4 ₀ not fixed number captured, the synchronization establishing unit 7 ₀ sends a signal to release the synchronization the synchronization establishing unit 7 _0.

[0012] or interrupted acquisition of the synchronization pattern in forward protection unit 5, when the predetermined number of times the synchronization pattern in the rear protection portion 6 can not be captured, the cycle generator 4 _0, re-generation of the capture period of the synchronization pattern.

[0013] In the error correction circuit 2 performs detection and correction of error in the data sent from the synchronizing circuit 1 _0.

[0014]

However, in such a conventional example, since the synchronization is pulled in or released only on the basis of the signal inside the synchronization circuit, the pseudo synchronization pattern (the same as the normal synchronization pattern is erroneously detected). A pattern,
Even if you pull in a pattern that is not in the regular position,
Sometimes it was impossible to distinguish from the correct synchronization pattern, and synchronization was sometimes pulled in at the wrong position.

Further, in the case of data having a plurality of synchronization patterns and in which the synchronization patterns appear in the same cycle, for example, in packet synchronization and frame synchronization in satellite communication etc., as will be described later, the forward protection unit is used. When counting the number of times the synchronization pattern is captured with, even if a certain synchronization pattern is being counted, it is not possible to efficiently count the synchronization pattern because there are other synchronization patterns in between, and it takes time to pull in synchronization. It may take some time or it may be difficult to pull in the synchronization.

FIG. 12 is a time chart of data in which a plurality of such synchronization patterns appear in the same cycle.

In this example, after the synchronization pattern 1 has been repeated twice, the data that the synchronization pattern 2 different from the synchronization pattern 1 occurs once is periodically repeated. Note that, in FIG. 12, * indicates a pseudo synchronization pattern.

In the case of such data, in the front protection section 5, under the condition that the synchronization is pulled when the synchronization pattern 1 is captured twice consecutively, the second synchronization of the synchronization pattern 1 which occurs twice consecutively. When the synchronization acquisition is started from the pattern 1, the synchronization cannot be acquired because the synchronization pattern 2 comes after the synchronization pattern 1 even though the data is correctly received, and the acquisition period of the synchronization pattern is abandoned. After that, when a pseudo synchronization pattern 1 that is the same pattern as the synchronization pattern 1 occurs, the synchronization acquisition is not performed because synchronization acquisition is performed based on the pseudo synchronization pattern 1, and the acquisition cycle of the synchronization pattern is abandoned again. The same operation as described above is repeated, and the synchronization acquisition cannot be performed.

The present invention has been made in view of the above-mentioned technical problems, and prevents the synchronization from being continuously pulled in at an erroneous position. Further, even if the data has a plurality of synchronization patterns, The purpose is to be able to quickly pull in synchronization in the correct position.

[0020]

In order to achieve the above-mentioned object, the present invention is configured as follows.

That is, the synchronizing apparatus according to the first aspect comprises a synchronizing circuit for detecting a synchronizing pattern and pulling in synchronization, and an error correction circuit for detecting an error in data generated in a transmission line, The circuit cancels the pulled-in synchronization based on the error detection signal from the error correction circuit.

According to a second aspect of the present invention, there is provided a synchronization device, which is provided in each of an error correction circuit for detecting an error in data generated on a transmission line, a front stage and a rear stage of the error correction circuit, and detects a synchronization pattern. And a plurality of synchronizing circuits for pulling in the synchronization, the synchronizing circuit on the front side of the error correction circuit cancels the pulled-in synchronization based on a signal from the synchronizing circuit on the rear side indicating that the synchronization cannot be pulled. To do.

According to a fourth aspect of the present invention, in the synchronizing circuit which pulls in the synchronization by capturing the synchronization pattern a certain number of times in the synchronization capturing period, the synchronization capturing period is maintained for a certain period without capturing the synchronization pattern. To hold.

According to the synchronizer of the first aspect, when synchronization is pulled in by the pseudo synchronization pattern, many errors occur in the error correction circuit and the error detection signal is given to the synchronization circuit. The synchronization will be released, which will prevent the synchronization from being continuously pulled in at the wrong position, and the synchronization will be acquired again.

According to the synchronizing device of the second aspect, since the synchronizing circuits are arranged in the front stage and the rear stage of the error correction circuit, the synchronization can be surely pulled in, and the error correction can be performed in the synchronization pattern. When the synchronization is pulled in by the pseudo synchronization pattern, the synchronization circuit in the rear stage cannot pull in the synchronization, and the signal from the synchronization circuit in the rear stage is received and the synchronization signal in the front stage is received. In the synchronizing circuit, since the pulled-in synchronization is released, it is prevented that the synchronization is continuously pulled in at an erroneous position, and the synchronization is captured again.

According to the synchronization circuit of the fourth aspect, even if the synchronization pattern is not captured, the cycle of the synchronization capture is held for a certain period. Therefore, even in the case of data having a plurality of synchronization patterns, Until the synchronization pattern is captured, the cycle of the synchronization acquisition will be held, and the synchronization can be pulled in quickly.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a synchronizer according to an embodiment of the present invention. The portion corresponding to the conventional example of FIG.
The same reference numerals are given.

The synchronizing apparatus of this embodiment detects an error in the synchronizing circuit 1 to which digital data is given from a demodulation section (not shown) in the preceding stage and an error in the data given through the synchronizing circuit 1 and corrects the error. And a circuit 2.

The synchronization circuit 1 for pulling in the synchronization includes a synchronization pattern detecting section 3 for detecting a predetermined synchronization pattern included in the data, and a cycle generating section 4 for generating a fixed acquisition cycle in response to the detection timing of the synchronization pattern. A front protection unit 5 that counts the number of synchronization patterns captured in the capture cycle; a rear protection unit 6 that counts the number of synchronization patterns not captured in the capture cycle; The synchronization establishing unit 7 is provided.

The error correction circuit 2 detects and corrects an error and outputs it to a signal processing unit (not shown) in the subsequent stage.
And an error detection signal output unit 9 that outputs an error detection signal to the signal processing unit when an error of a certain level or more occurs.

In this embodiment, the synchronization circuit 1 is constructed so that an error detection signal is provided from the error correction circuit 2 in order to prevent the synchronization from being continuously pulled in at an erroneous position due to the pseudo synchronization pattern. When this error detection signal is given, the synchronizing circuit 1 is designed to cancel the pulled-in synchronization.

That is, when the synchronization circuit 1 pulls in the pseudo synchronization pattern, many errors occur in the error correction circuit 2 and an error detection signal is output, so that the synchronization circuit 1
Responds to this error detection signal, cancels synchronization and newly starts synchronization acquisition.

FIG. 2 is a block diagram showing the configuration of the cycle generator 4 of FIG. 1. The same reference numerals are given to the parts corresponding to the conventional example of FIG. The cycle generation unit 4 holds and abandons the synchronization pattern acquisition cycle.
And a cycle generation unit 11 for generating a synchronization pattern acquisition cycle.
And The cycle holding / abandoning unit 10 holds or abandons the acquisition cycle of the synchronization pattern by using various signals inside the synchronization circuit 1. The cycle generation unit 11 generates a synchronization pattern acquisition cycle according to the synchronization pattern detection timing based on the signal from the cycle holding / abandoning unit 10.

That is, the cycle generator 4 generates a fixed cycle of the capture cycle in response to the sync pattern detection timing from the sync pattern detector 3, and the front protector 5 captures the sync pattern at the capture cycle. Is interrupted, or the backward protection unit 6 cannot capture the synchronization pattern a certain number of times, or when a large number of errors occur in the error correction circuit 2 and an error detection signal is given, the acquisition cycle is set. While abandoning and generating a capture cycle based on a new detection timing, the synchronization establishing unit 7 cancels the synchronization.

Next, the operation will be described.

First, when the synchronous pattern detecting section 3 detects a synchronous pattern, the cycle generating section 4 generates the synchronous pattern capturing cycle as described above based on the timing. The front protection unit 5 counts the number of times the synchronization pattern is continuously captured in the capture cycle generated by the cycle generation unit 4. When the synchronization pattern is captured a certain number of times, the front protection unit 4 sends a signal to the synchronization establishing unit 7 and the synchronization establishing unit 7 pulls in the synchronization.

After the synchronization is pulled in, the rear protection unit 6 counts the number of times that the synchronization pattern is not captured in the capture cycle generated by the cycle generation unit 4, and if it is not captured a fixed number of times, the synchronization establishment unit 7 is called. Sending a signal, synchronization establishment unit 7
Then cancel the synchronization.

The front protection unit 5 interrupts the capture of the synchronization pattern, the rear protection unit 6 cannot capture the synchronization pattern for a fixed number of times, and more errors occur in the error correction circuit 2, resulting in an error detection signal. When given, the cycle generation unit 4 redoes the generation of the synchronization pattern acquisition cycle, and the synchronization establishment unit 7 cancels the synchronization.

As described above, when a large number of errors of a certain level or more occur in the error correction circuit 2, the synchronization circuit 1 cancels the pulled-in synchronization and newly adds it based on the error detection signal from the error correction circuit 2. Since the synchronization acquisition is started, if many errors occur in the error correction circuit 2 due to the synchronization circuit 1 pulling in the pseudo synchronization pattern, the synchronization pulled in by the synchronization circuit 1 is immediately released. It is prevented that the pattern is continuously pulled in.

FIG. 3 is a block diagram of a synchronizer according to another embodiment of the present invention. The parts corresponding to the above-mentioned embodiment are:
The same reference numerals are given.

The synchronizing apparatus of this embodiment is provided with a synchronizing circuit 1 ₁ to which digital data is given from a demodulation section (not shown) in the preceding stage, and an error correction circuit 2 which processes an error in the data given via the synchronizing circuit 1 _1. And a synchronization circuit 1 arranged at a subsequent stage of the error correction circuit 2 for performing synchronization pull-in again.
_{It has 0} and.

The front of the synchronization circuit 1 _1, the synchronization pattern detection unit 3 for detecting a predetermined synchronization pattern contained in the data
When, the period generating unit 4 ₁ to generate a capture cycle of a fixed period in response to the detection timing of the synchronization pattern, the front protection unit 5 for counting the number of captured synchronization pattern in the capture period, at said capture cycle The backward protection unit 6 that counts the number of times that the synchronization pattern is not captured and the synchronization establishment unit 7 ₁ that controls the synchronization pull-in or the synchronization release are provided.

The error correction circuit 2, an error processing unit 8 for outputting the synchronizing circuit 1 ₀ in the subsequent stage to detect and correct errors, subsequent signal processing unit an error detection signal when more than a predetermined error occurs ( And an error detection signal output section 9 for outputting to (not shown).

The synchronous circuit 1 ₀ in the subsequent stage, for example, is similar to the conventional example of the synchronization circuit in FIG. 10, when it can not pull the synchronization, the synchronization acquisition impossible signal indicative thereof, the front stage of the synchronization circuit 1 ₁ Output to.

In this embodiment, two synchronization circuits 1 ₁ and 1 _{0 are provided.}
In order to prevent the continuous pulling of the synchronization at an erroneous position by the pseudo synchronization pattern, the synchronization circuit 1 ₁ on the front side of the error correction circuit 2 ₁
In accordance with the synchronization acquisition impossible signal indicating that no retraction synchronization from the synchronization circuit 1 ₀ in the subsequent stage side, so as to release the I synchronization retracted.

[0047] Thus, it is adapted to the synchronization acquisition impossible signal from the subsequent stage of the synchronization circuit 1 ₀ is applied to the period generating unit 4 ₁ and the synchronization establishing unit ₇₁ of the pre-stage of the synchronizing circuit 1 _1, preceding the synchronization When the circuit 1 ₁ receives the synchronization non-capturing signal after pulling in the synchronization, the cycle generation unit 4 redoes the generation of the synchronization pattern acquisition period, and the synchronization establishment unit 7 ₁ releases the synchronization. is there.

According to this embodiment, particularly in the case of data in which the synchronization pattern is also error-corrected, when the pseudo synchronization pattern is pulled in by the synchronization circuit 1 ₁ in the preceding stage, the error correction circuit 2 ₁ in the performing error correction, pseudo synchronization pattern will not match the synchronization pattern, and therefore, the subsequent synchronization circuit 1 ₀ can not draw synchronization, synchronization acquisition impossible signal of the preceding stage to the synchronous circuit 1 ₁ Will be output.

[0049] Therefore, when the data are also subjected to error correction in the synchronization pattern, when pulling the pseudo sync pattern in front of the synchronizing circuit 1 _1, the subsequent synchronization circuit 1 ₀ can not draw synchronization , will be the synchronization acquisition impossible signal is output, whereby, in the former of synchronizing circuits 1 ₁ and performs a new synchronization acquisition to release the pseudo sync. This prevents the pseudo sync pattern from being continuously pulled in.

[0050] Figure 4 is a block diagram showing the configuration of the period generating unit 4 ₁ of FIG. Cycle generation unit 4 _1, holds the capture period of the synchronization pattern, the period holding and abandonment unit 10 to give
₁ and a cycle generator 1 that generates a synchronization pattern capture cycle
1 is provided. In cycle holding and abandonment unit 10 _1, using the synchronization circuit inside the various signals, it holds or abandon the capture period of the synchronization pattern. The cycle generation unit 11 generates a synchronization pattern acquisition cycle according to the synchronization pattern detection timing based on the signal from the cycle holding / abandoning unit 10 ₁ .

That is, the cycle generator 4 ₁ generates a fixed cycle of the capture cycle in response to the detection timing of the sync pattern from the sync pattern detector 3, and the front protection unit 5 generates the sync pattern at the capture cycle. capture or interrupted, or in backward protection unit 6, it may not be a certain number of times capture of the sync pattern, and further, when the synchronization acquisition impossible signal from the synchronization circuit 1 ₀ second-stage is given, abandoned acquisition cycle Then, while the acquisition period based on the new detection timing is generated, the synchronization establishing unit 7 ₁ releases the synchronization.

FIG. 5 is a block diagram showing the structure of a synchronizing apparatus according to still another embodiment of the present invention, and FIG. 6 is a block diagram showing the structure of the cycle generation unit shown in FIG. The same reference numerals are attached to the portions corresponding to.

This embodiment has the configuration of each of the above-mentioned embodiments together, and when the error correction circuit 2 generates an error of a certain level or more, the synchronization circuit 1 ₂ on the preceding stage side has an error detection signal. together is given, when it can not pull in synchronization at a later stage of the synchronizing circuit 1 ₀ is configured as the synchronization acquisition impossible signal is applied, pre-stage of the synchronizing circuit 1
Similarly to each of the above-described embodiments, ₂ is to cancel the pulled-in synchronization and start a new synchronization acquisition when the error detection signal is applied or when the synchronization acquisition impossible signal is applied.

That is, in this embodiment, the cycle generator 4
_2, in response to the detection timing of the synchronization pattern from the synchronization pattern detection unit 3 generates a capturing period of a constant period, the front protection unit 5, or interrupted acquisition of the synchronization pattern in the capture cycle, or backward protection in part 6, it may not be a certain number of times capture of the sync pattern, and further, when given an error detection signal many errors occur in the error correction circuit 12, or the synchronization from the synchronization circuit 1 ₀ second-stage When the non-captureable signal is given, the capture cycle is abandoned to generate a capture cycle based on a new detection timing, while the synchronization establishment unit 7 ₂ releases the synchronization.

Therefore, according to this embodiment, when a large number of errors occur in the error correction circuit 2 by pulling in the pseudo synchronization pattern in the synchronization circuit 1 ₂ in the preceding stage, error detection from the error correction circuit 2 is detected. In the case of data in which the synchronization pulled in by the synchronizing circuit 1 ₂ is released by a signal, or when the synchronizing pattern is also subjected to error correction, the synchronizing circuit 1 ₂ in the preceding stage pulls in the pseudo synchronizing pattern and the synchronizing circuit 1 in the following stage. when it was not possible to draw synchronization _0, since it is canceled synchronization retracted by a synchronization circuit 1 ₀ by the synchronization acquisition can not signal a new synchronization acquisition is started, even that such continue pulling the pseudo sync pattern It will be surely prevented.

The rest of the configuration is the same as that of each of the above-mentioned embodiments, and therefore its explanation is omitted.

FIG. 7 is a block diagram showing the structure of a synchronizing circuit according to an embodiment of the present invention, and FIG. 8 is a block diagram showing the structure of the period generator of FIG. Corresponding parts are designated by the same reference numerals.

This embodiment is different from the above-mentioned embodiments in that it is a synchronizing circuit suitable for quickly pulling in the synchronization of data having a plurality of synchronization patterns, and holds the capture cycle when pulling in the synchronization. It is characterized by

[0059] synchronous circuit 1 ₃ of this embodiment, as shown in FIG. 7, the synchronization pattern detection unit 3 for detecting a predetermined synchronization pattern contained in the data, a fixed period in response to the detection timing of the synchronization pattern Period generating unit 4 ₃ for generating the capturing period, a front protection unit 5 ₃ for counting the number of synchronization patterns captured in the capturing period, and a backward unit 5 ₃ for counting the number of synchronization patterns not captured in the capturing period. The protection unit 6 and the synchronization establishing unit 7 ₃ that controls the synchronization pull-in or the synchronization release are provided.

As shown in FIG. 8, the cycle generator 4 ₃ holds the sync pattern acquisition cycle and holds the cycle abandonment section 10 _3, and the front protection section 5 ₃ interrupts the sync pattern acquisition. Sometimes, instead of abandoning the acquisition cycle immediately, the acquisition cycle is held for a certain period, if the synchronization pattern is acquired within the certain period, the acquisition cycle is held as it is, and if the synchronization pattern is not acquired, the acquisition cycle is abandoned. Control unit 12 for controlling holding / abandoning of the capture cycle
And a cycle generation section 11 that generates a synchronization pattern acquisition cycle in response to the acquisition / retention of the acquisition cycle of the control section 12.

Further, the control unit 12 holds the value of the counter of the front protection unit 5 ₃ which counts the number of the captured synchronization patterns, without resetting it, while holding the capturing period for a certain period. It controls. That is, in the conventional, when abandoned acquisition period in the cycle retention and abandonment unit 10 _0, had started a new count to reset the value of the counter of the forward protection unit 5, in this embodiment,
The value of the counter is held for the fixed period, and when the synchronization pattern is captured within the fixed period, counting by the counter is continuously performed.

In the case of data having a plurality of sync patterns, for example, as shown in FIG. 12 described above, another sync pattern 2 is provided between sync patterns 1 to be captured.
Therefore, if the acquisition cycle is abandoned immediately after the synchronization pattern 2 is detected, the correct acquisition cycle will be abandoned, and it will take a long time to pull in the synchronization, or it is difficult to pull in the synchronization. Therefore, in this embodiment, the acquisition cycle is not abandoned immediately but is held for a certain period as described above.

Next, the operation of this embodiment will be described with reference to FIG.
The description will be applied to the case of pulling in the synchronization of data having a plurality of synchronization patterns shown in FIG.

FIG. 9 is a time chart for explaining the synchronization pull-in according to this embodiment.
FIG.

In this embodiment, when the synchronization acquisition is started from the second synchronization pattern 1 out of the synchronization patterns 1 generated twice in succession, the synchronization cannot be acquired because the synchronization pattern 2 comes after the synchronization pattern 1. But for a certain period of time, for example,
Since the capture cycle is held over the period of two cycles, it is possible to capture from the synchronization pattern 1 after the synchronization pattern 2 and capture the synchronization pattern 1 twice in succession, so that the synchronization can be correctly pulled.

In this way, it is possible to efficiently pull in synchronization even for data having a plurality of synchronization patterns.

In the above-described embodiment, as shown in FIG. 9, when the synchronization pattern 1 is captured twice consecutively,
Although the synchronization is pulled in, as another embodiment of the present invention, the synchronization is pulled in at the time when the synchronization pattern 1 is captured twice with the synchronization pattern 2 interposed, that is, the synchronization pattern 1 next to the synchronization pattern 2. Good.

In addition to the structure of this embodiment, the structure of each of the above-mentioned embodiments, that is, the synchronization pulled by the error detection signal, the synchronization uncapturing signal, or both may be released. In this case, even if the data has a plurality of synchronization patterns, it is possible to efficiently pull in the synchronization, and it is possible to prevent the false synchronization from being continuously pulled by mistake, thereby improving the reliability of pulling the synchronization. .

[0069]

As described above, according to the present invention, not only the inside of the synchronizing circuit but also the signal from the outside such as the error detection signal or the uncaptureable signal is used to cancel the synchronization. It is possible to effectively prevent the continuous pull-in and increase the reliability of the pull-in of synchronization.

Further, when the synchronization is pulled in, even if the synchronization pattern is not captured, the cycle of the synchronization capture is held for a certain period. Therefore, even in the case of data having a plurality of synchronization patterns,
Until the same synchronization pattern is captured, the synchronization capture cycle is held, and it is possible to efficiently pull in synchronization.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a cycle generation unit in FIG.

FIG. 3 is a block diagram showing a configuration of a synchronization device according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a cycle generation unit in FIG.

FIG. 5 is a block diagram showing a configuration of a synchronization device according to still another embodiment of the present invention.

6 is a block diagram showing a configuration of a cycle generation unit in FIG.

FIG. 7 is a block diagram showing a configuration of a synchronizing circuit according to another embodiment of the present invention.

8 is a block diagram showing a configuration of a cycle generation unit in FIG.

9 is a time chart used for explaining the operation of the embodiment of FIG.

FIG. 10 is a block diagram showing a configuration of a conventional example.

FIG. 11 is a block diagram showing a configuration of a conventional cycle generator.

FIG. 12 is a time chart for explaining the operation of the conventional example.

[Explanation of symbols]

1, 1 ₀ , 1 ₁ , 1 ₂ , 1 ₃ Synchronization circuit 2 Error correction circuit 3 Synchronization pattern detection unit 4, 4 ₀ , 4 ₁ , 4 ₂ , 4 ₃ Cycle generation unit 5, 5 ₃ Front protection unit 6 Back protection Part 7, 7 ₀ , 7 ₁ , 7 ₂ , 7 ₃ Synchronization establishment part 12 Control part

Claims (5)

[Claims] 1. A synchronization circuit for detecting a synchronization pattern to pull in synchronization, and an error correction circuit for detecting an error in data generated in a transmission path, wherein the synchronization circuit detects an error from the error correction circuit. A synchronizing device characterized by releasing the drawn synchronization based on a signal. 2. An error correction circuit for detecting an error in data generated on a transmission line, and a plurality of synchronization circuits arranged at a front stage and a rear stage of the error correction circuit, respectively, for detecting a synchronization pattern and pulling synchronization. The synchronization device is characterized in that the synchronization circuit on the front side of the error correction circuit cancels the pulled-in synchronization based on a signal from the synchronization circuit on the rear side indicating that the synchronization cannot be pulled. 3. The synchronizing device according to claim 2, wherein the synchronizing circuit on the preceding stage side cancels the pulled-in synchronization based on an error detection signal from the error correction circuit. 4. A synchronization circuit which pulls in synchronization by capturing a synchronization pattern a certain number of times in a synchronization capture cycle, wherein the synchronization circuit holds the synchronization capture cycle for a certain period without capturing the synchronization pattern. . 5. The synchronization circuit pulls synchronization by capturing a synchronization pattern a certain number of times in a synchronization capture cycle, and holds the synchronization capture cycle for a certain period without capturing the synchronization pattern. The synchronization device according to any one of claims 1 to 3, wherein: