JPH09281188A - Ic-testing apparatus - Google Patents

Ic-testing apparatus

Info

Publication number
JPH09281188A
JPH09281188A JP8092205A JP9220596A JPH09281188A JP H09281188 A JPH09281188 A JP H09281188A JP 8092205 A JP8092205 A JP 8092205A JP 9220596 A JP9220596 A JP 9220596A JP H09281188 A JPH09281188 A JP H09281188A
Authority
JP
Japan
Prior art keywords
test
performance board
voltage
testing device
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8092205A
Other languages
Japanese (ja)
Inventor
Satoshi Kobayashi
智 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP8092205A priority Critical patent/JPH09281188A/en
Publication of JPH09281188A publication Critical patent/JPH09281188A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To calibrate a testing device in a short time by setting between the testing device and a performance board a means for electrically separating the performance board from the testing device and calibrating each part of the testing device without detaching the performance board from on a test head. SOLUTION: A switch is connected as a separating means 60 between a testing device 20 and a cable 15. Because of setting the separating means 60, a performance board 10 can be electrically separated from the testing device 20 without being detached from on a test head 13. Accordingly, a calibration can be started with the manipulation of the switch only. Moreover, the device is restored simply with the manipulation of the switch when the calibration is finished. A time required for the calibration is thus shortened, whereby an IC is tested efficiently.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明はICが正常に動作
するか否かを試験するIC試験装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing whether an IC operates normally.

【0002】[0002]

【従来の技術】図3に従来のIC試験装置の概略の構成
を示す。図中10はパフォーマンスボード、11はこの
パフォーマンスボード10に搭載したICソケット、1
2はこのICソケット11に接触させた被試験IC、1
3はパフォーマンスボード10を電気的に試験装置に接
続するためのテストヘッド、14はテストヘッド13の
上面に突出して設けられたポゴピンと呼ばれる接触子を
示す。被試験IC12の各端子はこの接触子14とケー
ブル15を介して試験装置20に接続される。
2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional IC test apparatus. In the figure, 10 is a performance board, 11 is an IC socket mounted on this performance board 10, 1
2 is an IC to be tested brought into contact with the IC socket 11, 1
Reference numeral 3 denotes a test head for electrically connecting the performance board 10 to a test device, and reference numeral 14 denotes a contactor called a pogo pin provided on the upper surface of the test head 13 so as to project. Each terminal of the IC under test 12 is connected to the test apparatus 20 via the contactor 14 and the cable 15.

【0003】試験装置20は被試験IC12の動作を試
験する機能試験装置30と、被試験IC12の各端子の
直流特性を測定するための直流試験装置40と、被試験
IC12の負荷試験を行なうプログラムロードテスト装
置50とを具備して構成される。図では被試験IC12
の1つの端子を試験する構成だけを示している。機能試
験装置30は試験パターン信号を被試験IC12に与え
るドライバ31と、被試験IC12の出力信号の波形が
所定の電圧の範囲に入っているか否かを判定するコンパ
レータ32とを具備し、これらドライバ31とコンパレ
ータ32を介して被試験IC12との信号の授受を行な
う。
The test apparatus 20 includes a function test apparatus 30 for testing the operation of the IC 12 under test, a DC test apparatus 40 for measuring the DC characteristics of each terminal of the IC 12 under test, and a program for performing a load test on the IC 12 under test. And a load test device 50. In the figure, the IC under test 12
Only the configuration for testing one of the terminals is shown. The functional test apparatus 30 includes a driver 31 that gives a test pattern signal to the IC under test 12, and a comparator 32 that determines whether the waveform of the output signal of the IC under test 12 is within a predetermined voltage range. Signals are exchanged with the IC under test 12 via 31 and the comparator 32.

【0004】直流試験装置40は正確な値を持つ電圧を
発生する電圧発生器と、正確な値を持つ電流を出力する
電流発生器と、電圧、電流測定器等を具備し、被試験I
C12の端子に所定の電圧を与えた状態で予定した電流
が流れるか否かを見る電圧印加電流測定試験と、被試験
IC12の端子に所定の電流を流した状態でその端子に
予定した電圧が発生するか否かを見る電流印加電圧測定
試験を行なう。
The DC test apparatus 40 comprises a voltage generator for generating a voltage having an accurate value, a current generator for outputting a current having an accurate value, a voltage and current measuring device, etc.
A voltage applied current measurement test to see if a predetermined current flows when a predetermined voltage is applied to the terminal of C12, and a predetermined voltage is applied to the terminal of the IC12 under test with a predetermined current applied. Perform the current applied voltage measurement test to see if it occurs.

【0005】プログラムロードテスト装置50は負荷抵
抗器51と、ダイオードブリッジ52と、電流源53,
54と、可変電圧源55と、スイッチ56とを具備して
構成される。スイッチ56をオンの状態に設定し、被試
験IC12の端子に負荷抵抗器51を接続した状態で被
試験IC12から信号を出力させる。この信号の波形を
機能試験装置30に設けたコンパレータを通じて取り込
み、立上り速度、立下り速度を計測し、出力波形の立上
り速度及び立下り速度が予定した規格の範囲に入ってい
るか否かを試験する。また、他の試験として、スイッチ
56をオフに設定し、可変電圧源55の電圧を被試験I
C12の出力波形の中間の電圧VTに設定し、被試験I
C12から出力信号を出力させる。出力信号がL論理に
ある状態では被試験IC12の端子の電圧が可変電圧源
55に設定した電圧VTより低いので、ダイオードブリ
ッジ52を通じて電流源53を流れる電流IPが被試験
IC12の端子に流れ込む状態となる。また、被試験I
C12の端子がH論理を出力した状態では、この端子の
電圧が可変電圧源55の電圧VTより高くなるので、こ
の場合には被試験IC12の端子から電流INが流れ出
し、この電流INが電流源54に吸引される。この試験
により、被試験IC12がL論理の状態と、H論理の状
態で出力端子に所定の電流を出力するか否かを試験して
いる。
The program load test apparatus 50 includes a load resistor 51, a diode bridge 52, a current source 53,
54, a variable voltage source 55, and a switch 56. The switch 56 is set to the ON state, and the signal is output from the IC 12 under test with the load resistor 51 connected to the terminal of the IC 12 under test. The waveform of this signal is taken in through a comparator provided in the functional test device 30, the rising speed and the falling speed are measured, and it is tested whether the rising speed and the falling speed of the output waveform are within the predetermined standard range. . Further, as another test, the switch 56 is set to OFF and the voltage of the variable voltage source 55 is changed to I under test.
The voltage VT in the middle of the output waveform of C12 is set, and I
An output signal is output from C12. Since the voltage of the terminal of the IC under test 12 is lower than the voltage VT set in the variable voltage source 55 when the output signal is in the L logic, the current IP flowing through the current source 53 through the diode bridge 52 flows into the terminal of the IC under test 12. Becomes In addition, I
When the terminal of C12 outputs H logic, the voltage of this terminal becomes higher than the voltage VT of the variable voltage source 55. In this case, the current IN flows out from the terminal of the IC 12 under test, and this current IN is the current source. 54 is sucked. This test tests whether the IC 12 under test outputs a predetermined current to the output terminal in the L logic state and the H logic state.

【0006】[0006]

【発明が解決しようとする課題】上述したように試験装
置20は各種の試験を行なうが、試験の信頼性を確保す
るためには各試験装置の出力電圧、出力電流が正しく校
正されていなければならない。例えば機能試験装置30
ではドライバ31から出力される試験パターン信号のL
論理の電圧、H論理の電圧が正しく設定されているか否
か、コンパレータのスレッシュホールド電圧が予定して
いる電圧に設定されているか否か、或はプログラムロー
ドテスト装置50では電流源53と54の電流が予め予
定した電流値に設定されているか否か、可変電圧源55
の電圧が正しい値であるか否か、等を校正する必要があ
る。
As described above, the test apparatus 20 performs various tests, but in order to ensure the reliability of the test, the output voltage and output current of each test apparatus must be properly calibrated. I won't. For example, the functional test device 30
Then, L of the test pattern signal output from the driver 31
Whether or not the logic voltage and the H logic voltage are properly set, whether or not the threshold voltage of the comparator is set to a predetermined voltage, or in the program load test device 50, the current sources 53 and 54 are set. Whether the current is set in advance to a predetermined current value, the variable voltage source 55
It is necessary to calibrate whether or not the voltage of is the correct value.

【0007】これらの校正を行なう場合、直流試験装置
40に設けられた電圧発生器、電流発生器と、電圧、電
流測定器を利用して校正を行なっている。この校正を行
なう場合、従来はパフォーマンスボード10を取外し、
ケーブル15の先に何も接続されない状態にして各部の
電圧、電流を直流試験装置40によって測定している。
つまり、パフォーマンスボード10には各種の回路が接
続されているため、パフォーマンスボード10上の回路
が負荷となって校正に影響を与えるため、パフォーマン
スボード10を取外して校正を行なう必要がある。
When performing these calibrations, the calibration is performed using a voltage generator, a current generator and a voltage / current measuring device provided in the DC test apparatus 40. To perform this calibration, remove the performance board 10 in the past,
With nothing connected to the end of the cable 15, the voltage and current of each part are measured by the DC test device 40.
That is, since various circuits are connected to the performance board 10, the circuit on the performance board 10 becomes a load and affects the calibration. Therefore, it is necessary to remove the performance board 10 and perform calibration.

【0008】パフォーマンスボード10をテストヘッド
13から取外すには少なくとも数人の人手を要し、簡単
な作業でなく、取外しとその復旧作業だけで長い時間が
とられ、更に校正作業に要する時間が加わるため、ダウ
ンタイム(不作動時間)が長くなる。この結果IC試験
の効率が悪くなる欠点がある。この発明の目的は校正作
業を短時間に済ませることができるIC試験装置を提供
しようとするものである。
It takes at least several people to remove the performance board 10 from the test head 13, and it takes a long time only for the removal and the restoration work, not the simple work, and the time required for the calibration work is added. Therefore, the down time (non-operation time) becomes long. As a result, there is a drawback that the efficiency of the IC test becomes poor. An object of the present invention is to provide an IC test apparatus which can complete calibration work in a short time.

【0009】[0009]

【課題を解決するための手段】この発明では被試験IC
の各端子の直流特性を試験する直流試験装置を利用して
ICの機能試験を行なう機能試験装置及びプログラムロ
ードテスト装置の各部の電圧値及び電流値を校正するI
C試験装置において、試験装置とパフォーマンスボード
との間にパフォーマンスボードを電気的に切離す手段を
設けた構成とするものである。
In the present invention, the IC to be tested is
Calibrate the voltage and current values of each part of the functional test device and the program load test device for performing the functional test of the IC by using the DC test device for testing the DC characteristic of each terminal of I.
In the C test apparatus, a means for electrically disconnecting the performance board is provided between the test apparatus and the performance board.

【0010】この発明の構成によれば試験装置とパフォ
ーマンスボードを電気的に切離す手段を設けたから、こ
の切離し手段によってパフォーマンスボードをテストヘ
ッドの上から取外さなくても試験装置各部の校正を行な
うことができる。この結果短時間に試験装置各部の校正
を行なうことができ、IC試験装置を不作動状態におく
時間を大幅に少なくできる利点が得られる。
According to the structure of the present invention, the means for electrically disconnecting the test device and the performance board is provided. Therefore, each part of the test equipment can be calibrated by this disconnecting means without removing the performance board from the test head. be able to. As a result, each part of the test apparatus can be calibrated in a short time, and there is an advantage that the time for which the IC test apparatus is inactive can be significantly reduced.

【0011】[0011]

【発明の実施の形態】図1にこの発明によるIC試験装
置の一実施例を示す。図3と対応する部分には同一符号
を付して示す。この実施例では試験装置20とケーブル
15との間にスイッチを接続し、このスイッチを切離手
段60とした場合を示す。この切離手段60を設けたこ
とによりパフォーマンスボード10をテストヘッド13
の上から取外さなくても試験装置20からパフォーマン
スボード10を電気的に切離すことができる。
FIG. 1 shows an embodiment of an IC test apparatus according to the present invention. Portions corresponding to those in FIG. 3 are designated by the same reference numerals. In this embodiment, a switch is connected between the test apparatus 20 and the cable 15, and this switch is used as the disconnecting means 60. By providing the separating means 60, the performance board 10 can be mounted on the test head 13
It is possible to electrically disconnect the performance board 10 from the test apparatus 20 without removing it from above.

【0012】従ってスイッチ操作だけで校正作業に取り
掛ることができる。また校正の終了時点でもスイッチ操
作だけで復旧することができるから、校正に要する時間
を短時間にすることができる利点が得られる。図2はこ
の発明の他の実施例を示す。図2に示す実施例ではパフ
ォーマンスボード10をテストヘッド13に抑え付ける
抑え付け手段70に、パフォーマンスボード10のロッ
クを解いた状態でパフォーマンスボード10を接触子1
4から引き離す切離手段60を付加した構成としたもの
である。この実施例に示す切離手段60は、パフォーマ
ンスボード10を接触子14の可動ストローク(ポゴピ
ンは先端にバネによって突出する向に偏倚力が与えられ
た可動部分を有し、その可動部分のストローク)以上に
移動させる手段で構成される。図2の例ではレバー71
によって抑え付け手段70と切離手段60を移動させる
ように構成した場合を示す。
Therefore, the calibration work can be started only by operating the switch. Further, even when the calibration is completed, it can be restored only by operating the switch, so that there is an advantage that the time required for the calibration can be shortened. FIG. 2 shows another embodiment of the present invention. In the embodiment shown in FIG. 2, the performance board 10 is attached to the holding means 70 for holding the performance board 10 to the test head 13 in a state where the performance board 10 is unlocked.
4 has a structure in which a separating means 60 for separating from 4 is added. The disconnecting means 60 shown in this embodiment moves the performance board 10 to a movable stroke of the contactor 14 (the pogo pin has a movable portion to which a biasing force is applied at the tip in the direction of protruding by a spring, and the stroke of the movable portion). It is composed of means for moving the above. In the example of FIG. 2, the lever 71
The case where the pressing means 70 and the separating means 60 are configured to be moved by is shown.

【0013】[0013]

【発明の効果】以上説明したように、この発明によれ
ば、切離手段60によってパフォーマンスボード10を
試験装置20から電気的に切離すことができる。従って
パフォーマンスボード10をテストヘッド13から取外
す作業を行なわなくて済むため、試験装置20の各部の
校正を短時間に済ませることができる。よってIC試験
を効率よく実施することができる利点が得られる。
As described above, according to the present invention, the performance board 10 can be electrically separated from the test apparatus 20 by the separation means 60. Therefore, the work of removing the performance board 10 from the test head 13 does not have to be performed, so that each part of the test apparatus 20 can be calibrated in a short time. Therefore, there is an advantage that the IC test can be efficiently performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を示す接続図。FIG. 1 is a connection diagram showing one embodiment of the present invention.

【図2】この発明の変形実施例を示す側面図。FIG. 2 is a side view showing a modified embodiment of the present invention.

【図3】従来の技術を説明するための接続図。FIG. 3 is a connection diagram for explaining a conventional technique.

【符号の説明】[Explanation of symbols]

10 パフォーマンスボード 11 ICソケット 12 被試験IC 13 テストヘッド 14 接触子 15 ケーブル 20 試験装置 30 機能試験装置 40 直流試験装置 50 プログラムロードテスト装置 60 切離手段 10 Performance Board 11 IC Socket 12 IC Under Test 13 Test Head 14 Contact 15 Cable 20 Test Device 30 Functional Test Device 40 DC Test Device 50 Program Load Test Device 60 Disconnection Means

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被試験ICを搭載するパフォーマンスボ
ードと、このパフォーマンスボードに設けた各端子を試
験装置に接続するためのテストヘッドとを具備して構成
されるIC試験装置において、 上記テストヘッドとパフォーマンスボードとの間を電気
的に切離す手段を設けたことを特徴とするIC試験装
置。
1. An IC test apparatus comprising a performance board on which an IC under test is mounted and a test head for connecting each terminal provided on the performance board to a test apparatus, the test head comprising: An IC test apparatus comprising means for electrically disconnecting the performance board.
JP8092205A 1996-04-15 1996-04-15 Ic-testing apparatus Withdrawn JPH09281188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8092205A JPH09281188A (en) 1996-04-15 1996-04-15 Ic-testing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8092205A JPH09281188A (en) 1996-04-15 1996-04-15 Ic-testing apparatus

Publications (1)

Publication Number Publication Date
JPH09281188A true JPH09281188A (en) 1997-10-31

Family

ID=14047953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8092205A Withdrawn JPH09281188A (en) 1996-04-15 1996-04-15 Ic-testing apparatus

Country Status (1)

Country Link
JP (1) JPH09281188A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029571A1 (en) * 1999-10-19 2001-04-26 Teradyne, Inc. Circuit and method for improved test and calibration in automated test equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001029571A1 (en) * 1999-10-19 2001-04-26 Teradyne, Inc. Circuit and method for improved test and calibration in automated test equipment
US6331783B1 (en) 1999-10-19 2001-12-18 Teradyne, Inc. Circuit and method for improved test and calibration in automated test equipment
JP2003512630A (en) * 1999-10-19 2003-04-02 テラダイン・インコーポレーテッド Improved test and calibration circuit and method in automatic test equipment
KR100731344B1 (en) * 1999-10-19 2007-06-21 테라다인 인코퍼레이티드 Circuits and methods for testing and calibrating in automated test equipment

Similar Documents

Publication Publication Date Title
US4714875A (en) Printed circuit board fault location system
CN210604879U (en) Voltage current source test circuit
JPH09281188A (en) Ic-testing apparatus
JP3239864B2 (en) Test board for power / GND terminal continuity test
JP5663943B2 (en) Test equipment
JP2809304B2 (en) Inspection equipment for IC testing equipment
JP3353288B2 (en) LSI test equipment
JPH0954143A (en) Parallel-connected voltage generators in semiconductor testing apparatus and contact test method
JP2000074975A (en) Substrate inspection device and substrate inspection method
JP4173229B2 (en) IC test equipment
JPH11304880A (en) Semiconductor testing device
JP4066265B2 (en) Contact ring of semiconductor test equipment
JPH06265594A (en) Ic test equipment
JPH04302453A (en) semiconductor test equipment
JPH0541419A (en) Estimation method of test equipment
JPH03293571A (en) Apparatus for testing semiconductor integrated circuit
JP4863048B2 (en) IC tester
JP5040790B2 (en) Diagnostic board for semiconductor test equipment
CN118777828A (en) Test circuit and test device including the test circuit
JP2000133395A (en) Ic measuring socket
JP2002075538A (en) connector
JPH05315411A (en) Test head
JPH1123648A (en) Test head for ic tester
JP2002243810A (en) Semiconductor device and inspection method thereof
JP2001296333A (en) IC tester

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20030701