JPH09282000A - Data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the processing quantity by DSP(digital signal processing processor) without increasing the DSP by storing an input signal in a storage means once and fetching the input signal stored in the storage means by the DSP. SOLUTION: When a voice or an audio input signal is inputted to a serial/ parallel(S/P) converter 11, the S/P converter 11 converts the inputted serial data into parallel data to output them to a memory 12. The memory 12 stores the data converted into parallel data for a fixed inerval and outputs the inputted data to a DSP 13 in parallel. Then, the DSP 13 reads in the data from the memory 12 at an arbitrary time and performs the digital processing of the data. That is, the input signal to be inputted at random is stored in the memory 12 once and the DSP 13 performs the digital signal processing of the data by fetching the data from the memory 12 at arbitrary time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit, and more particularly to a data processing circuit used in a voice codec or an audio codec installed in a transmission device or a multiplexing device.

[0002]

2. Description of the Related Art Currently, in a transmission device or a multiplexing device, a voice signal or an audio signal is compressed in order to reduce the amount of transmission information. Dedicated LSI, processor type dedicated LS for compression of voice or audio signals
I, Digital Signal Processor (DSP: digital
Signal processor Hereinafter, abbreviated as DSP as appropriate. There are three ways to use). In particular, a dedicated DSP is used as a voice codec installed in the multiplexing device to realize real-time signal processing.

The DSP has an arithmetic unit mainly having a multiplication function, and firmware controls the arithmetic function and data transfer to perform signal processing. Generally, the internal function of the DSP is roughly divided into a program decoder section, a data memory section, an arithmetic section and an input / output section, which are organically combined.

As a conventional DSP used for this kind of voice codec or audio codec, there is, for example, one shown in FIG.

FIG. 2 is a diagram showing a basic configuration of compression / expansion of a voice signal.

In FIG. 2, 1 is an encoder, 2 is a decoder, 3 is an encoding DSP, and 4 is a decoding DSP. Further, S1 is an input digital audio signal, S2 is an encoded signal, and S3 is a reproduced audio signal. S1, S
Both 2 and S3 are serial signals.

Here, S1 and S3 may be not only digitized audio signals but also digitized audio signals.

The encoder 1 receives a serial audio signal, fetches the data into an internal buffer, and starts the encoding process when a required number of received data are received.

When the encoding process is completed, the code word is output. The decoder inputs the codeword and starts the decoding process. When the decoding process is completed, the reproduction signal reproduced by the decoding process is output.

[0010]

However, such a conventional data processing circuit has the following problems.

That is, as the bit rate becomes lower, the processing is executed by using several tens to several hundreds of audio samples as one unit. Further, in order to enable real-time processing by the DSP, it is necessary to finish the processing within the maximum dynamic step (which means the maximum number of executable instruction cycles).

Within this maximum dynamic step, it is necessary to execute voice compression processing and I / O interrupt processing. When the frame length becomes long, the number of samples of the input signal taken in the frame also increases, so that the number of steps required for the reception interrupt routine increases and the voice compression process is interrupted. Further, if the number of steps required for the reception interrupt routine increases, the number of steps required for audio compression will be reduced.

As a method for solving this, as shown in FIG. 3, there is a method in which DSP 6 is added to the digital signal processing DSP 5 and the DSP 5 and the DSP 6 perform parallel processing. As a result, real-time processing becomes possible, but there is a problem that the cost is increased because the DSP is expensive.

The present invention allows D to be used without increasing DSP.
An object of the present invention is to provide a data processing circuit capable of reducing the processing amount of SP.

[0015]

A data processing circuit according to the present invention comprises a storage means for temporarily storing an input signal, and a digital signal processor for reading the input signal stored in the storage means for signal processing. Equipped with an input signal
Once stored in the storage means, the digital signal processor is configured to capture the input signal stored in the storage means.

Further, the data processing circuit includes serial / parallel conversion means for converting serial data into parallel data, and the storage means stores the input signal converted into parallel data by the serial / parallel conversion means. It may be configured.

Further, the digital signal processor is
The input signal once stored in the storage means may be configured to be fetched at a predetermined timing for digital signal processing, and the input signal may be a voice signal or an audio signal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing circuit according to the present invention is
It can be applied to a digital signal processor used for a voice codec or an audio codec installed in a transmission device or a multiplexing device.

FIG. 1 is a diagram showing the configuration of a data processing circuit according to an embodiment of the present invention, which is an example applied to a digital signal processor used in a voice codec or an audio codec.

In FIG. 1, a data processing circuit 10 includes a serial / parallel (S / P) converter 11 (serial / parallel conversion means), a memory 12 (storage means) and a DSP.
13 (digital signal processor).

The serial / parallel (S / P) converter 11 converts serial data such as a voice signal into parallel data of a predetermined bit.

The memory 12 temporarily stores the data converted into the parallel data.
M, pseudo static RAM, DRAM, etc.

The DSP 13 has an arithmetic unit mainly having a multiplication function, and controls the arithmetic function and data transfer by firmware to perform signal processing.

Next, the operation of the data processing circuit 10 configured as described above will be described.

Serial / parallel (S / P) converter 11
When a voice or audio input signal is input to the input of, the S / P converter 11 converts the input serial data into parallel data and outputs it to the memory 12.

In the memory 12, the data converted into parallel data is accumulated for a certain fixed interval, and the input data is output in parallel to the DSP 13.

The DSP 13 reads data from the memory 12 at an arbitrary time and performs digital signal processing.

That is, an input signal input at any time is temporarily stored in the memory 12, and the DSP 13 fetches data from the memory 12 at an arbitrary time and performs digital signal processing.

By doing so, the DSP 13 is interrupted by the timing of the input signal,
The problem of interruption of the voice compression process does not occur.

As described above, the data processing circuit 10 according to the present embodiment is a serial / parallel (S / P) converter 11 for converting serial data into parallel data.
And the DSP 12 for temporarily storing the input signal converted into the parallel data and the DSP 13 for fetching the input signal once stored in the memory 12 at a predetermined timing and processing the digital signal. The dynamic steps required for the I / O routine can be reduced, and the S / P converter 11 and the memory 12 enable real-time processing. Furthermore, since it is not necessary to increase DSP, cost can be reduced.

Therefore, if the data processing circuit having such excellent features is applied to a data processing circuit used for a voice codec or an audio codec installed in a transmission device or a multiplexing device, the transmission device or the multiplexing device can be used. The performance of the device can be improved and the cost can be reduced.

The data processing circuit according to the present embodiment can be applied to the above-described transmission device and multiplexing device, but of course the invention is not limited to this, and any digital signal processing can be performed. Needless to say, it can be applied to all devices (for example, video / audio storage / playback device).

Further, in the present embodiment, the serial / parallel (S / P) converter 11 is used, but the present invention is not limited to this, and may be in any form as long as the input signal can be temporarily stored in the memory. May be.

Further, in the above-mentioned configuration, for example, a DRAM can be used as the memory device, but any memory device can be applied, and the same effect can be obtained even if it is a pseudo static RAM. .

Further, D constituting the above data processing circuit
It goes without saying that the types of SP and the like, the number of bits of the memory, etc. are not limited to those in the above-described embodiment.

[0036]

The data processing circuit according to the present invention comprises storage means for temporarily storing an input signal, and a digital signal processor for reading the input signal stored in the storage means for signal processing. Since the signal is temporarily stored in the storage means and the digital signal processor is configured to capture the input signal stored in the storage means, the processing amount of the DSP can be reduced without increasing the DSP. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data processing circuit according to an embodiment to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the data processing circuit.

FIG. 3 is a timing chart for explaining the operation of the data processing circuit.

[Explanation of symbols]

10 data processing circuits, 11 serial / parallel (S
/ P) converter (serial / parallel conversion means), 12
Memory (storage means), 13 DSP (digital signal processor)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Aoyagi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. A storage means for temporarily storing an input signal, and a digital signal processor for performing signal processing by reading the input signal stored in the storage means, wherein the input signal is temporarily stored in the storage means. A data processing circuit for storing, wherein the digital signal processor is configured to capture an input signal stored in the storage means. 2. The data processing circuit according to claim 1, further comprising a serial / serial converter for converting serial data into parallel data.
A data processing circuit comprising parallel conversion means, wherein the storage means is configured to store an input signal converted into parallel data by the serial / parallel conversion means. 3. The digital signal processor comprises:
3. The data processing circuit according to claim 1, wherein the input signal once stored in the storage means is taken in at a predetermined timing and digital signal processing is performed. 4. The input signal is a voice signal or an audio signal, wherein the input signal is a voice signal or an audio signal.
The data processing circuit according to any one of 1.