JPH09292995A - Instruction prefetching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance by abolishing unnecessary instruction prefetch so as to realize an effective instruction prefetch at the time of returning to a main routine from a subroutine. SOLUTION: An address generating part 7 generates the address of an instruction next to an instruction under execution. At the time of detecting a subroutine call instruction, a call instruction detection part 6 allows an address holding part 8 to hold an address generated the the generation part 7. The address held at this time is that of an instruction next to the subroutine call instruction, namely the instruction just after returning from the subroutine. When a return instruction detecting part 5 detects a return instruction in the middle of executing subroutine processing, an address selection part 9 selects the address held by the holding part 8 to use this address as an address for prefetch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction prefetching device, and more particularly to an instruction prefetching device suitable for a subroutine instruction.

[0002]

2. Description of the Related Art Many conventional instruction prefetching devices of this type prefetch an instruction without considering whether or not a subroutine is being processed. On the other hand, JP-A-61-1
96332 describes a method in which a plurality of registers for storing a plurality of prefetched instructions are provided and the instructions after branching to the subroutine in the main routine are stored until the end of the subroutine processing.

[0003]

In many of the conventional instruction prefetching apparatus described above, the instruction prefetched during the processing of the subroutine becomes unnecessary when the return instruction from the subroutine is executed, and the instruction of the main routine is newly provided. Since it is necessary to retake the above, unnecessary instruction prefetch occurs when returning from the subroutine to the main routine, which hinders performance improvement.

Further, the method disclosed in Japanese Patent Laid-Open No. 61-196332 has a problem that it is necessary to prepare a register for storing a plurality of prefetched instructions, which causes an increase in the amount of hardware.

An object of the present invention is to provide an instruction prefetching device which eliminates unnecessary instruction prefetching, realizes effective instruction prefetching, and improves performance when returning from a subroutine to a main routine.

[0006]

The instruction prefetching apparatus of the present invention holds a return address when a main routine is moved to a subroutine, and when a return instruction is detected during instruction prefetching during subroutine processing, The return address held as described above is used as the address for prefetching the instruction.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which comprises a processing device 1 and a storage device 2. Processing device 1
Is an instruction execution unit 3, an instruction buffer 4, a return instruction detection unit 5, a call instruction detection unit 6, an address generation unit 7, an address holding unit 8, an address selection unit 9, a prefetch address generation unit 1.
It consists of 0 and a counter 11.

The memory device 2 has a function of transmitting the data signal DT from an address designated by the address signal AD transmitted by the address selecting section 9, and the address signal AD
And the data signal DT are stored in the instruction buffer 4. The instruction execution unit 3 sequentially fetches instructions from the instruction buffer 4 and executes them. Further, the prefetch address generation unit 10
A prefetch address is generated from the address signal AD and the number of bytes read from the storage device 2 at that time, and is output to the address selection unit 9 as the address signal PAD.

On the other hand, the return instruction detecting section 5 decodes the data signal DT to detect a return instruction, and then sends a return signal RTN to the address selecting section 9 and the counter 11. The call instruction detecting unit 6 decodes the execution instruction signal CMD fetched from the instruction buffer 4, and when detecting the call instruction, sends the call instruction signal CAL to the address holding unit 8 and the counter 11. Also, the address generator 7
Is an execution instruction signal CM fetched from the instruction buffer 4.
An address next to the address of the command being executed is generated from D and the execution address signal BAD, and the generated address signal GAD is sent to the address holding unit 8.

The counter 11 has a size corresponding to the number of words in the address holding unit 8 and counts up when the call command signal CAL is received and counts down when the return signal RTN is received. Further, the value indicated by the counter 11 is sent as the write signal W, and the value minus the counter value is sent as the read signal R.

As described above, the address holding unit 8 writes the generated address signal GAD in the word indicated by the write signal W when receiving the call command signal CAL. Further, the value of the word indicated by the read signal R is transmitted as the holding address signal SAD. In this way, the counter 11 and the address holding unit 8 form a first-in / first-out buffer, and even in the case of a so-called nested state in which a subroutine is further called, the sequence can be dealt with without disturbing the sequence. It is possible.

The address selection unit 9 uses the return signal RTN.
Is inactive, the address signal PAD is selected, and if the return signal RTN is active, the holding address signal SAD is selected and used as the address signal AD.

Now, the operation of prefetching one instruction and then prefetching the next instruction will be described.

Based on the address of the prefetched instruction and the number of bytes of the instruction, the prefetch address generator 10 generates the address signal PAD of the next prefetched instruction. The address signal PAD is selected by the address selection unit 9 under the condition that the return signal RTN is inactive, and is sent to the storage device 2 as the address signal AD. The memory device 2 sends an instruction to the data signal D according to the address signal AD.
It is sent to the processing device 1 as T. In this way, the instruction immediately following the prefetched instruction can be prefetched.

Next, the operation when the instruction executed by the instruction executing section 3 is a subroutine call will be described.

An execution command signal CMD is sent from the command buffer 4 to the command execution unit 3, the call command detection unit 6, and the address generation unit 7. At the same time, the address generator 7 also receives the execution address signal BAD from the instruction buffer 4. The execution command signal CMD and the execution address signal BAD are a command executed by the command execution unit 3 and its address. Based on these, the address generation unit 7 generates an address next to the address of the command being executed, and sends it to the address holding unit 8 as a generated address signal GAD.

On the other hand, the call instruction detection unit 6 decodes the execution instruction signal CMD and activates the call instruction signal CAL when detecting a subroutine call instruction. The address holding unit 8 writes the generated address signal GAD in the word indicated by the write signal W of the counter 11 under the condition that the call command signal CAL is active. What is written at this time is the address of the instruction following the subroutine call instruction, that is, the address of the instruction immediately after returning from the subroutine.

The address holding unit 8 has a call command signal CA.
Call command signal CAL even after L becomes inactive
Holds the written data until is activated again. Further, the data of the word indicated by the read signal R of the counter 1 is sent to the address selection unit 9 by the holding address signal SAD.

Next, the processing when the processing of the subroutine is completed and a return instruction to the main routine is detected will be described.

The return command detecting section 5 inputs the data signal DT immediately after the prefetching, decodes the data signal DT and detects the return command, and activates the return signal RTN. The address selector 9 selects the signal SAD as the address signal AD to be sent to the storage device 2 under the condition that the return signal RTN is active. The memory device 2 sends an instruction to the data signal DT according to the address signal AD.
Is sent to the processing device 1. In this way, the retained address can be used when returning from the subroutine to the main routine, and the next instruction of the subroutine call can be prefetched.

[0022]

According to the present invention, the address of the return destination at the time of shifting from the main routine to the subroutine is held, and when the return instruction is detected during the instruction prefetch during the subroutine processing, the address for the next instruction prefetch is obtained. As
Since the stored return destination address is used, unnecessary instruction prefetching can be eliminated when returning from the subroutine to the main routine, effective instruction prefetching can be realized, and performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 processing device 2 storage device 3 instruction execution unit 4 instruction buffer 5 return instruction detection unit 6 call instruction detection unit 7 address generation unit 8 address holding unit 9 address selection unit 10 prefetch address generation unit 11 counter.

Claims (3)

[Claims] 1. When a return instruction is detected during a prefetch of an instruction during processing of a subroutine, the return address when the main routine is transferred to the sub routine is retained, and the address is retained as the address for the next prefetch of the instruction. An instruction prefetching device characterized by using a return address that has been set. 2. A call instruction detection unit that decodes an executing instruction to detect a subroutine call instruction, and generates an address of an instruction next to the executing instruction based on the address and the number of bytes of the executing instruction. An address generation unit, an address holding unit that holds the generated address when a subroutine call instruction is detected, a return instruction detection unit that decodes a prefetched instruction to detect a return instruction from a subroutine, and the return instruction is detected. 2. The instruction prefetching apparatus according to claim 1, further comprising: an address selecting unit that selects an address held by the address holding unit as a prefetching address for the next instruction. 3. The address holding unit has a size corresponding to the number of words, counts up when the subroutine call instruction is detected, counts down when the return instruction is detected, and a count value is a write signal or a count value minus one. 3. The instruction prefetching device according to claim 2, further comprising a counter for supplying a read signal to the address holding unit.