JPH0934793A - Main memory key controller - Google Patents

Abstract

(57) [Abstract] [Problem] An existing processor having a key function of a main memory is replaced with a general-purpose memory unit (memory
To provide a low-cost, highly reliable data processing system that is configured to be connectable to the control circuit). In a data processing device including a processor with a key function and a memory control unit without a key function, a key base address KB is provided.
The main memory 40 that uses the part divided by the key storage space KSM, the key base address holding means 5 in which KB is entered, and the processor with key function 2
Request holding means 1 for receiving an access request from 0
And the address specified in this access request, and the K
It is provided with an adding means 6 for adding B, and a selective output means 8 for outputting either one of the address output from the adding means 6 and the address designated in the access request according to the content of the access request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory key control device, and more particularly to connecting an existing processor having a main memory key function to a general-purpose low-cost memory unit having no key function at a low cost. The present invention relates to a device capable of providing a highly reliable data processing system.

[0002]

2. Description of the Related Art In a conventional computer, as shown in FIG. 3, the main memory 103 is divided into a plurality of areas A _{0 to} A _n , and keys K _{0 to} K _n are added to the respective areas. And C
When accessing the main memory 103 from the PU 100, C
The keys K _{0 to} K _n are prepared in advance on the PU 100 side, and the key corresponding to the access destination address is sent to the memory control unit 101 together with this address. Memory control unit 101
However, since the key storage 102 for storing the keys K _{0 to} K _n corresponding to the addresses is prepared, the memory control unit 10
In 1, key storage 1 according to the access destination address
02 is accessed to read the key corresponding to the access destination, and this is compared with the key transmitted from the CPU 100,
When they match, an access request from the CPU 100 is issued to the main memory 103.

For example, when the access destination address from the CPU 100 is the area A ₁ , the CPU 100 sends the access destination address as well as the key K ₁ to the memory control unit 101. In the memory control unit 101, for example, upper N bits (KS ₀ , KS ₁ ...
The key storage 102 is accessed by any address of KS _n ), the key is read, and the obtained key K ₁ is compared with the key transmitted from the CPU 100.

The access destination requested by the CPU 100 is
If correct, both keys (K ₁) Is a match,
If it is incorrect, it will not match
Access to the main memory 103 of the
Access and improve system reliability.
Wear.

Such a main memory key controller is conventionally used in a so-called large-sized computer, and a memory controller 101 such as a special key storage 102 is used.
It was necessary to provide a key control circuit.

If such a key control circuit is not provided, it is necessary to rent a key table on the DAT table of the main memory as described in Japanese Patent Laid-Open No. 6-309237, and in this case, the memory is memorized. It was not possible to use a general-purpose low-cost memory unit including a control circuit.

[0007]

By the way, recently, in order to reduce the price of a computer, it is required to connect a general-purpose low-cost memory unit including a memory control circuit. Has no key control circuit.

In the prior art, only a dedicated memory control circuit unit can be connected to a CPU having a key function, and even if a general-purpose low-cost memory control circuit unit capable of covering a large capacity is announced, It was not possible to replace it with a dedicated memory control circuit unit.

Therefore, an object of the present invention is to provide a main memory key control device which can use a general-purpose memory unit including a memory control circuit without a key control circuit.

[0010]

To achieve the above object, according to the present invention, when the memory space of the main memory unit 40 is set to addresses 0 to MAX as shown in FIG. The key storage space KSM is defined as the main storage space MS. This key storage space KSM is, for example, addresses KB to MAX in the memory space.
To access the key storage space KSM, use
The KB is added as a key base address.

Therefore, in the present invention, as shown in FIG. 1A, the input registers 1 and 2 and the output register 3 are provided between the CPU unit 20 with the key function and the general-purpose memory control unit 30 without the key function. 4, a key base address register 5, an adding unit 6, a subtracting unit 7, and multiplexers 8 and 9 are provided. Further, the main memory unit 40 is connected to the general-purpose memory control unit 30.

The key base address KB is held in the key base address register 5. C with key function
Input register 1 provided on the output side of the PU unit 20
Holds a memory access command output from the CPU unit with a key function 20.

Of this command, the address part is directly input to one input end of the multiplexer, and the other input end of the multiplexer 8 is added with the address part and the key base address KB in the adder section 6. The address for the obtained key storage space KSM is input.

When the memory access command set in the input register 1 is a key access, the multiplexer 8 outputs the address for the key storage space KSM input from the adder unit 6 for normal memory access. In the case of, the address input from the input register 1 is output and set in the register 2. The operation code part set in the register 1 is set in the register 2 as it is without passing through the multiplexer 8.

In FIG. 1A, when a memory access command output from the CPU unit 20 with a key function is set in the register 1, a decoding unit (not shown) determines the contents of this command, and a normal command is executed. If it is a memory access command, the address on the input register 1 side is output from the multiplexer 8 and is input to the register 2 as it is and sent to the general-purpose memory control unit 30 having no key function.

If the content of the command is a key access command, the key base address KB set in the key base address register 5 is added in the adding section 6.
The sum of the address on the input register 1 side and the address on the input register 1 side is output from the multiplexer 8, input to the register 2, and sent to the general-purpose memory control unit 30.
Then, the key storage space KSM of the main memory unit 40 shown in FIG. 1B is accessed and, for example, a desired key is read.

As the access result, for example, the read key is output from the general-purpose memory control unit 30 to the output register 3 together with the address of the access destination. This address is input to one of the input terminals of the subtractor 7 and the multiplexer 9, respectively. The output from the subtraction unit 7 is input to the other input terminal of the multiplexer 9. At this time, since the key base address KB is transmitted from the key base address register 5 to the subtraction unit 7, the address input from the output register 3 is the key base address K in the subtraction unit 7.
Only B is subtracted. For example, as described above, when the key storage space KSM is accessed, it is restored to the address set in the input register 1 as a result of this subtraction.

The address set in the output register 3 is decoded by a decoding unit (not shown), and the access destination is the key storage space KSM of the main memory unit 40.
In the case of, the multiplexer 9 outputs the input from the subtractor 7 to the output register 4, and in the case of the main memory space MS,
The address input from the output register 3 is output to the output register 4. Note that the address data is output from the multiplexer 9, and the access result part set in the output register 3 is set in the output register 4 as it is without passing through the multiplexer 9.

Since a desired key can be read from the key storage space KSM of the main memory unit 40 in this manner, whether or not this key matches the key already possessed by the CPU unit 20 with a key function. Or you can compare.

In this way, the key storage space can be provided directly in the memory, and it is not necessary to compare the keys on the memory control unit side.
It is possible to use a general-purpose memory control unit without a key function.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. 2 and other drawings. In FIG. 2, the same symbols as in the other figures indicate the same parts, 1 is an input register, 2 is an input register, 3 is an output register, 4 is an output register, and 5 is a key.
Base address register, 6 adder, 7 subtractor,
8 is a multiplexer, 9 is a multiplexer, 10 is a decryption unit, 11 is a decryption unit, 20 is a CPU unit with a key function,
Reference numeral 30 is a general-purpose memory control unit without a key function, 40 is a main memory unit, and 50 is a service processor.

The input register 1 outputs a memory access command from the CPU unit 20 with a key function. In this memory access command, the address of the access destination and the OP code indicating the access content are written.

A memory access command for the general-purpose memory control unit 30 having no key function is set in the input register 2, and the operation code portion from the input register 1 is directly set as the operation code portion. . When the key storage space KSM of the main memory unit 40 is accessed, the address output from the adder 6 is set in the address portion. However, when accessing the main memory space MS,
The address portion of the input register 1 is set.

In the output register 3, the access result to the main memory unit 40 output from the general-purpose memory control unit 30 having no key function is set together with the access destination address.

The output register 4 outputs the access result to the main memory unit 40 to the CPU unit 20 with a key function, and the access result portion from the output register 3 is set as it is. When the key storage space KSM of the main memory unit 40 is accessed, the address output from the subtraction unit 7 is set in that address portion.
However, when the main memory space MS is accessed, the address portion of the output register 3 is set.

The key base address register 5 holds the key base address KB shown in FIG. 1 (B). This key base address KB
Are set by the service processor 50, for example, at system startup. Of course, the present invention is not limited to this. For example, an operator may input from a keyboard or the like.

The adder 6 is provided with the key base address KB set in the key base address register 5.
And the address written in the address portion of the command set in the input register 1 are added, and the added value is transmitted to one of the input ends of the multiplexer 8.

The subtracting section 7 subtracts the key base address KB from the address set in the output register 3, and the subtracted value is transmitted to one of the input ends of the multiplexer 9.

The multiplexer 8 selects and outputs either the added value of the address transmitted from the adder 6 or the address transmitted from the input register 1. In this case, when the command set in the input register 1 is a key access command, the added value transmitted from the adder unit 6 is output, and in other cases, the address transmitted from the input register 1 is output. To do.

The multiplexer 9 selects and outputs either the subtracted value of the address transmitted from the subtractor 7 or the address transmitted from the output register 3. In this case, when the address set in the output register 3 is the key storage space KSM, the subtraction value transmitted from the subtraction unit 7 is output, and in other cases, the address transmitted from the output register 3 is output. To do.

The decoding section 10 identifies whether or not the command set in the input register 1 is a key access command by decoding the operation code portion of the command. Whether or not the command is a key access command. An identification signal indicating that is output to the multiplexer 8.

The decoding unit 11 checks the address part of the key storage space KSM to see if the access result set in the output register 3 is for the key storage space KSM.
It is identified by judging whether it is larger than the base address KB. Therefore, the key base address KB is transmitted from the key base address register 5. That is, if the address entered in this address part is in the key storage space KSM,
It is determined that the access result is for the key storage space. In this way, it is determined whether or not it is for the key storage space KSM, and the identification signal corresponding to this is output to the multiplexer 9.

When the memory is accessed, the CPU unit with key function 20 divides the memory into a plurality of areas, holds a key for each of the areas, and corresponds to the area of the access destination at the time of memory access. The key is read from the key storage, and a memory access is executed when it matches the one held.

General-purpose memory control unit 30
When there is an access request to the main memory unit 40 from the CPU unit 20 with a key function, it processes the request and outputs the access result together with the access destination address, and has no key function. It consists of things.

The main memory unit 40 is, for example, a DRA.
A main memory composed of M, a main memory space MS and a key storage space K by a key base address KB.
It is divided into SB. The key storage space KSM stores the same keys K ₀ , K _1, ... K _{n as} those held by the CPU unit with a key function 20. These keys K ₀ , K _1, ... K _n are offset values KS ₀ , KS _1, ... Of the key storage space KSM.
It is written in KS _n . The offset values KS ₀ , KS _1, ... KS _n are the addresses KS ₀ , KS _1, ... KS of the key storage 102 shown in FIG.
It matches _n .

By the way, the CPU unit with key function 20
When accessing the key storage space KSM from
The offset value KS ₀ as an access destination address is added to the command output from the CPU unit 20 with the key function.
~ Fill in one of KS _n . And this offset value K
By adding the key base address KB to Si (KSi + KB), the key storage space K
The SM is accessed and, for example, the key Ki is read.

Next, the operation of the present invention will be described. (1) When accessing the key storage space KSM
If, for example, key K₁When reading out, CPU with key function
Unit 20 uses KS as the address₁Enter
Key access piece with lead entered as the access mode
The input register 1 is transmitted to the input register 1. This adds 6
Is the address KS ₁Key base address KB to
Added (KS₁+ KB) is output and the multiplexer 8
It is applied to one input terminal. In addition to the multiplexer 8
The adder set in the input register 1 is provided at one input end.
Less KS₁Is applied as it is.

At this time, the decoding section 10 decodes the access command set in the input register 1 and recognizes that this is a key access command, and an identification signal indicating this, for example, "1" is sent to the multiplexer 8. Output.
In response to this, the multiplexer 8 transmits the (KS ₁ + KB) transmitted from the adder 6 to the address portion of the input register 2. At this time, the operation code portion of the input register 1 is directly transmitted to the operation code portion of the input register 2.

In this way, in the case of the key access command, the input register 2 has the key base address at the address of the access command set in the input register 1.
The access command to which the address KB is added is set.

The access command set in the input register 2 is the general-purpose memory control unit 3
0 is transmitted. The general-purpose memory control unit 30 decodes this and accesses the address (KS ₁ + KB) of the main memory unit 40, that is, the key storage space KSM and reads the key K ₁ .
Then, the output data obtained by adding the access destination address (KS ₁ + KB) to the key K ₁ obtained as a result of this access is sent to the output register 3.

When the decoding section 11 recognizes that the address of the output register 3 is an access to the key storage space KSM, it outputs an identification signal indicating this, for example, "1" to the multiplexer 9. In response to this, the multiplexer 9 is transmitted from the subtractor 7 [(KS ₁ +
KB) -KB], that is, the address KS ₁ of the key access command set in the input register 1 is transmitted to the address portion of the output register 4.

At this time, the access result part of the output register 4
In addition, the access result of the output register 3, that is, the key K
₁Is transmitted as is. This way the output register
The key K obtained as the access result is 4₁And the input register
Address KS described in the command transmitted to 1₁
Is set and transmitted to the CPU unit 20 with key function.
It is. In the CPU unit 20 with key function,
Key K read ₁Already owned by
By comparing the key and checking for a match or mismatch,
And determine whether the area you are going to access is accurate.
Can be.

(2) When accessing the main memory space MS When accessing the main memory space MS, a CPU with a key function
The unit 20 writes a value equal to or less than the key base address KB, which is an access destination, as an address, and transmits a read command in which, for example, read is written as an access mode, to the input register 1.

At this time, the decoding section 10 decodes the access command set in the input register 1 to recognize that it is not a key access command, and outputs an identification signal indicating this, for example, "0" to the multiplexer 8. In response to this, the multiplexer 8 outputs the address transmitted from the input register 1 and transmits it to the address portion of the input register 2. At this time, since the operation code portion of the input register 1 is directly transmitted to the operation code portion of the input register 2, the command set in the input register 1 is set in the input register 2 as it is.

The command set in the input register 2 in this manner is the general-purpose memory control unit 3
0 transmitted to, for example, the main memory space MS based on this
Is read, and the general-purpose memory control unit 30 outputs the read result and the access destination address to the output register 3.

When the decoding section 11 recognizes that the address of the output register 3 is not for the key storage space KSM, it outputs an identification signal indicating this, for example, "0" to the multiplexer 9. In response to this, the multiplexer 9 outputs the address transmitted from the output register 3 and transmits it to the address portion of the output register 4.

At this time, the access result portion of the output register 3 is directly transmitted to the access result portion of the output register 4. In this way, the data set in the output register 3 is set in the output register 4 as it is. As a result, the CPU unit 20 with a key function can access the main storage space MS, and can perform processing using, for example, the data obtained by the read command.

In the above description, an example in which the key base address KB is written in the key base address register 5 by the service processor 50 has been described.
The present invention is of course not limited to this. For example, the operator may input the data using a keyboard or the like.

Further, in the above description, the case where the number of the CPU unit 20 with the key function is one has been described, but the present invention is not limited to this, of course, and a plurality of CPU units with the key function are used. It can also be applied to a processor system.

In the above description, the general-purpose memory control
Although the example in which the address is added to the output data from the unit has been described, it is not always necessary to add the address to the output data. For example, in the case of a multiprocessor system, if an address is added to the output data, it is checked whether the processor requesting access has requested that the output data output on the bus is the one requested by itself. Although it can be determined, another method, for example, the ID code of the access source processor may be added instead of the address.

In the above description, a general-purpose memory unit having no key function, which is a combination of the general-purpose memory control unit 30 having no key function and the main memory unit 40, can be used.

According to the present invention, the main memory unit can be divided into the main storage space and the key storage space by the key base address, and the key storage can be easily performed by the general-purpose memory control unit having no key function. Since the space can be made accessible, the computer system can be configured with a key function by using a low-cost general-purpose memory control unit without key function.
Since it can be configured by connecting to a PU unit, for example, even when a write request is made from an input / output device connected via a channel, a computer system having high reliability by confirming the key Can be configured at a low price.

Of course, the highly reliable computer system is constructed by using a general-purpose low-cost memory unit having no key function, which is a combination of a general-purpose memory control unit having no key function and a main memory unit. can do.

When the memory capacity of a general-purpose memory unit having no key function is changed, the set value set in the key base address register 5 can be changed.

[0055]

According to the first aspect of the present invention,
Since the CPU unit with key function can be connected to a general-purpose low-cost memory unit without key function,
It is possible to inexpensively configure a computer system using a memory unit having no key function without lowering the reliability of the system while making the most of the key function of the CPU.

According to the present invention described in claim 2, it is possible to change the key base address very easily. Therefore, even if the memory capacity is changed, it can be easily dealt with. .

[Brief description of drawings]

FIG. 1 shows a principle configuration diagram of the present invention.

FIG. 2 shows a configuration diagram of an embodiment of the present invention.

FIG. 3 shows an explanatory view of a conventional example.

[Explanation of symbols]

 1 Input Register 2 Input Register 3 Output Register 4 Output Register 5 Key Base Address Register 6 Addition Unit 7 Subtraction Unit 8 Multiplexer 9 Multiplexer 10 Decoding Unit 11 Decoding Unit 20 CPU Unit with Key Function 30 General-purpose Memory Control Unit 40 Main Memory unit 50 Service processor

Claims (2)

[Claims] 1. A data processing device comprising a processor with a key function and a memory control unit without a key function, wherein a portion divided by a key base address is a key
A main memory used as a storage space, a key base address holding means in which a key base address is written, a request holding means for receiving an access request from a processor with a key function, and an address designated by this access request And the key
And a selection output unit for outputting one of the address output from the addition unit and the address designated in the access request according to the content of the access request. Main memory key control device characterized by. 2. The main memory key control apparatus according to claim 1, wherein the key base address is changed when the main memory capacity is changed.