JPH0936711A - Scramble signal generating circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a signal generation circuit for generating scrambled data that can be scrambled without converting the format of byte data. In a scramble signal generation circuit for outputting scramble data to be added to digital data,
n registers 10 to 19 and m 1-bit adder circuits 30 to 37 to which a plurality of outputs of this register are combined and input
(N ≧ m: n, m is an integer) and each output of the 1-bit adder circuit is input to m registers 12 to 19, and the output of the 1-bit adder circuit is not input. 1
The outputs of different registers 18 and 19 are input to 0 and 11, and the outputs of m registers 10 to 17 of the n registers are simultaneously output as scramble data for m bits. According to the input of the byte clock 52, a scramble signal for m bits is output at one time, and scramble processing can be performed without using a high speed bit clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble circuit for generating a scramble signal in order to disperse the power spectrum of digital data to be recorded / reproduced,
In particular, it makes it possible to generate a scramble signal in byte units.

[0002]

2. Description of the Related Art In recent years, recording / reproduction of digital signals has been carried out by using floppy disks, hard disks, and
It is used in a wide range of fields such as compact discs for recording and reproducing PCM signals and digital tape recorders.

In these recording / reproducing, a recording / reproducing system is used in which a known scramble signal is added to a recording signal to record on a recording medium, and at the time of reproducing, descrambling to obtain reproduced data. This is a measure for preventing the recording signal of the specific pattern from being continuously recorded on the recording medium. For example, when “0” is continuously input data, if it is recorded as it is, the recording signal becomes a specific signal. It is fixed to the pattern, as a result, it becomes difficult to extract the clock information at the time of reproduction, and the power spectrum of the recording signal is concentrated at a specific frequency, causing distortion in the reproduced waveform due to the influence of the DC component, etc. A phenomenon such as deterioration of the error rate of the read data occurs. The addition of the scramble signal is performed to avoid such a bad effect.

As shown in FIG. 3, a conventional scramble signal generating circuit for generating this scramble signal receives a shift register 80 for shifting data by 1 bit each time a bit clock 50 is input and a preset signal 51. A preset circuit 81 that sets initial data in the shift register 80, and a 1-bit addition circuit that adds the data output from the shift register 80 and the data extracted from the middle (d1) of the shift register 80 (that is, exclusive logic). Summing circuit) 82, and the output of the adding circuit 82 is fed back to the shift register 80.

The output 83 of the shift register 80 is also input to a 1-bit adder circuit 84, and the adder circuit 84 performs an exclusive logic of the input serial data 71 and the scramble signal 83 output from the shift register 80. The sum is calculated and the result is output from the serial data output terminal 72.

In order to simplify the description, the number of bits of the shift register 80 is 10.

In this scramble signal generating circuit, first, when a preset signal 51 for instructing the setting of initial data is input, the preset circuit 81 executes the initial setting of the shift register 80. In this example, the initial setting is "0000
10-bit data of 000001 "is a shift register
Set to 80.

Next, when the bit clock 50 is input, the data in the shift register 80 is shifted right by 1 bit. At this time, the data newly input to the left end of the shift register 80 is the output signal of the addition circuit 82, and since d0 and d1 of the shift register 80 are input to the addition circuit 82,
In this example, d0 + d1 = 1 is a new shift register 80
Will be entered. It should be noted that this addition is performed by an exclusive OR circuit.

The contents of the shift register 80 from the time of initial setting are as follows when the bit clock is changed.

00100001 1000000000 010000000 0010000000 001000000 0000100000000 00000010000 0000001000 0000000000100 0000000010 1000000001 1100000000 0110000000 0011000000 0001100000 00001010000 80000011000 0000100100 000010110 10080001110 01000010001 The adder circuit 84 sequentially adds the output of the scramble signal generation circuit section and the input serial data 71, and outputs the scrambled serial signal to the data output terminal 72. This signal is recorded on the recording medium together with the synchronization signal.

When reproducing, the same data as the input data 71 can be reproduced by synchronizing the timing with the synchronization signal at the time of reproduction and by performing the exclusive logical addition of the same scramble signal as at the time of recording again.

This scramble circuit outputs the scramble signal 83 in bit units according to the bit clock. Therefore, it is also necessary to convert the byte-unit data to be scrambled into the adder circuit 84 bit by bit, in the form of serial data.

Therefore, around the scramble circuit, as shown in FIG. 4, a parallel / serial converter 61 for converting the input 8-bit parallel data 53 into serial data.
And the serial output 72 output from the scramble circuit 62
And a serial-parallel converter 63 for converting the data into 8-bit parallel data 54 and outputting the parallel data 54. The byte-clock 52 and the bit clock 50 are given to the parallel-serial converter 61 and the serial-parallel converter 63 as operation clocks. To be

When scrambling the parallel data 53, the parallel / serial converter 61 temporarily fetches the 8-bit parallel data 53 with the byte clock 52 for each input data unit and stores it in the bit clock 50 for each bit. It is converted to serial data 71 at a timing and output to the scramble circuit 62.

The scramble circuit 62 scrambles the serial data 71 by the procedure described above and outputs it as the serial data 72. The serial-parallel converter 63 sequentially stores the serial data 72 output in synchronization with the bit clock 50 in the internal register, and when the data of the register is collected for 8 bits, the byte clock 52
Output as parallel data 54.

[0016]

As described above, since the conventional scramble signal generation circuit is configured to output the scramble signal 83 bit by bit in accordance with the high speed bit clock 50, the data to be scrambled is serialized. It is necessary to change the form of the data 71 and to give it to this circuit bit by bit. Therefore, in order for this circuit to transfer data to and from other blocks that are often processed in byte units, a circuit for converting the format of data is required, which causes a problem that the circuit scale becomes large. is there.

When the bit clock 50 is used,
There is a problem that a high-speed clock having a frequency of at least 8 times as high as that of the byte unit processing is required, and a circuit with high precision is required accordingly.

The present invention solves the above-mentioned conventional problems, and scramble signal generation for generating scrambled data capable of performing scramble processing on data in byte units without performing format conversion. It is intended to provide a circuit.

[0019]

Therefore, in the present invention, in a scramble signal generating circuit for outputting scramble data to be added to digital data, n registers and a plurality of outputs of the registers are combined and input. M 1-bit adder circuits (n ≧ m: n, m is an integer) are provided, each output of the 1-bit adder circuit is input to m registers, and the output of the 1-bit adder circuit is not input n
-Input the output of different register to m registers,
The outputs of the m registers out of the n registers are simultaneously output as scrambled data for m bits.

[0020]

Therefore, the scramble signal for m bits can be output at a time from the outputs of the n registers, and the scramble processing can be performed without using a high speed bit clock.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A scramble signal generating circuit according to an embodiment of the present invention has ten registers 10 to 19 as shown in FIG.
With a memory circuit 1, an OR circuit 20 and AND circuits 21 to 29
And a preset circuit 2 having eight 1-bit addition circuits
And an adder circuit 3 having 30 to 37. Further, the byte clock 52 is input to each register 10 to 19 of the memory circuit 1, and the preset signal 51 is input to the logical sum circuit 20 and the logical product circuits 21 to 29 of the preset circuit 2 (however, the logical product is The preset signal is inverted and input to the circuits 21 to 29).

Around the scramble signal generating circuit, there is an adder circuit 42 for receiving the output of the scramble signal generating circuit 4, as shown in FIG. This adder circuit 42
Is composed of eight 1-bit adder circuits arranged in parallel, and is specifically composed of eight EXOR gates.

When the byte clock 52 is input, the scramble signal generating circuit 4 outputs an 8-bit scramble signal 41 in synchronization with it. The adder circuit 42 performs an exclusive OR operation for each bit of the 8-bit scrambled signal and the input 8-bit parallel data 53 to obtain 8-bit scrambled data in which the output of each bit is collected. Output from the output terminal 54.

Storage circuit 1 of scramble signal generating circuit 4
Each of the registers 10 to 19 in 1 outputs the held data in response to the input of the byte clock 52. Here, the data output from the register 10 is d0, the data output from the register 11 is d1, the data output from the register 12 is d2,
If the data output from the register 19 is d9, the data from d0 to d7 in this is output to the adder circuit 42 as an 8-bit scramble signal 41. The outputs of the registers 10 to 19 are, as shown in FIG. 1, added to the adder circuit 3 or the preset circuit 2 of the scramble signal generation circuit.
Feedback on some of the. That is, the output d0 of the register 10 is sent to the 1-bit addition circuit 30 of the addition circuit 3
The output d1 of 11 is the 1-bit addition circuits 30 and 31 of the addition circuit 3.
The output d8 of the register 18 is input to the 1-bit addition circuit 37 of the adder circuit 3 and the logical sum circuit 20 of the preset circuit 2, and the output d9 of the register 19 is input to the logical product circuit 21 of the preset circuit 2.

By defining the feedback destination of the output of each register 10 to 19 in this way, eight registers 10
The outputs from 17 to 17 are the same as the scramble signal 83 continuously output from the shift register 80 of the conventional scramble signal generation circuit (FIG. 3) over the 8-bit clock.

This point will be described in more detail.
The scramble signal generation circuit of FIG. 3 shifts the addition value (exclusive OR) of the output value of the 10th register and the output value of the 9th register of the shift register 80 having the bit number (n) of 10. This is because the configuration is such that feedback is made to the register 80 (this can be generally expressed as a shift register which feeds back X ⁿ + X ⁿ⁻¹ ) and the output from this shift register 80 is output as the scramble signal 83. Assuming that the data stored in the shift register 80 is d9, d8, ..., D1, d0 in this order, the scramble signal output 83 changes as follows each time the bit clock is input.

[0027] 0 d0 1 d1 2 d2 3 d3 4 d4 5 d5 6 d6 7 d7 8 d8 9 d9 10 d0 + d1 11 d1 + d2 12 d2 + d3 13 d3 + d4 14 d4 + d5 15 d5 + d6 16 d6 + d7 17 d7 + d8 18 d8 + d9 19 d9 + d0 + d1 20 d0 + d1 + d1 + d2 21 d1 + d2 + d2 + d3:: The Thus, if the contents of the shift register 80 at a certain point of time are known, the subsequent scramble signal output 83 can be calculated in principle.

The circuit shown in FIG. 1 performs this calculation with the minimum number of circuits. When the preset signal 51 is input to this circuit, the OR circuit 20 of the preset circuit 2 outputs 1
However, 0 is output from the other AND circuits 21 to 29, and the initial data corresponding to "0000000001" is stored in the registers 10 to 19 of the storage circuit 1. This initial data setting is the same as the initial data setting in the shift register 80 in the conventional scramble signal generation circuit.
The OR circuit of the preset circuit 2 is arranged corresponding to the registers 10 to 19 that set 1 as the initial data. For example, when the initial data is "0000000010", the positions of the logical sum circuit 20 and the logical product circuit 21 of the preset circuit 2 are exchanged.

The data stored in the registers 10 to 19 of the memory circuit 1 are output by the input of the byte clock 52.
Assuming that the outputs of the registers 10 to 19 at a certain point are d0 to d9, 8 bits d0 to d7 of these are output to the adder circuit 42 as scrambled data 41, and the outputs d0 of the registers 10 to 19 are also output. To d9 are fed back, and the adder circuit 3 and the preset circuit 2 of the scramble signal generating circuit are fed back.
And part of. As a result, the register of the memory circuit 1
Next, d8 is set as the next data in 10, and similarly, d9 is stored in the register 11, d0 + d1 is stored in the register 12, d1 + d2 is stored in the register 13, and d5 + is stored in the register 17.
d6, d6 + d7 are set in the register 18, and d7 + d8 are set in the register 19. When the next byte clock 52 is input, d8, d9, d0 + d1, ..., d5 + d6 set in the registers 10 to 17 are output as scrambled data for 8 bits, and the outputs of the registers 10 to 19 are scrambled. It is fed back to a part of the adding circuit 3 and the preset circuit 2 of the signal generating circuit.

Therefore, for example, paying attention to the register 13, the exclusive OR of d9 + d0 + d1 obtained by adding d9 output from the register 11 and d0 + d1 output from the register 12 is set as the next output data. Become. The same setting is performed in other registers, and the next byte clock input causes registers 10 to 17 to
As scrambled data for 8 bits, d6 + d7,
d7 + d8, d8 + d9, d9 + d0 + d1, d0 + d
1 + d1 + d2, ..., D3 + d4 + d4 + d5 are output.

In the scramble signal generating circuit of the embodiment, the conventional shift register calculates the bit clock 50 by changing the bit clock 50 eight times by repeating such processing.
The scrambled data for bits can be calculated and output at one time when the byte clock changes.

As described above, in the scramble signal generating circuit of the embodiment, the scramble processing can be realized without using the parallel-serial converter or the serial-parallel converter, so that the total circuit scale is the conventional one (see FIG. 4). ) Is smaller than. Also, since it can be processed in 8-bit units,
Even when the scramble processing is realized by software such as a microcomputer, it is possible to reduce the number of processing steps by using the algorithm of the scramble signal generating circuit of the present invention.

In the embodiment, the registers 10 to 19 of the memory circuit 1 are
The number n of m = 10 and the number m of the 1-bit addition circuits 30 to 37 of the addition circuit 3 = 8 are described, but the values of n and m are not limited to this number. Number of 1-bit addition circuits m
Is set to the same number as the number of bits of the scrambled signal to be output. Then, the outputs of the registers 10 to 19 corresponding to the added value fed back in the shift register 80 are input to the respective 1-bit addition circuits, and the outputs of the respective 1-bit addition circuits are in the order of the storage circuit 1. To the m registers located at.

The outputs of the mn registers of the storage circuit 1 in the order are input to the nm registers in the order of the storage circuit 1 as they are. This is because, when the scramble signal is output in the previous round, the signals that have not been output are output in the higher order in the next round. Then, the outputs of the m registers in the previous order of the storage circuit 1 are simultaneously output as m-bit scramble signals.

When changing the values of n and m, the circuit configuration is changed in accordance with this idea. For example, n = 15, m
In the case of = 8, the circuit has a form in which five circuit parts including the AND circuit 21 and the register 11 in FIG. 1 are added. When n = 8 and m = 8,
This is a circuit in which the logical sum circuit 20 and the register 10, the logical product circuit 21 and the register 11 are deleted. Also, n = 10, m =
In the case of 4, that is, when outputting a scrambled signal in units of 4 bits, the 1-bit addition circuit of the addition circuit 3
It is reduced to only 4 of 37, and these 1-bit addition circuits 34-
The outputs of the registers 10 to 13 are combined and input to 37, and the outputs of the registers 14 to 19 are input to the logical sum circuit 20 and the logical product circuits 21 to 25 of the preset circuit 2. Then, the scrambled output is taken out from the registers 10 to 13 of the storage circuit 1.

Further, this scramble signal generating circuit is
By changing the input to the 1-bit adder circuit of the adder circuit 3, a scramble signal corresponding to a shift register for feedback other than X ⁿ + X ^n-1 can be generated in parallel.

[0037]

As is apparent from the above description of the embodiments, the scramble signal generating circuit of the present invention can generate scramble data in units of 8 bits or 4 bits. Therefore, it is possible to scramble the 8-bit or 4-bit unit data, which is often output from other blocks, as it is without converting the format. As a result, a circuit for converting the format of data becomes unnecessary, and the circuit scale as a whole can be reduced.

Further, this scramble processing can be processed at a much lower speed than the bit clock, and strict accuracy is not required for the circuit configuration.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a scramble signal generation circuit according to an embodiment of the present invention,

FIG. 2 is a block diagram of a scramble processing circuit using the scramble signal generation circuit of the embodiment,

FIG. 3 is a schematic diagram of a conventional scramble signal generation circuit,

FIG. 4 is a block diagram of a scramble processing circuit using a conventional scramble signal generation circuit.

[Explanation of symbols]

 1 memory circuit 2, 81 preset circuit 3, 42, 82, 84 adder circuit 4, 62 scramble signal generation circuit 10-19 register 20 logical sum circuit 21-29 logical product circuit 30-37 1-bit adder circuit 41, 83 scramble signal Output 50 Bit clock input 51 Preset signal input 52 Byte clock input 53 Parallel data input 54 Parallel data output 61 Parallel / serial conversion circuit 63 Serial / parallel conversion circuit 71 Serial data input 72 Serial data output 80 Shift register

Claims (1)

[Claims] 1. A scramble signal generation circuit for outputting scramble data to be added to digital data, wherein n registers and m 1-bit adder circuits (n where n outputs are combined and input) are combined. ≧ m: n,
m is an integer), each output of the 1-bit adder circuit is input to m registers, and the output of the 1-bit adder circuit is not input n−
The scramble signal generation, wherein the outputs of the different registers are input to the m registers and the outputs of the m registers of the n registers are simultaneously output as scramble data for m bits. circuit.