JPH0936717A - Signal detection circuit - Google Patents

Abstract

(57) 【Abstract】 PROBLEM TO BE SOLVED: To detect only a pulse signal generated at a specified timing among pulse signals included in an input signal. SOLUTION: A pulse signal is output from a buffer 14 when the voltage of an input signal 100 exceeds a threshold voltage, the pulse signal is delayed by a delay element 16 for a predetermined time, and the output pulse of the delay element 16 and the buffer 14 are delayed. AND gate 18 calculates the logical product of the output pulses of
When the output pulse of the gate 18 overlaps with the timing signal on the time axis, the flip-flop 22 outputs a trigger signal via the AND gate 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit, and more particularly to a signal detection circuit suitable for detecting whether or not an input signal contains a pulse signal having a predetermined time width or more.

[0002]

2. Description of the Related Art As a conventional signal detection circuit, for example,
The one described in JP-A-63-164522 is known. This signal detection circuit includes a delay circuit 72, an inverter 74, a NAND gate 7 as shown in FIG.
6 is provided. This signal detection circuit is shown in FIG.
As shown in, when the pulse signal 200 is input to the input terminal 70 as an input signal, the delay circuit 72 delays the pulse signal 200 for a certain period of time, and then the inverter 74 generates a negative logic pulse signal 202, and the NAND gate At 76, the logical product of the pulse signal 200 and the pulse signal 202 is calculated, and the pulse signal 204 having a prescribed pulse width is detected.

Another signal detection circuit shown in FIG. 9 is known. This signal detection circuit includes a delay circuit 82, an inverter 84, a delay time selection circuit 86, an NA.
It is configured to include an ND gate 88. As shown in FIG. 10, when the pulse signal 206 is input to the input terminal 80 as an input signal, the signal detection circuit delays the pulse signal 206 by a certain time in the delay time selection circuit 86 to form a pulse signal 208, Delay circuit 8 for pulse signal 208
A pulse having a pulse width equal to or longer than a specified delay time is generated by delaying a predetermined time by 2 and generating a negative logic pulse signal 210 by the inverter 84 and ANDing the pulse signals 206, 208, 210 by the NAND gate 88. The signal 212 can be detected.

[0004]

The conventional signal detecting circuit can detect a pulse signal when the input signal includes a pulse signal having a certain time width or more or a certain time width or less. It is not possible to determine whether the detected pulse signal is a normal pulse signal or noise. That is, when this signal detection circuit is mounted on a system, it is impossible to determine whether the pulse signal detected by the signal detection circuit is a pulse signal that causes a problem in the circuit operation of the system or a pulse signal that does not cause a problem.

Therefore, an object of the present invention is to provide a signal detection circuit capable of detecting only a pulse signal generated at a specified timing among pulse signals included in an input signal.

[0006]

According to a first aspect of the invention, (a) when the input signal exceeds the set voltage, a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage is output. The buffer means, (b) the delay means for delaying the pulse signal from the buffer means by the set time, and (c) the pulse signal from the buffer means and the pulse signal delayed by the delay means are compared to determine that both pulse signals have time. Noise detection means for outputting a noise detection pulse signal having a pulse width according to the overlapping time when overlapping on the axis; and (d)
The signal detection circuit is provided with a trigger signal output means for outputting a trigger signal on the condition that the timing signal generated at the designated timing and the noise detection pulse signal overlap on the time axis.

That is, according to the first aspect of the invention, when the pulse signal exceeding the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time, and the pulse signal and the input signal delayed by the set time are added. When the pulse signals of the two are overlapped on the time axis by comparing with the superimposed pulse signal, a noise detection pulse signal is generated assuming that the pulse signal of the set time width or more is superimposed on the input signal,
It is characterized in that the trigger signal is output on condition that the noise pulse signal overlaps with the timing signal on the time axis.

According to the second aspect of the invention, (a) buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage when the input signal is equal to or lower than the set voltage; (B) The delay means for delaying the pulse signal from the buffer means by the set time and (c) the pulse signal from the buffer means and the pulse signal delayed by the delay means are compared, and both pulse signals are overlapped on the time axis. Sometimes noise detection means that outputs a noise detection pulse signal with a pulse width according to the overlapped time, and (d) the timing signal generated at the specified timing and the noise detection pulse signal are overlapped on the time axis And a trigger signal output means for outputting a trigger signal to the signal detection circuit.

That is, according to the second aspect of the present invention, when the pulse signal having the voltage equal to or lower than the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time and is superimposed on the pulse signal delayed by the set time and the input signal. When the pulse signals of both are overlapped on the time axis by comparing with the pulse signal generated, the noise detection pulse signal is generated as if the pulse signal of the set time width or more is superimposed on the input signal,
It is characterized in that the trigger signal is output on condition that the noise pulse signal overlaps with the timing signal on the time axis.

According to the third aspect of the invention, (a) first buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage when the input signal exceeds the set voltage; (B) Second buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage when the input signal is equal to or lower than the set voltage.
(C) first delay means for delaying the pulse signal from the first buffer means for a first set time, (d) second delay means for delaying the pulse signal from the second buffer means for a second set time, and (e) The first noise detection pulse having a pulse width corresponding to the overlapped time when the pulse signals from the one buffer means and the pulse signal delayed by the first delay means are compared with each other When the first noise detecting means for outputting a signal and (f) the pulse signal from the second buffer means and the pulse signal delayed by the second delay means are compared, and both pulse signals overlap on the time axis. The second noise detection means for outputting the second noise detection pulse signal having the pulse width corresponding to the overlapping time, and the timing signal generated at the designated timing (g) and the first noise detection pulse signal On condition that duplicate on Axis 1
First trigger signal output means for outputting a trigger signal,
(H) The signal detection circuit includes a second trigger signal output means for outputting a second trigger signal on condition that the timing signal generated at the designated timing and the second noise detection pulse signal overlap on the time axis. Let

That is, according to the third aspect of the invention, when the pulse signal exceeding the set voltage is superimposed on the input signal, the pulse signal is delayed for the first set time, and
When the pulse signal delayed by the set time and the pulse signal superimposed on the input signal are compared and both pulse signals overlap on the time axis, the pulse signal of the set time width or more is superimposed on the input signal. Is generated, and the first trigger signal is output on condition that the noise pulse signal overlaps with the timing signal on the time axis. When the pulse signal is superimposed, the pulse signal is delayed by the second set time, and the pulse signal delayed by the set time and the pulse signal superimposed on the input signal are compared to determine that both pulse signals are on the time axis. When it overlaps with, the second noise detection pulse signal is generated assuming that the pulse signal of the set time width or more is superimposed on the input signal, and this noise pulse signal is It is characterized by outputting a second trigger signal on the condition that overlap on the signal and the time axis.

According to a fourth aspect of the invention, (a) buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage when the input signal exceeds the set voltage; ) A delay means for delaying the pulse signal from the buffer means by a set time, and (c) a pulse signal having a time width or more set by the delay means by comparing the pulse signal from the buffer means with the pulse signal delayed by the delay means. A pulse detection means for detecting the above, and (d) a trigger signal output means for outputting a trigger signal on the condition that the timing signal generated at the specified timing and the pulse signal detected by the pulse detection means overlap on the time axis. Is provided in the signal detection circuit.

That is, when the pulse signal exceeding the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time and the pulse signal and the input signal delayed by the set time are added. When the pulse signals of the two are overlapped on the time axis by comparing with the superimposed pulse signal, the pulse signal is generated assuming that the pulse signal of the set time width or more is superimposed on the input signal. The feature is that the trigger signal is output on condition that it overlaps with the timing signal on the time axis.

According to a fifth aspect of the invention, (a) buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage when the input signal is equal to or lower than the set voltage; (B) A delay means for delaying the pulse signal from the buffer means by a set time, and (c) a pulse signal having a time width or more set by the delay means by comparing the pulse signal from the buffer means with the pulse signal delayed by the delay means. A pulse detection means for detecting a signal, and (d) a trigger signal output means for outputting a trigger signal on condition that the timing signal generated at the designated timing and the pulse signal detected by the pulse detection means overlap on the time axis. And the signal detection circuit.

That is, according to the invention of claim 5, when a pulse signal having a voltage equal to or lower than a set voltage is superimposed on the input signal, the pulse signal is delayed by a set time and is superimposed on the pulse signal delayed by the set time and the input signal. When both pulse signals overlap on the time axis, the pulse signal is generated as if the pulse signal of the set time width or more is superposed on the input signal. The feature is that the trigger signal is output on condition that the signal and the signal overlap on the time axis.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to Examples.

FIG. 1 is a block diagram of a signal detection circuit according to an embodiment of the present invention. In FIG. 1, the signal detection circuit includes a buffer 14 as a first buffer means and a first buffer means.
A delay element 16 as a delay unit, an AND gate 18 as a first noise detection unit, an AND gate 20 as a first trigger signal output signal, and a flip-flop 22 are provided, and the buffer 14 is connected to the input terminal 10. The AND gate 20 is connected to the input terminal 12, and the flip-flop 22 is connected to the output terminal 24.

The buffer 14 is an input buffer that determines the threshold voltage of the input signal 100 input to the input terminal 10, and when the input signal 100 exceeds the set voltage, a pulse corresponding to the time when the set signal is exceeded. It is designed to output a pulse signal having a width. Delay element 16
Is designed to delay the pulse signal from the buffer 16 by a set time. The AND gate 18 includes the delay element 16
The pulse signal from the buffer 14 and the pulse signal from the buffer 14 are compared, and when the pulse signals of both are overlapped on the time axis, the first noise detection pulse signal having the pulse width corresponding to the overlapped time is output. It has become. AND gate 2
0 outputs a high-level pulse signal to the flip-flop 22 when the first noise detection pulse signal from the AND gate 18 and the generation period of the timing signal input to the input terminal 12 overlap. There is. The flip-flop 22 outputs the high-level first trigger signal in response to the pulse signal from the NAND gate 20.

Next, the operation of the signal detection circuit shown in FIG. 1 will be described with reference to the waveform chart of FIG.

The signal detection circuit shown in FIG.
It is configured to detect high-level noise among the noise included in 0, and noise 10
When 2, 104, 106, 108 are superposed,
When the noise 102 is below the threshold voltage, the noise 102 is not detected by the buffer 14.

On the other hand, when the noises 104, 106 and 108 exceed the threshold voltage,
A pulse signal 11 having a pulse width corresponding to the time when each of the noises 104, 106 and 108 exceeds the threshold voltage.
0, 112, 114 are sequentially output from the buffer 14. Each pulse signal 110, 112, 114 is delayed by a delay element 16 for a set time, and the pulse signal 11
6, 118 and 120 are input to the AND gate 18. With this AND gate 18, pulse signals 110 and 11
6, pulse signals 112 and 118, pulse signals 114 and 1
The logical product with 20 is determined. Based on this determination, the AND gate 18 outputs the first noise detection pulse signals 122, 12
4 are sequentially output.

On the other hand, the timing signal 126 is generated from the input terminal 12 at a timing which causes a problem in the circuit operation of the system in which the signal detection circuit is mounted. And the first AN
In the D gate 20, the pulse signal 102 and the timing signal 126, and the pulse signal 124 and the timing signal 126
It is determined whether and are overlapping on the time axis. At this time, only the pulse signal 124 is the timing signal 1
26 on the time axis, a high-level pulse signal 128 is generated from the AND gate 20 in response to the pulse signal 124. When the pulse signal 128 is input to the set terminal of the flip-flop 22, the flip-flop 22 outputs the first trigger signal 130.

As described above, according to this embodiment, when the noises 102, 104, 106 and 108 are superimposed on the input signal 100, only the noise 108 is generated at a timing when there is a problem in the circuit operation of the system. It can be detected as noise.

Next, a second embodiment of the present invention will be described with reference to FIG.

In FIG. 3, the signal detection circuit includes a buffer 34 as a second buffer means, a delay element 36 as a second delay means, a NOR gate 38 as a second noise detection means, and a second trigger signal output means. It is configured by including an AND gate 40 and a flip-flop 42,
The buffer 34 is connected to the input terminal 30, the AND gate 40 is connected to the input terminal 32, and the flip-flop 42 is connected.
Are connected to the output terminal 44.

In the signal detection circuit of this embodiment, in order to detect low-level noise included in the noise included in the input signal 140, the buffer 34 detects noise below the threshold voltage (pulse signal), and N
The OR gate 38 is configured to take a negative logical OR of the pulse signal from the delay element 36 and the pulse signal from the buffer 34, and other configurations are similar to those of FIG.

Next, the operation of the signal detection circuit shown in FIG. 3 will be described with reference to the waveform chart shown in FIG.

Noise 142, 144,
When 146 and 148 are superimposed, noise 142
Is above the threshold voltage of buffer 34, noise 142 is not detected. On the other hand, when the noises 144, 146, 148 are below the threshold voltage of the buffer 34, the noises 144, 14
6, 148, pulse signals 150, 152, 154 having a pulse width corresponding to the time when the voltage is below the threshold voltage.
Are output from the buffer 34, respectively. Each pulse signal 150, 152, 154 is input to the NOR gate 38 after being delayed by the delay element 36 for a set time.
Then, in the NOR gate 38, the pulse signals 150 and 156, the pulse signals 152 and 158, and the pulse signal 154.
And 160 are respectively subjected to the logical sum determination, and the negative gate pulse signals 152 and 164 are output from the NOR gate 38.

On the other hand, when the timing signal 166 is input to the output terminal 32 at a timing which causes a problem in the circuit operation of the system, the pulse signals 162 and 164 generated as the second noise detection pulse signal in the AND gate 40.
Of the timing signal 166 and the timing signal 166 overlap each other on the time axis. At this time, the pulse signal 16
Since only 4 overlaps with the timing signal 166 on the time axis, the AND gate 40 outputs the high-level pulse signal 168 in response to the pulse signal 164. When the pulse signal 168 is input to the set terminal of the flip-flop 42, the flip-flop 42 outputs the second trigger signal 170.

According to the present embodiment, when the noises 142, 144, 146, 148 are superimposed on the input signal 140, only the noise 148 is detected as the noise generated at the timing which causes a problem in the circuit operation of the system. It

Next, an application example of the present invention will be described with reference to FIG.

In FIG. 5, the signal detection circuit 54 comprises the circuit shown in FIG. 1 or 3, and the input terminal 10 or 30 is connected to the observation circuit 50 and the input terminal 12 or 32 is connected to the timing circuit 52. Output terminal 24
Or 44 is connected to the oscilloscope 56. From the observation circuit 50, as shown in FIG.
dres select) signal 180, CAS (Colum Ad Row Adr)
es Serect) signal 182 is output, the RAS signal 180 is input to the timing circuit 52, the signal detection circuit 54, and the oscilloscope 56, and the CAS signal 182 is input to the timing circuit 52. A timing signal 184 is generated from the timing circuit 52 at a timing that causes a problem in the circuit operation of the system, and the timing signal 184 is input to the signal detection circuit 54. That is, the timing signal 184 is the RAS signal 1
In response to the fall of 80, when the CAS signal 182 is at the high level, it becomes the high level, and the CAS signal 182
It is set to a low level in response to the falling edge of.

In the above configuration, when the noises 186 and 188 are superimposed on the RAS signal 180, the noise 1
When 86 is below the threshold voltage of the buffer 14, the noise 186 is not detected, but when the noise 188 exceeds the threshold voltage of the buffer 14 and the timing signal 184 is generated at this timing, the signal detection circuit 54 outputs A trigger signal 192 is output, this trigger signal is input to the external terminal of the oscilloscope 56 as an external trigger, and the waveform of the noise 188 is displayed on the screen of the oscilloscope 56.

According to the present embodiment, of the noises 186 and 188 superposed on the input signal 180, the noise 188 is recorded by the oscilloscope 56 as the noise generated at the timing which causes a problem in the circuit operation of the system.

In the present embodiment, the buffers 14 and 34 used in the signal detection circuit 54 having different threshold voltages and the delay elements 16 and 36 having different delay times can be used. In this case, various noises can be observed by using different threshold voltages and delay times.

[0036]

As described above, according to the first aspect of the invention, when a pulse signal exceeding the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time and set by the set time delay. The detected pulse signal and the pulse signal superimposed on the input signal are compared, and when both pulse signals overlap on the time axis, noise detection is performed if the pulse signal of the set time width or more is superimposed on the input signal. A pulse signal is generated and the trigger signal is output on condition that this noise pulse signal overlaps with the timing signal on the time axis.Therefore, when a pulse such as noise is superimposed on the input signal, circuit operation It is possible to detect only the noise generated at the timing when there is a problem.

According to the second aspect of the invention, when a pulse signal having a voltage equal to or lower than the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time, and the pulse signal and the input signal delayed by the set time are provided. When the pulse signals of both are overlapped on the time axis by comparing with the pulse signal superimposed on, the noise detection pulse signal is generated as if the pulse signal of the set time width or more is superimposed on the input signal,
Since the trigger signal is output on the condition that this noise pulse signal overlaps with the timing signal on the time axis, when a pulse such as noise is superimposed on the input signal, it may occur at a timing when there is a problem in circuit operation. Only the generated noise can be detected.

According to the third aspect of the invention, when the pulse signal exceeding the set voltage is superimposed on the input signal,
This pulse signal is delayed by the first set time, and the pulse signal delayed by the set time is compared with the pulse signal superimposed on the input signal. When both pulse signals overlap on the time axis, the pulse signal is set as the input signal. The first noise detection pulse signal is generated assuming that the pulse signal of the time width or more is superimposed, and the first trigger signal is output on condition that the noise pulse signal overlaps with the timing signal on the time axis. In addition, when a pulse signal having a voltage equal to or lower than the set voltage is superimposed on the input signal, the pulse signal is delayed by the second set time, and the pulse signal delayed by the set time and the pulse signal superimposed on the input signal are In comparison, when the pulse signals of both are overlapped on the time axis, it is considered that the pulse signal of the set time width or more is superimposed on the input signal and the second noise detection pulse A signal is generated and the second trigger signal is output on condition that this noise pulse signal overlaps with the timing signal on the time axis. Therefore, when a pulse such as noise is superimposed on the input signal, the circuit It is possible to detect only the noise generated at the timing when there is a problem in operation.

According to the fourth aspect of the invention, when the pulse signal exceeding the set voltage is superimposed on the input signal,
This pulse signal is delayed by the set time, and the pulse signal delayed by the set time and the pulse signal superimposed on the input signal are compared, and when both pulse signals overlap on the time axis, the set time width is changed to the input signal. A pulse signal is generated assuming that the above pulse signals are superimposed, and the trigger signal is output on the condition that this pulse signal overlaps with the timing signal on the time axis. It is possible to detect only the noise generated at the timing when there is a problem in circuit operation when superposed.

According to the fifth aspect of the present invention, when the pulse signal having the voltage equal to or lower than the set voltage is superimposed on the input signal, the pulse signal is delayed by the set time, and the pulse signal and the input signal delayed by the set time are added. When the pulse signals of the two are overlapped on the time axis by comparing with the superimposed pulse signal, the pulse signal is generated assuming that the pulse signal of the set time width or more is superimposed on the input signal. Since the trigger signal is output on the condition that it overlaps with the timing signal on the time axis, when noise or other pulses are superimposed on the input signal, only the noise generated at the timing when there is a problem in circuit operation Can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal detection circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the signal detection circuit shown in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG.

FIG. 5 is a block diagram showing an application example of the present invention.

6 is a waveform chart for explaining the operation of the circuit shown in FIG.

FIG. 7 is a circuit configuration diagram of a conventional example.

FIG. 8 is a waveform chart for explaining the operation of the circuit shown in FIG.

FIG. 9 is a circuit configuration diagram of another conventional example.

FIG. 10 is a waveform chart for explaining the operation of the circuit shown in FIG.

[Explanation of symbols]

 14 buffer 16 delay element 18, 20, 40 AND gate 22, 42 flip-flop 34 buffer 36 delay element 38 NOR gate

Claims (5)

[Claims] 1. A buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage when the input signal exceeds the set voltage, and delaying the pulse signal from the buffer means by the set time. The delay means compares the pulse signal from the buffer means with the pulse signal delayed by the delay means, and when both pulse signals overlap on the time axis, noise detection of a pulse width corresponding to the overlapped time It is provided with noise detection means for outputting a pulse signal, and trigger signal output means for outputting a trigger signal on condition that the timing signal generated at a specified timing and the noise detection pulse signal overlap on the time axis. A signal detection circuit characterized by. 2. Buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage when the input signal is equal to or lower than the set voltage, and the pulse signal from the buffer means is set to the set time. Delay means for delaying, comparing the pulse signal from the buffer means with the pulse signal delayed by the delay means, and when both pulse signals overlap on the time axis, noise having a pulse width corresponding to the overlapping time It is provided with noise detection means for outputting a detection pulse signal, and trigger signal output means for outputting a trigger signal on condition that the timing signal generated at a specified timing and the noise detection pulse signal overlap on the time axis. A signal detection circuit characterized by the above. 3. A first buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage when the input signal exceeds the set voltage, and the input signal is below the set voltage. Second buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage, and first delay means for delaying the pulse signal from the first buffer means for the first set time. Second delay means for delaying the pulse signal from the second buffer means for a second set time, pulse signals from the first buffer means and pulse signals delayed by the first delay means are compared, and both pulses are compared. First noise detection means for outputting a first noise detection pulse signal having a pulse width corresponding to the overlapping time when the signals overlap on the time axis, and a pulse from the second buffer means. Signal and the pulse signal delayed by the second delay means are compared, and when both pulse signals overlap on the time axis, a second noise detection pulse signal having a pulse width corresponding to the overlapping time is output. A second noise detecting means, a timing signal generated at a designated timing, and the first signal
A first trigger signal output means for outputting a first trigger signal on condition that the noise detection pulse signal overlaps on the time axis, a timing signal generated at the designated timing, and the second noise detection pulse signal. And a second trigger signal output means for outputting a second trigger signal on the condition that they overlap on the time axis. 4. Buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input signal exceeds the set voltage when the input signal exceeds the set voltage, and delaying the pulse signal from the buffer means by the set time. Delay means, pulse detection means for comparing the pulse signal from the buffer means with the pulse signal delayed by the delay means to detect a pulse signal having a time width set by the delay means or more, and designated timing 2. A signal detection circuit, comprising: a trigger signal output means for outputting a trigger signal on the condition that the timing signal generated in 1) and the pulse signal detected by the pulse detection means overlap on the time axis. 5. Buffer means for outputting a pulse signal having a pulse width corresponding to the time when the input voltage is equal to or lower than the set voltage when the input signal is equal to or lower than the set voltage, and the pulse signal from the buffer means is set to the set time. Delay means for delaying, pulse detecting means for comparing the pulse signal from the buffer means and the pulse signal delayed by the delay means to detect a pulse signal having a time width set by the delay means or more, A signal detection circuit comprising: a trigger signal output means for outputting a trigger signal on condition that a timing signal generated at a timing and a pulse signal detected by the pulse detection means overlap on a time axis.