JPH0944460A - Barrier synchronization processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide barrier synchronization at a high speed even when the number of processors is increased. SOLUTION: Respective PEs turn on the bit of the present PE of the local register of the present PE (a step 2.2). Then, the value of the local register and the value of a shared register are exchanged by a TS instruction (the step 2.3). Then, whether or not the bits of all the PEs of the value obtained in the local register by exchange are on is checked (the step 2.4). When all are on, it is concidered as a barrier synchronization end. When all bits are not on, whether or not the bits except the bit of the present PE of the local register are all on is checked (the step 2.5). When the step 2.5 is no, the bit of the present PE of the local register is turned on (the step 2.6) and the step 2.3 is returned. When the step 2.5 is yes, the bit '0' of the local register is turned on and the value of the local register and the value of the shared register are exchanged by the TS instruction (the step 2.7).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrier synchronization processing method in a computer system, particularly a multiprocessor system.

[0002]

2. Description of the Related Art A conventional barrier synchronization processing method in a multiprocessor system utilizes a Test And Set instruction. Test And Set command (hereinafter referred to as TS command)
Is an instruction for exchanging the value of the local register of the self processor with the value of the shared register. When the most significant bit of the shared register is ON, the value of the shared register is only copied to the local register. This instruction is used to lock and modify shared registers.

FIG. 1 is a system configuration diagram of a multiprocessor system, FIG. 4 is a diagram explaining the meaning of each bit of a shared register and a local register, and FIG. 5 is a processing flow chart of a conventional barrier synchronization processing.

First, each processor (hereinafter referred to as PE) starts with bit 0 indicating lock being turned on (step 4.1). PE1 issues a TS instruction to exchange values with the shared register (step 4.
2). A lock is given to PE1 since bit 0 of the lock bit of the copied value is off (step 4.
3). PE1 turns on bit 1 of its own PE to write to the shared register (step 4.
4). Since the lock has already been acquired for writing here, it is forcibly written using a normal instruction. Then PE
2 issues a TS instruction to exchange values with the shared register (step 4.5). A lock is given to PE2 because bit 0 of the lock bit in the copied value is off (step 4.6). PE2 turns on bit 2 which is the bit of its own PE, and writes to the shared register (step 4.7). This turns on all the bits in the shared register, thus establishing the barrier motive (step 4.8).

[0005]

In the above-mentioned conventional barrier synchronization processing method, since the barrier synchronization processing is performed by using the lock, all the other processors wait until the lock is released and the barrier synchronization processing is performed. However, there is a problem that the processing time increases remarkably when the number of processors is large, and the performance of the multiprocessor deteriorates.

[0006]

According to the present invention, n (n is 2)
In the barrier synchronization processing method in the multiprocessor system in which the processors each having the above integer) and the shared register and each processor has a local register, bit 0 is a lock bit and bit 1 to bit n.
Each of the bits up to is prepared in advance with the shared register and the local register having a bit configuration corresponding to one of the n processors, and each processor has
The bit corresponding to the local processor of the local register of the local processor is turned on (step 2.2), and then TS
The information of the local register and the information of the shared register are exchanged by a (Test & Set) instruction (step 2.
3) Next, it is checked whether the bits of all the processors in the information obtained in the local register by the exchange are on (step 2.4), and if all the bits of all the processors are on, it is considered that the barrier synchronization has ended. If even one of the bits of all the processors is not on, it is checked whether all the bits other than the bit of the local processor in the local register are on (step 2.5), and all the check results in step 2.5 are on. Otherwise, after turning on the bit of the local processor of the local register (step 2.6), the process returns to step 2.3, and if all the check results in step 2.5 are on, the bit of the local register is turned on. When 0 is turned on, the information of the local register is Exchanging information of the serial shared register (step 2.7) to be characterized.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram for implementing the barrier synchronization processing method of the present invention, FIG. 2 is a flow chart of a barrier synchronization processing showing an embodiment of the present invention, and FIG. 3 is a block diagram of the barrier synchronization processing of the present invention. FIG.

In the following example, the case of two processors will be described, but the same applies to the case of three or more processors.

Also in the present invention, TS (Test And) is used as an instruction for exchanging the values of the local register and the shared register.
Set) instruction. That is, if the most significant bit of the shared register is off, the TS instruction operates as a simple exchange instruction.

Referring to FIG. 2, each PE is its own PE.
The local PE bit of the local register is turned on (step 2.2). Next, the value of the local register and the value of the shared register are exchanged by the TS instruction (step 2.3).
Next, it is checked whether the bits of all PEs of the value obtained in the local register by the exchange are on (step 2.4). If all are turned on, it is considered that the barrier synchronization has ended, and the barrier ends (step 2.8). If all the bits are not on, it is checked whether all the bits in the local register other than the PE's own bit are on (step 2.5). If step 2.5 is no, the bit of the local PE of the local register is turned on (step 2.6), and step 2.3
Return to If yes in step 2.5, bit 0 of the local register is turned on, the value of the local register and the value of the shared register are exchanged by the TS instruction (step 2.7), and the process proceeds to step 2.8.

Next, a specific example will be described with reference to FIG. First, each PE (processor) starts from a state in which the bit corresponding to its own PE is turned on (logic 1) (step 3.1). PE1 issues a TS instruction (step 3.2) and exchanges the value of the shared register with the value of the local register (step 3.3). Since the lock bit is not turned on here, the shared register is not locked and the shared register can be accessed freely from any PE. Next, the PE 2 issues a TS instruction to exchange the values of the local register and the shared register (step 3.
4). PE2 turns on the bit of its own PE of the value copied to the local register (step 3.6). Since the bits of all PEs are turned on, the lock bit is also turned on (step 3.7). This prevents the value with all bits turned on from being exchanged from the shared register. PE2 issues a TS instruction to exchange the value with the shared register (step 3.8). Now all the bits of the shared register are turned on, so that barrier synchronization is established. Since the lock bit is on, it is not rewritten even when the TS instruction is issued from another PE, and the other PE also refers to this value and the barrier is established immediately.

The number of times the TS command is issued by this method is P
It rises moderately with respect to the number of E, and P compared with the conventional technology
The effect becomes more remarkable as the number of E units increases.

[0014]

As described above, the barrier synchronization processing method of the present invention mainly realizes the barrier synchronization by exchanging the values of the shared register and the local register without using the lock, so that each processor always operates. There is an effect that the shared register can be defined and referenced, and barrier synchronization can be realized at high speed even if the number of processors increases.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a system configuration example to which a barrier synchronization process is applied.

FIG. 2 is a flowchart showing an example of barrier synchronization processing of the present invention.

FIG. 3 is a flowchart for explaining the operation of the present invention.

FIG. 4 is a diagram showing a configuration of a shared register.

FIG. 5 is a flowchart showing an example of a conventional barrier synchronization processing method.

[Explanation of symbols]

1.1, 1.4 PE (processor) 1.3 Shared register 1.2, 1.5 Local register Step 2.1 to Step 2.7 Barrier synchronization processing flowchart

Claims (1)

[Claims] 1. In a barrier synchronization processing method in a multiprocessor system comprising n (n is an integer of 2 or more) processors and shared registers, each processor having a local register, bit 0 is a lock bit, and bit 1 is a lock bit. Each bit from to n is prepared in advance with the shared register and the local register having a bit configuration corresponding to one of the n processors, and each processor has its own local register self-registered. Turn on the bit corresponding to the processor (step 2.2), and then TS (Test & Set)
An instruction exchanges information in the local register and information in the shared register (step 2.3), and then checks whether all processor bits in the information obtained in the local register by the exchange are on (step 2). ．
4) If all the bits of all the processors are on, it is considered that the barrier synchronization has ended, and if even one of the bits of all the processors is not on, it is checked whether all the bits other than the bits of the local processor of the local register are on. (Step 2.5), if the check results in step 2.5 are not all on, the bit of the local processor of the local register is turned on (step 2.6), and then the process returns to step 2.3. If all the check results in the step 2.5 are on, the bit 0 of the local register is turned on and the information of the local register and the information of the shared register are exchanged by the TS instruction (step 2.7). A characteristic barrier synchronization processing method.