JPH0951496A - Liquid crystal display - Google Patents

Abstract

It is an object of the present invention to provide a liquid crystal display device capable of performing thinning processing of a scanning period of a video signal without deteriorating image quality. An electronic tuning tuner-3 receives a predetermined television wave, and an interface circuit 8 performs various drive controls for thinning out a scanning period of a video signal in accordance with a broadcasting system received by the electronic tuning tuner 3. A signal is generated and selected, and is supplied to the signal side driving circuit 9 and the scanning side driving circuit 10. Then, the scan side drive circuit 10 does not select the scan line of the liquid crystal display panel 11 during the scan period in which the video signal should be thinned out, in response to various control signals supplied from the interface circuit 8.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, for example, a liquid crystal television device, scanning lines and signal lines are generally formed in a matrix on a substrate, and scanning line driving signals are supplied to the scanning lines and video signals are supplied to the signal lines. A television image is displayed by so-called matrix driving, in which a signal line driving signal corresponding to is applied.

Normally, in a liquid crystal television set, one of the video signals is used.
In the scanning period (1H), one scanning line of the liquid crystal display panel is selected, a relatively high scanning line driving voltage is applied, and at the same time, all signal lines facing this scanning line are compared with each other corresponding to video signals. By applying an extremely low gradation signal voltage, each pixel on the selected scan line is displayed.

By the way, in the conventional liquid crystal television device, the number of scanning lines of the liquid crystal display panel corresponds only to a specific broadcasting system. Therefore, in order to correspond to a broadcasting system having a different number of scanning lines, It is necessary to perform thinning processing for the scanning period of the video signal.

For example, as a conventional thinning method for the scanning period of the video signal, a method shown in the scanning principle diagram of FIG. 6 is known. In the figure, when performing the thinning-out process of the 5th H of the video signal, after displaying the 5th H of the video signal on the 5th scanning line of the display unit, the 6H H of the video signal is displayed on the 5th scanning line. I am overwriting. That is, it is a method of overwriting the video signal of the scanning period to be thinned out and the video signal of the next scanning period on one scanning line of the display unit.

[0006]

However, in the above-described conventional thinning method for the scanning period of the video signal,
Since the video signal of the scanning period to be thinned out and the video signal of the next scanning period are overwritten on one scanning line of the display unit, the effective value of the voltage applied to the overwritten scanning line is Therefore, there is a problem in that an appropriate display image cannot be obtained because the brightness is increased only in the scanning line portion, and the image quality of the scanning line to be thinned out is deteriorated. Therefore, the present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device capable of performing thinning processing of a scanning period of a video signal without degrading image quality.

[0007]

According to another aspect of the present invention, there is provided a liquid crystal display panel having display elements arranged in a matrix at intersections of scanning lines and signal lines, the scanning side driving means and the signal side driving means. According to another aspect of the present invention, there is provided a liquid crystal display device driven by, wherein the scanning side driving means does not select the scanning line during a scanning period in which a video signal should be thinned.

That is, according to the liquid crystal display device of the first aspect, the scanning side driving means deselects the scanning line of the liquid crystal display panel during the scanning period in which the thinning of the video signal is performed, so that the video signal is generated. Thinning processing is performed. Therefore, an appropriate voltage is applied to the scan line of the liquid crystal display panel, and the thinning process during the scan period that does not deteriorate the image quality becomes possible.

In this case, as in the liquid crystal display device according to the second aspect, the signal side driving means alternately inverts the voltage polarity of the video signal applied to each signal line for each scanning line. May be.

That is, according to the liquid crystal display device of the second aspect, the signal side driving means alternately inverts the voltage polarity of the video signal applied to each signal line for each scanning line, thereby generating the flicker. To prevent. Therefore, it is possible to prevent the occurrence of flicker, and it is possible to display a high-quality video signal.

Further, in this case, as in the liquid crystal display device according to the third aspect, a receiving unit capable of receiving television radio waves of a plurality of broadcasting systems, and scanning line thinning processing according to the broadcasting systems received by the receiving unit. A plurality of drive control signal generators for generating a drive control signal for performing the above, and a selection unit for selecting one drive control signal generator according to a broadcasting system received from the plurality of drive control units. The scanning side drive means and the signal side drive means may drive the liquid crystal display panel based on a drive control signal generated from one drive control signal generation section selected by the selection means.

That is, according to the liquid crystal display device of the third aspect, the receiving unit receives the television radio wave of the predetermined broadcasting system, and performs the thinning process of the scanning period according to the broadcasting system received by the receiving unit. It has various drive control signal generators for generating drive control signals, and the selecting means selects a predetermined drive control signal generator from the various drive control signal generators.
The scanning side driving means and the signal side driving means drive the liquid crystal display panel based on the selected driving control signal of the driving control signal generating section, and perform thinning processing of the scanning period of the video signal. Therefore, the liquid crystal display panel can be driven by automatically selecting the drive control unit that performs the thinning process corresponding to the type of broadcasting system, and the common liquid crystal display panel, the signal side drive circuit, and the scan side drive can be used. Since it is possible to display video signals with different numbers of scanning lines using a circuit, convenience in using the liquid crystal display device can be improved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 5 show a liquid crystal display device 1 according to the present invention.
It is a figure showing an example, and its liquid crystal display device 1 is NTS.
It is configured to be able to display C system and PAL system broadcasts. FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device of the present invention. FIG. 3 shows that the liquid crystal display device of FIG.
FIG. 7 is a timing diagram when scanning TSC broadcasting.
FIG. 4 is a timing diagram when the liquid crystal display device of FIG. 1 scans a PAL system broadcast. Hereinafter, the present invention will be described in detail based on FIG. 1 and with reference to FIGS. 3 and 4.

First, the configuration will be described. 1, the liquid crystal display device 1 includes a rod antenna 2, an electronic tuning tuner 3, a television linear circuit 4, an A / D conversion circuit 5, a data conversion circuit 6, a controller 7, an interface circuit 8,
It is composed of a signal side drive circuit 9, a scanning side drive circuit 10, a liquid crystal display panel 11 and the like. Liquid crystal display panel 11
Adopts an active matrix type, and 220 scanning lines Ym and 540 signal lines Xn are arranged in a matrix on a substrate (not shown) and is compatible with NTSC broadcasting. A TFT (thin film transi) is provided at each intersection of the scanning line Ym and the signal line Xn.
Stor) element and a pixel electrode is connected to the drain side of the switching element to form a liquid crystal capacitor, which has 540 × 220 pixels.

Each TFT element (not shown) has its gate connected to the corresponding scanning line Y1-Ym, and its source respectively corresponding signal line X1-Ym.
It is connected to Xn. Further, each TFT element has a liquid crystal capacitor connected to its drain, and a common line (not shown) to which a reference voltage is supplied is connected to the other electrode of the liquid crystal capacitor.

Then, in the liquid crystal display panel 11, the scanning side drive circuit 10 and the signal side drive circuit 9, which will be described later, sequentially drive the scanning lines Ym and the signal lines Xn, and the liquid crystal capacity of each of the sequentially selected pixels. A drive voltage corresponding to the video signal is applied to the display device, and the electric charge is retained, so that the video signal is displayed. The rod antenna 2 receives TV radio waves, and the received radio waves are electronically tuned by the tuner 3
To supply. The electronic tuning tuner 3 has a controller 7
A designated channel is selected according to the tuning signal input from the converter, the desired television broadcast radio wave supplied from the rod antenna 2 is converted into an intermediate frequency signal, and the intermediate frequency signal is output to the television linear circuit 4.

The television linear circuit 4 is composed of an intermediate frequency amplification circuit, a video detection circuit, a video amplification circuit, an AFT detection circuit, a chroma circuit, etc., and converts the intermediate frequency signal input from the electronic tuning tuner 3 into the intermediate frequency signal. After amplification by the amplifier circuit, AFT detection circuit performs AFT detection, or video detection circuit performs video detection to extract a video signal, and further the video signal output by the video detection circuit is amplified by the video amplification circuit. , To the A / D conversion circuit 5. Further, the television linear circuit 4 uses its chroma circuit to extract a synchronization signal from the video signal and output it to the controller 7.

The audio signal separated by the television linear circuit 4 is sent to an audio circuit (not shown), and the audio circuit
After being voice-detected and converted into a low frequency signal, it is supplied to a speaker (not shown) via an amplifier circuit. The A / D conversion circuit 5 performs A / D (analog / digital) conversion (sampling) on the video signal input from the television linear circuit 4 based on the timing signal input from the controller 7, and outputs it to the data conversion circuit 6. To do.

The data conversion circuit 6 converts the digital video signal input from the A / D conversion circuit 5 into a signal side drive circuit 9.
After being converted into a data format that can be driven by, it is output to the signal side drive circuit 9 as display data. That is, the data conversion circuit 6 sequentially reads, for example, the video signal input from the A / D conversion circuit 5 according to the timing signal input from the controller 7, reads the video signal for one line, and then converts the video signal into the video signal. Accordingly, a gradation signal is created and output to the signal side drive circuit 9 as display data.

The controller 7 separates the horizontal synchronizing signal φH and the vertical synchronizing signal φV contained in the video signal input from the television linear circuit 4, and outputs them to the interface circuit 8. Further, the controller 7 is provided with a sync separation circuit (not shown) in its main part. The sync signal is input from the television linear circuit 4 to the sync separation circuit,
The sync separation circuit generates a vertical sync signal φV and a horizontal sync signal φH from this sync signal, and the interface circuit 8
Output to

The controller 7 also supplies a broadcast type signal indicating the type of the received broadcast wave to the mode selection circuit 83 of the interface circuit 8. The interface circuit 8 includes an NTSC signal control circuit 81, a PAL signal control circuit 82, and a mode selection circuit 83. The NTSC signal control circuit 81 and the PAL signal control circuit 82 include a clock generating circuit and a frequency dividing circuit, which are not shown, and a horizontal synchronizing signal φH input from the synchronizing separation circuit of the controller 7.
Based on the vertical synchronizing signal φV and the vertical synchronizing signal φV, various control signals corresponding to the received broadcasting system are generated, and the mode selection circuit 8
3, the signal side driving circuit 9 and the scanning side driving circuit 10
To supply.

The NTSC signal control circuit 81 generates various control signals corresponding to the NTSC broadcasting system on the basis of the horizontal synchronizing signal φH and the vertical synchronizing signal φV inputted from the synchronizing separation circuit of the controller 7, and causes the mode selecting circuit 83 to do so. Supply. When the broadcasting system is the NTSC system, the number of scanning lines in one field of the video signal is 525 divided by 2 26
Although it is 2.5, the actual number of scanning lines is about 220 after subtracting the vertical blanking period and the number of ineffective scanning lines of about 40. Therefore, when displaying the NTSC image, the liquid crystal display panel 1 is used as described above.
Since the number of one scanning line is 220, it is not necessary to thin out the scanning period of the video signal.

That is, the NTSC control circuit 81 uses, as various control signals, a gate start signal ST (vertical synchronization signal) and a gate clock signal GCK (horizontal synchronization) for determining the start timing of driving the scanning lines as shown in FIG. signal),
Also, a gate reset signal RES (gate control signal) or the like is generated and supplied to the scanning side drive circuit 10 via the mode selection circuit 83. Further, the NTSC control circuit 81 generates a signal side drive control signal SCK as a control signal and a source inversion signal HCNT which alternately repeats "H" and "L" every 1H as shown in FIG. Mode selection circuit 8
3 to the signal side drive circuit 9. The source inversion signal HCNT is for inverting the voltage corresponding to the display data applied to the signal line for each scanning line.

The PAL signal control circuit 82 generates various control signals corresponding to the PAL broadcasting system based on the horizontal synchronizing signal φH and the vertical synchronizing signal φV input from the sync separation circuit of the controller 7, and the mode selecting circuit 83. Is supplied to the signal side drive circuit 9 and the scanning side drive circuit 10 via.
The PAL system has 625 scanning lines per frame, and the NTSC system has 525 scanning lines per frame.
It is a book. Therefore, in order to display the PAL system broadcast on the television which receives the NTSC system broadcast, (625-525) becomes an excessive number of scanning lines, which cannot fit on one screen. Therefore, it is necessary to thin out the scanning lines at a rate of one in six.

The PAL signal control circuit 82 is shown in FIG.
Generate a gate start signal ST (vertical synchronization signal), a gate clock signal GCK (horizontal synchronization signal), and a gate reset signal RES (gate control signal) that determine the start timing of scanning line drive. , To the scanning side drive circuit 10 via the mode selection circuit 83. These control signals are for thinning out the scanning period of the video signal by 1H every 6H.

Here, in the embodiment shown in FIG. 3, the gate shift clock signal CK is decimated by one in every six pulses, that is, the 5H and 6H, 11H and 12H of the video signal. The pulses are periodically (6H units) decimated between. Then, the gate reset signal RES
, Pulses corresponding to the 5th H, the 11th H, ... Are thinned out.

Further, the PAL signal control circuit 82 generates a signal side drive control signal SCK, a source inversion signal HCNT, etc. as control signals and supplies them to the signal side drive circuit 9 via the mode selection circuit 83. Here, in the embodiment shown in FIG. 4, the source inversion signal HCNT has the same logical value between the thinned scanning period and the next scanning period. That is, 5H and 6H, 11H and 12H,
... have the same logical value. In other words, if the logical values of the scanning period (4H, 10H, ...) Before the thinned scanning period (5H, 11H, ...) And the scanning period (6H, 12H) after it are different. I am making it.

The mode selection circuit 83, as described above, uses the N
Various control signals are input from the TSC signal control circuit 81 and the PAL signal control circuit 82, and a broadcast type signal is input from the controller 7 to the selector terminal of the mode selection circuit 83. When the broadcast type signal input from the controller represents the NTSC broadcast signal, the mode selection circuit 83
The control signal input from the NTSC signal control circuit 81 is selected and supplied to the signal side drive circuit 9 and the scan side drive circuit 10. On the other hand, when the broadcast type signal input from the controller 7 represents a PAL broadcast signal, the PAL signal control circuit 8
The control signal input from 2 is selected and supplied to the signal side drive circuit 9 and the scanning side drive circuit 10.

That is, the mode selection circuit 83 determines the NT based on the broadcast type signal S4 supplied from the controller 7.
Either the SC signal control circuit 81 or the PAL signal control circuit 82 is selected, and various control signals are supplied to the signal side drive circuit 9 and the scan side drive circuit 10. Scanning side drive circuit 10
Are various control signals (gate start signal ST, gate clock signal GC) supplied from the interface circuit 8.
K, the gate reset signal RES), a predetermined number of scanning lines Yn in the active matrix type liquid crystal display panel.
Is selected and sequentially scanned and driven. Here, FIG. 2 is a circuit configuration example of the scanning side drive circuit 10.

In FIG. 2, the scanning side drive circuit 10 includes shift register circuits 31 to 36 and NAND gates 41 to 4.
6 and inverter circuits 51 to 56, and the scanning lines Y1 to Yn are connected to the respective output terminals of the shift register circuit via the inverter circuit and the NAND gate. The shift register circuits 31 to 36 are
The gate start signal ST is changed to the gate shift clock signal C
It is a circuit that holds at the timing of K. The shift register circuits 31 to 36 latch the gate start signal ST at the timing of the gate clock signal GCK and sequentially output the data to the shift register and the NAND gate of the next stage.

The NAND gates 41 to 46 output the NAND outputs of the shift output and the gate reset signal RES respectively supplied from the shift register circuits 31 to 36 to the scanning lines Y1 to Y6 via the inverters 51 to 56.
Here, when the control signal output from the NTSC signal control circuit 81 is selected by the mode selection circuit 83, the gate start signal ST, the gate clock signal GCK, and the gate reset signal RES as shown in FIG. ,
The input terminals of the shift register circuits 31 to 36, the CK terminal,
, And the NAND gates 41 to 46 are input to one of the input terminals, respectively, and the inverter circuits 51 to 56 sequentially output selection pulses to predetermined scan lines Y1 to Y6.

On the other hand, when the control signal output from the PAL signal control circuit 82 is selected by the mode selection circuit 83, the gate start signal ST, the gate clock signal GCK, and the gate reset signal as shown in FIG. R
ES is an input terminal of the shift register circuits 31 to 36, C
The input signals are input to the K terminal and one of the input terminals of the NAND gates 41 to 46, respectively.
From 6 the 5H period of the video signal is thinned out "1H, 2
H, 3H, 4H, 6H, 7H, ... The selection pulses in the periods are the scanning lines Y1, Y2, Y3, Y4, Y5, Y.
6, ... will be supplied respectively.

The signal side drive circuit 9 supplies from the interface circuit 8 a set voltage having a polarity according to the display data supplied from the data conversion circuit 6 and the source inversion signal HCNT supplied from the interface circuit 8. The signal lines Xn of the liquid crystal display panel 11 are sequentially selected and applied based on the signal side drive control signal SCK.
The set voltage is held in the liquid crystal capacitance connected to the selected scanning line Ym, and the video signal is displayed on the display panel 11.

Further, in this case, the setting voltages of opposite polarities are applied to the adjacent scanning lines, and the positive and negative voltages can be evenly distributed over the liquid crystal display panel 11. That is, since the voltage of each pixel can be evenly distributed in the vertical direction, the occurrence of flicker can be suppressed. Further, as shown in FIG. 5, if the set voltage VID is AC-inverted every one field (1/60 s), it is possible to further prevent the occurrence of flicker.
In the figure, VG indicates a gate potential and VCOM indicates a common electrode potential.

Next, the operation of this embodiment will be described. When the main power source (not shown) of the liquid crystal display device 1 of the present embodiment is turned on, the power source circuit (not shown) supplies a power source voltage to each block shown in FIG. 3 to start the operation of each block. First, the television wave received from the rod antenna 2 is supplied to the electronic tuning tuner 3, and the electronic tuning tuner 3 selects a desired channel according to the tuning signal input from the controller 7, and the rod antenna 2
A desired television broadcast radio wave supplied from is converted into an intermediate frequency signal and supplied to the television linear circuit 4.

In the television linear circuit 4, after the intermediate frequency signal input from the electronic tuning tuner 3 is amplified by the intermediate frequency amplifier circuit, the AFT detection circuit performs AFT detection, and the image detection circuit performs image detection. The video signal is taken out and the video signal supplied from the video detection circuit is amplified by the video amplification circuit,
It is supplied to the A / D conversion circuit 5. Further, in the television linear circuit 4, the chroma circuit extracts a synchronization signal from the video signal and supplies it to the controller 7.

In the A / D conversion circuit 5, the video signal supplied from the television linear circuit 4 is A / D (analog / digital) converted (sampled) based on the timing signal input from the controller 7, and then the data is converted. It is supplied to the conversion circuit 6. In the data conversion circuit 6, the digital video signal input from the A / D conversion circuit 5 is converted into a data format that can be driven by the signal side drive circuit 9, and then output as display data to the signal side drive circuit 9. .

On the other hand, in the controller 7, the horizontal synchronizing signal φH and the vertical synchronizing signal φV included in the video signal input from the television linear circuit 4 are separated and output to the interface circuit 8. Interface circuit 8 NT
In the SC signal control circuit 81 and the PAL signal control circuit 82, various control signals are respectively generated according to the horizontal synchronizing signal φH and the vertical synchronizing signal φV input from the synchronizing separation circuit of the controller 7, and the mode selecting circuit 83 is generated. Supplied.

In the mode selection circuit 83, the controller 7
When the broadcast type signal S4 input from the NTSC broadcast signal represents an NTSC broadcast signal, various control signals input from the NTSC signal control circuit 81 are selected and supplied to the signal side drive circuit 9 and the scan side drive circuit 10. When the broadcast type signal S4 input from the controller 7 represents a PAL broadcast signal, P
Various control signals input from the AL signal control circuit 82 are selected and supplied to the signal side driving circuit 9 and the scanning side driving circuit 10.

Here, when the broadcast type signal represents NTSC broadcast, as shown in FIG. 3, a gate start signal ST (vertical synchronization signal) and a gate clock signal GCK (which determine the start timing of driving the scanning lines. The horizontal synchronization signal) and the gate reset signal RES (gate control signal) are transferred from the NTSC signal control circuit 81 to the mode selection circuit 8
It is supplied to the scan side drive circuit 10 via

In the scanning side drive circuit 10, the gate start signal ST and the gate clock signal C as shown in FIG.
In the scanning side drive circuit 10 shown in FIG. 2, K and the gate reset signal RES are the shift register times 31 to 31.
6 input terminals, CK terminal, and NAND gates 41 to 4
6 will be input to one of the input terminals of each of the input terminals 6, and the predetermined scan lines Y1 to Y1 will be sequentially output from the inverter circuits 51 to 56.
A selection pulse is output to Y6, and as shown in FIG. 3, selection pulses corresponding to 1H, 2H, 3H, ... Of the video signal are sequentially applied to the scanning lines Y1, Y2, Y3 ,. , The scan line will be selected.

In the signal side drive circuit 9, the polarity is set according to the display data supplied from the data conversion circuit 6 and the source inversion signal HCNT as shown in FIG. 3 supplied from the interface circuit 7. The voltage is the signal side drive control signal S supplied from the interface circuit 8.
The signal lines Xn of the liquid crystal display panel 11 are sequentially applied according to CK. The set voltage is held in the liquid crystal capacitance connected to the selected scanning line Ym, and the video signal is displayed on the display panel 11.

Further, in this case, the setting voltages having opposite polarities are applied to the adjacent scanning lines, so that the positive and negative voltages can be evenly distributed over the entire liquid crystal display panel 11. That is, since the voltage of each pixel can be evenly distributed in the vertical direction, the occurrence of flicker can be suppressed.

On the other hand, when the broadcast type signal represents a PAL broadcast, as shown in FIG. 4, a gate start signal ST (vertical synchronization signal) and a gate clock signal GCK (horizontal synchronization signal) that determine the start timing of driving the scanning lines. ), And the gate reset signal RES (gate control signal) is N
It is supplied from the TSC signal control circuit 81 to the scanning side drive circuit 10 via the mode selection circuit 83.

In the scanning side drive circuit 10, the gate start signal ST and the gate clock signal GC as shown in FIG.
K and the gate reset signal RES are input to the input terminals of the shift register circuits 31 to 36, the CK terminal, and one input terminal of the NAND gates 41 to 46 in the specific example circuit of the scanning side drive circuit 10 shown in FIG. As shown in FIG. 4, 5H periods of the video signal are thinned out from the inverter circuits 51 to 56, respectively, “1H, 2H,”.
3H, 4H, 6H, 7H, ... The selection pulses of the period are the scanning lines Y1, Y2, Y3, Y4, Y5, Y
6, ... will be supplied respectively.

In the signal side drive circuit 9, the data conversion circuit 6
Signal supplied from the interface circuit 7 and a polarity setting voltage corresponding to the source inversion signal HCNT supplied from the interface circuit 7 as shown in FIG. SC
Based on K, the signal lines Xn of the liquid crystal display panel 11 are sequentially selected and applied. The set voltage is held in the liquid crystal capacitance connected to the selected scanning line Ym, and the video signal is displayed on the display panel 11.

In this case, as shown in FIG. 4, the source inversion signal HCNT is set to have opposite polarities in the scanning periods (4H, 6H) before and after the scanning period 5H in which the video signal is thinned out. The polarity of the set voltage is inverted between the scanning line Y4 for scanning 4H of the video signal and the scanning line Y5 for scanning 6H of the video signal. Therefore, even when performing the thinning-out process of the scanning period of the video signal, it becomes possible to apply the setting voltage of the opposite polarity for each scanning line, and it is possible to prevent the occurrence of flicker.

In the above embodiment, when thinning out the scanning period of the video signal, the scanning line is not selected during the thinning scanning period, so that an appropriate voltage is applied to the scanning line and the image quality is deteriorated. It is possible to perform thinning processing of the scanning lines on the video signal without performing the above.

Further, in the present embodiment, when displaying the broadcasting of the broadcasting system having different scanning lines on the liquid crystal display device, the common liquid crystal display panel and the driving circuit are formed by performing the thinning-out processing according to the broadcasting system. It is possible to use, and it is possible to display broadcasts of different broadcast systems with an inexpensive and simple configuration.

Further, in the above embodiment, since the polarity of the set voltage is inverted for each scanning line, the occurrence of flicker can be prevented. In this embodiment, the TFT
The active matrix driving method is used, but the invention is not limited to this, and for example, MIM (Metal Insu
An active matrix driving method using a lat-or metal diode or a simple matrix driving method may be used. The point is that it can be driven by time division.

In this embodiment, the broadcasting system is N
The case where there are two types of the TSC system and the PAL system and the number of scanning lines of the liquid crystal display panel 11 is 220 has been described, but the broadcasting system is not limited to the above two types, and the liquid crystal is not limited to the above two types. The number of scanning lines of the display panel is not limited to this. In addition, although the liquid crystal television has been described in the present embodiment, the present invention is not limited to this, and can be applied to the case of displaying an image or the like on a computer display or the like. Further, in the above embodiment, the polarity of the set voltage of the video signal is inverted for each scanning line to prevent the occurrence of flicker, but the polarity of the set voltage may be inverted for each signal line.

[0052]

According to the liquid crystal driving method of the first aspect,
The scanning side driving means is configured to perform thinning processing of the video signal during the scanning period by deselecting the scanning lines of the liquid crystal display panel during the scanning period in which the video signal should be thinned. As a result, an appropriate voltage is applied to the scanning line of the liquid crystal display panel, and the thinning process of the scanning period of the video signal can be performed without deteriorating the display image quality.

Further, according to the invention of the liquid crystal driving method as set forth in claim 2, the signal side driving means is configured to alternately invert the voltage polarity of the video signal applied to each signal line for each scanning line. . As a result, it is possible to prevent the occurrence of flicker and display a high-quality video signal.

Further, according to the liquid crystal driving method of the third aspect, the receiving section further receives television radio waves of a predetermined broadcasting system, and thinning-out processing is performed according to the broadcasting system received by the receiving section. A drive control signal generating section for generating a drive control signal for selecting a predetermined drive control signal generating section from the various drive control signal generating sections, and selecting the drive control signal. Based on the drive control signal of the generator, the scanning side drive means and the signal side drive means
The liquid crystal display panel is driven to perform thinning processing of the scanning period of the video signal. As a result, it is possible to automatically select the drive control unit that performs the thinning-out process corresponding to the type of broadcasting system and drive the liquid crystal display panel.
Since it is possible to display video signals having different scanning line numbers by using a common liquid crystal display panel, a signal side driving circuit, and a scanning side driving circuit, it is possible to improve convenience of use of the liquid crystal display device. You can

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of a liquid crystal television according to the present invention.

FIG. 2 is a diagram showing a specific example of a scanning side drive circuit in FIG.

FIG. 3 is a timing diagram when the liquid crystal display device of FIG. 1 scans an NTSC broadcast.

FIG. 4 is a timing diagram when the liquid crystal display device of FIG. 1 scans a PAL system broadcast.

5 is a diagram showing drive waveforms of the liquid crystal display panel of FIG.

FIG. 6 is a scanning principle diagram for explaining a conventional thinning method for a scanning period of a video signal.

[Explanation of symbols]

 1, liquid crystal display device 2 rod antenna 3 electronic tuning tuner 4 television linear circuit 5 A / D converter 6 data conversion circuit 7 controller 8 interface circuit 9 signal side drive circuit 10 scanning side drive circuit 11 liquid crystal display panel 81 NTSC signal control unit 82 PAL signal controller 83 Mode selection circuit

Claims (3)

[Claims] 1. A liquid crystal display device in which a liquid crystal display panel in which display elements are arranged in a matrix at intersections of scanning lines and signal lines is driven by scanning side driving means and signal side driving means. The liquid crystal display device is characterized in that the means does not select the scanning line during a scanning period in which a video signal is to be thinned out. 2. The liquid crystal display device according to claim 1, wherein the signal line driving means alternately inverts the voltage polarity of the video signal applied to each signal line for each scanning line. 3. A receiving unit capable of receiving television radio waves of a plurality of broadcasting systems, and a plurality of drive controls for generating a drive control signal for thinning out a scanning period according to a broadcasting system received by the receiving unit. 1 depending on the signal generation unit and the broadcasting system received from the plurality of drive control units
Selecting means for selecting the drive control signal generating section, and the scanning side driving means and the signal side driving means are based on the drive control signal generated from the one drive control signal generating section selected by the selecting means. The liquid crystal display device according to claim 1, wherein the liquid crystal display panel is driven.