JPH0955728A - Frame sync detection method - Google Patents

Abstract

(57) Abstract: To provide a frame synchronization detection method that is compact, has low power consumption, is highly versatile, and can achieve high speed. SOLUTION: A bit string of input data is rearranged in parallel by an SP conversion circuit 1, a clock input is divided by a frequency divider 4, and a bit string of input data is divided for each of a plurality of divided clocks output. The frequency register 5 takes in.
The synchronization pattern comparison / detection circuit 2 includes a data division register 5
The bit string of is compared with the frame synchronization pattern of the frame synchronization pattern comparison memory 21 for each divided clock to output the number of unmatched bits, and when they match, the frame synchronization detection flag stored in advance corresponding to the divided clock. “1” is output to the clock bit rate pulse generator 6. The clock bit rate pulse generator 6 is a conversion means for converting the bit rate divided by the frequency divider 4 into the bit rate of the clock input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization detection method for detecting a frame synchronization by comparing a bit string of input data with a frame synchronization pattern, and particularly to downsizing of a circuit, power saving, generalization, and The present invention relates to a frame synchronization detection method capable of speeding up processing.

[0002]

2. Description of the Related Art Conventionally, in this type of frame synchronization detection system, for example, as shown in FIG. 8 and Japanese Patent Laid-Open No. 5-235924, a serial-parallel (hereinafter SP) conversion circuit 1 Pattern comparison / detection circuit 91, error bit number comparison circuit 92, and hazard removal circuit 93
Further, the sync pattern comparison / detection circuit 91 includes a sync pattern comparison memory 94 as shown in FIG.
Are stored in advance, the input data string is compared with the frame synchronization pattern by the synchronization pattern comparison detection circuit 91 for each input clock, and then when the error bit number comparison circuit 92 matches the allowable error bit number, The frame sync detection flag is output.

In the sync pattern comparison memory 94, as shown in the figure, the number of unmatched bits of the 8-bit frame sync code, the 8-bit full expansion code as an input address, and the frame sync code for each code. When,
This non-matching bit number code that is output data is stored, and the non-matching bit number code is output using parallel 8 bits to be compared as an address.

The SP conversion circuit 1 is a data delay circuit for rearranging 8 bits of a received data bit string in parallel, and has SP _{2 to} SP ₈ by a 1-bit memory. Details will be described later with reference to FIG. To do. The sync pattern comparison / detection circuit 91 takes out the mismatch bit number code from the sync pattern comparison memory 94 using the 8 bits received from the SP conversion circuit 1 as an address, and outputs it. The error bit number comparison circuit 92 separately compares the preset allowable error bit number code with the mismatch bit number code input from the synchronization pattern comparison and detection circuit 91, and if the mismatch bit number is less than or equal to the allowable error bit number. , And outputs a frame synchronization detection flag to the hazard removal circuit 93. The hazard removal circuit 93 is a flip-flop circuit that removes a hazard signal generated at the output of the error bit number comparison circuit 92 and outputs a reliable frame synchronization detection flag.

Next, a description will be given with reference to FIG. 8 together with the waveform chart of FIG.

When the synchronization bits F _{1 to} F ₈ are input to the SP conversion circuit 1 as 8-bit data in synchronization with the input clock, each of SP _{2 to} SP ₈ of the SP conversion circuit 1 is
When the data input (corresponding to SP ₁ ) is the data F _{8 and} is input to the synchronization pattern comparison / detection circuit 91 with a delay of one clock, the synchronization bits F ₁ to F ₁ are simultaneously applied to SP _{8 to} SP ₁ .
₈ is entered.

The synchronous pattern comparison / detection circuit 91 is SP ₈ ...
In the error bit number comparison circuit 92 for comparing the unmatched bit number code obtained from the sync pattern comparison memory 94 and output with the 8-bit pattern input by SP ₁ as an address, as shown in the figure,
Inevitably, the output will generate a hazard pulse. Therefore, the hazard removal circuit 9 using the flip-flop circuit
3 receives the output of the error bit number comparison circuit 92 and outputs the frame synchronization detection flag from which the hazard has been removed.

[0008]

In the above-mentioned conventional frame synchronization detection method, the error bit number comparison circuit for comparing the predetermined allowable error bit number with the mismatch bit number obtained from the synchronization pattern comparison memory is generally installed. This hinders circuit miniaturization and power saving, and lacks versatility because the result output is only the frame synchronization detection flag.

Further, in the above system, since the synchronous pattern comparison / detection circuit receives the parallel data according to the bit rate of the input clock and stores it in the memory, the operation cycle is limited by the allowable cycle time of the memory. There is a problem that high speed processing is difficult.

The object of the present invention is to reduce the size and power consumption by eliminating the error bit number comparison circuit, and at the same time, to output not only the frame synchronization detection flag but also the number of unmatched bits, which is highly versatile. , In addition,
An object of the present invention is to provide a frame synchronization detection method capable of increasing the speed by increasing the number of synchronization pattern comparison and detection circuits.

[0011]

A frame synchronization detection method according to the present invention is a frame synchronization detection method for detecting a frame synchronization by comparing a bit string of input data with a frame synchronization pattern. A synchronization pattern comparison memory that stores in advance a frame synchronization detection flag that is output when a comparison is made with a pattern, a divider that divides an input clock and outputs a plurality of divided clocks, and this divider A sync pattern comparison and detection circuit that outputs the frame synchronization detection flag stored in advance for each divided clock when the bit string of the data input for each divided clock output by It has and.

Further, the sync pattern comparison memory stores in advance all bit string patterns to be compared with the frame sync pattern together with the number of unmatched bits, and the sync pattern comparison / detection circuit, when the bit string of data is input, The number of unmatched bits is fetched from the comparison memory and output.

The present system is provided with a data division register for taking in a bit string of data input for each divided clock output from the divider, and the sync pattern comparison / detection circuit is configured to detect the data division. A bit string of data may be received from the register.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing a first embodiment of the present invention. In the frame synchronization detection method shown in FIG. 1, the SP (serial / parallel) conversion circuit 1, the synchronization pattern comparison / detection circuit 2, and the hazard removal register 3 are used.
Further, the synchronization pattern comparison / detection circuit 2 includes a synchronization pattern comparison memory 21 to input data and clock.

In the first embodiment, compared with the conventional one,
While the error bit number comparison circuit 92 (FIG. 8) is deleted,
As shown in FIG. 2, a storage area for a frame synchronization detection flag is added to the synchronization pattern comparison memory 21 for output data as compared with the conventional synchronization pattern comparison memory 94 (FIG. 9). The pattern comparison detection circuit 2 outputs the number of error bits and the frame synchronization detection flag. Therefore, the hazard removal register 3 removes the hazard from the two outputs of the error bit number and the frame synchronization detection flag.

In the storage area of the frame synchronization detection flag,
N-bit (8 bits as shown in this example) synchronization pattern (in this example, "10110010") that becomes the address of the synchronization pattern comparison memory 21
The frame synchronization detection flag "1" is set only for the number of unmatched bits "0" and the frame synchronization detection flag "0" is set for other numbers of unmatched bits.

Next, a first embodiment will be described with reference to FIGS. 1 to 3 as well.

The SP conversion circuit 1 is a data delay circuit for rearranging 8 bits of a received data bit string in parallel as in the conventional case, and has SP _{2 to} SP ₈ by 1-bit memory. As shown in FIG. 3, the 8 bits F _{1 to} F ₈ of the data bit string received together with the input clock are
SP ₂ to SP ₈ are sequentially delayed for each clock, and if the input corresponding to SP ₁ is data F ₈ , then SP ₈
To SP ₁ parallel to set the synchronization pattern data F ₁ to F _8, respectively, are simultaneously output.

The sync pattern comparison / detection circuit 2 has a sync pattern comparison memory 21 as shown in FIG.
_A set of data of _{8 to} SP ₁ is used as an address code, and 4 bits of code of the number of mismatched bits with the frame synchronization code and 1 bit of the frame synchronization detection flag “1 or 0” are taken out from the synchronization pattern comparison memory 21 and output. To do. As a result of searching the address code, when the frame sync detection flag "0" is output due to a mismatch with the frame sync code, ROM (read only memory) is used as the sync pattern comparison memory 21, so it is sufficiently shorter than the flag "1". Pseudo-pulses with time occur as a hazard.

The hazard elimination register 3 has a known circuit for eliminating the generated hazard.

In the first embodiment, the error bit number comparison circuit is deleted as compared with the prior art, but the frame synchronization detection flag added to the synchronization pattern comparison memory is only 1 bit for each address. , The circuit is downsized and power is saved compared with the conventional one. Furthermore,
Since the error bit number information is output in addition to the frame synchronization detection flag, it is highly versatile.

Next, a second embodiment will be described with reference to FIGS. 4 to 7.

First, as shown in the functional block diagram of FIG. 4, in the second embodiment, the same SP conversion circuit 1 and synchronization pattern comparison / detection circuit 2 as in the first embodiment are used.
It is assumed that a divider 2 and two data divider registers 5a and 5b corresponding to the divide-by-two are provided for a and 2b. Normally, M data dividers and M sync pattern comparison / detection circuits are provided for the M divider. Further, in order to remove the hazards generated by the plurality of synchronization pattern comparison / detection circuits 2-, these outputs,
A clock bit rate pulse generator 6 corresponding to each of the error bit number code and the frame synchronization detection flag
a and 6b are provided.

Since the SP conversion circuit 1 has already been described, a description thereof will be omitted. Sync pattern comparison and detection circuit 2
Since a and 2b are also the same as described above, description thereof will be omitted.
The divide-by-two frequency divider 4 divides the input clock into 1/2 to generate divided-by-two clocks A and B. In the case of the frequency division by two, the frequency division clock A using the fall of the input clock is inverted to generate the frequency division clock B, the frequency division clock A is supplied to the data frequency division register 5a, and the frequency division clock B of the other side is generated. It shall be supplied to the data division register 5b. Further, the data input is in the order of D ₀ , D ₁ , and.

As shown in FIGS. 4 and 5, the data division register 5a includes SPa1 to SPa1 of 1-bit memory.
Has SPa8, by a two-divided clock A, takes in the output of the SP ₁ to SP ₈ of the SP converter 1. As a result, S
The Pa1, the data D _1, D _3, it is assumed that - the odd group of every is sequentially read. On the other hand, the data division register 5b also has SPb1 to Sb of 1-bit memory similarly.
Has PB8, by a two-divided clock B, receives the output of the SP ₁ to SP ₈ of the SP converter 1, as a result, SP
The data D ₀ , D ₂ , to and every other even number are sequentially fetched into b1.

The sync pattern comparison / detection circuit 2a fetches the data of SPa1 to SPa8 of the data division register 5a in parallel, and incorporates a sync pattern comparison memory 21.
To compare. Similarly, the synchronization pattern comparison / detection circuit 2b
In parallel, the data of SPb1 to SPb8 of the data division register 5b is fetched in parallel and compared by the built-in synchronization pattern comparison memory 21.

Here, the frame synchronization pattern is set to the data D.
If ₁ to D _8, the data division register 5b SPb1
When the data D ₈ is input to the clock bit rate pulse generator 6b, the sync pattern comparison / detection circuit 2b outputs the mismatch bit number code “0” to the clock bit rate pulse generator 6a.
output to b.

Clock bit rate pulse generator 6a,
6b, since the received data becomes a pulse of the section T ₁ that spans the sections T ₂ and T ₃ of the two pieces of data D ₈ and D _9, respectively, it receives the halved clocks A and B and receives from the synchronization pattern comparison / detection circuit 2b. The received hazard is removed, and only the error bit number or the frame synchronization detection flag is output in parallel according to the bit rate and timing corresponding to the clock input section T ₂ . That is, the clock bit rate pulse generator 6a outputs a 4-bit mismatch bit number code, and the clock bit rate pulse generator 6b outputs a 1-bit frame synchronization detection flag. It should be noted that the two inputs obtained by dividing the frequency by two are converted to the bit rate of the clock input and then serially output by the OR circuit.

In the second embodiment, since the speed of the clock input, that is, the bit rate of the data input is reduced to ½ by the frequency divider, the synchronous pattern comparison / detection circuit can be used with respect to the allowable cycle time of the memory. There is a margin in the comparison operation, and the speed of the memory comparison process can be increased.

In the above description, the sync pattern is the 8-bit frame sync code, but N bits may be used to increase or decrease both the address code of the sync pattern comparison memory and the mismatch bit number code. Further, the frame sync detection flag is set to "0" as the number of mismatch bits, but the allowable error bit number "3" can be set by setting the frame sync detection flag up to the number of mismatch bits "3", for example.

Further, in the above description, only the divide-by-two frequency division is explained as the frequency divider. However, as M frequency division, M number of M frequency division clocks are generated so as to cause the rise of the frequency division clock for each bit of the data input. As a result, it is possible to achieve higher speed.

In the above description, the functional blocks are illustrated and described, but the functional distribution of the blocks can be freely changed as long as the above functions are satisfied by separation and merging, so the above description does not limit the present invention.

[0034]

As described above, according to the present invention, the error bit number comparison circuit is eliminated as compared with the prior art, and
Since the frame sync detection flag of only 1 bit is added to the sync pattern comparison memory and the frame sync detection flag is directly output from the sync pattern comparison and detection circuit, the main circuit can be composed of a ROM (read-only memory), which is miniaturized. It is possible to obtain a frame synchronization detection method that saves power and saves power.

In addition to the frame synchronization detection flag,
Since the error bit number information is also output, a versatile frame synchronization detection method can be obtained.

A frequency-divided clock divided by M is generated from the clock input, and each of the M sync pattern comparison / detection circuits compares the data input with the frame sync detection flag of the memory due to the speed reduced to 1 / M. Therefore, the synchronization pattern comparison / detection circuit has a margin in the operation for comparison with the allowable cycle time of the memory, and it is possible to obtain the frame synchronization detection method capable of speeding up the comparison processing.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a memory area diagram showing an embodiment of the present invention.

FIG. 3 is a waveform diagram showing an embodiment in FIG.

FIG. 4 is a functional block diagram showing another embodiment of the present invention.

5 is a waveform diagram on the A side showing the embodiment in FIG.

6 is a B-side waveform diagram showing the embodiment in FIG. 4. FIG.

FIG. 7 is a waveform diagram on the output side showing the embodiment in FIG.

FIG. 8 is a functional block diagram showing an example of the related art.

FIG. 9 is a memory area diagram showing a conventional example.

10 is a waveform chart showing an example in FIG.

[Explanation of symbols]

 1 SP (serial parallel) conversion circuit 2, 2a, 2b Sync pattern comparison detection circuit 3 Hazard removal register 4 Divider 2 5a, 5b Data division register 6a, 6b Clock bit rate pulse generator 21 Sync pattern comparison memory

Claims (5)

[Claims] 1. A frame synchronization detection method for detecting a frame synchronization by comparing a bit string of input data with a frame synchronization pattern, and outputting a frame synchronization when the bit string of input data is compared with the frame synchronization pattern and coincides with each other. A sync pattern comparison memory that stores a detection flag in advance, and a sync pattern comparison and detection circuit that outputs the frame sync detection flag when a bit string of input data is compared with a frame sync pattern and coincides with each other. Frame synchronization detection method. 2. A frequency divider that divides an input clock and outputs a plurality of divided clocks in a frame synchronization detection method for detecting a frame synchronization by comparing a bit string of input data with a frame synchronization pattern. A frame synchronization detection method, comprising: a synchronization pattern comparison and detection circuit that detects a frame synchronization by comparing a bit string of data input for each divided clock output by the divider with the frame synchronization pattern. 3. A frame synchronization detection method for detecting a frame synchronization by comparing a bit string of input data with a frame synchronization pattern, and outputting a frame synchronization when the bit string of input data is compared with the frame synchronization pattern and coincides with each other. A synchronization pattern comparison memory that stores a detection flag in advance, a divider that divides an input clock to output a plurality of divided clocks, and a data input for each divided clock output by the divider. A frame synchronization detection method, comprising: a synchronization pattern comparison and detection circuit that outputs the frame synchronization detection flag stored in advance for each divided clock when a bit string is compared with the frame synchronization pattern and coincides. 4. The sync pattern comparison memory according to claim 1 or 3, wherein all the bit string patterns to be compared with the frame sync pattern are stored together with the number of mismatch bits, and the sync pattern comparison / detection circuit is configured to A frame synchronization detection method, wherein when a bit string is input, the number of unmatched bits is extracted from the synchronization pattern comparison memory and output. 5. The data division register according to claim 2 or 3, further comprising a data division register for taking in a bit string of data input for each division clock output from the frequency divider. A frame synchronization detection method characterized by receiving a bit string of data from a data division register.