JPH0964295A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] Current cut method by low leakage circuit and MO
Provided is a semiconductor memory device capable of reducing the standby current by cutting off the off-state current of a MOS transistor without increasing the layout area in combination with the layout method of the S-transistor gate length. A large-capacity DRAM using a hierarchical word system, in a main word driver forming a row decoder for selecting a row direction of a memory array, a first stage CMO
The off current I flowing through the PMOS transistor P1 that constitutes the S inverter is
A low-leakage circuit for cutting 1 is connected, and 2
The gate length of the NMOS transistor N2 forming the CMOS inverter of the stage is
It is laid out larger than other MOS transistors in order to cut off current I2 flowing in the.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and is particularly effective when applied to a semiconductor memory device suitable for reducing the standby current without increasing the layout area in a memory such as a large capacity DRAM. Regarding technology.

[0002]

2. Description of the Related Art For example, according to a study by the inventor, in a portable computer using a battery or a battery as a power source, not only power consumption during operation but also power consumption during standby has been emphasized. Therefore, it is considered that a demand for a low-power memory with a small standby current is desired for the memory used in such a computer.

For example, as a technique for reducing the standby current, as in the semiconductor device described in Japanese Patent Laid-Open No. 6-208790, a MOS transistor is used in a two-stage inverter circuit structure of a CMOS structure composed of a PMOS transistor and an NMOS transistor. By setting the threshold value Vth and varying the power supply during standby, the standby current can be kept low.

[0004]

By the way, in the above-described standby current reduction technique, the standby current due to the increase of the off current is reduced by increasing Vth, and instead, the channel width is increased to increase the speed. Therefore, the number of steps for controlling Vth increases, the cost increases, and the increase in chip size due to the increase in channel width may cause a problem.

Further, in order to reduce the off-current during standby, a method of connecting a low leak circuit to the power supply potential side of the PMOS transistor of the front stage inverter and the ground potential side of the NMOS transistor of the rear stage inverter is also used. However, even in this case, a dedicated wiring for connecting to the low-leakage circuit is required, which may cause an increase in chip size.

Therefore, an object of the present invention is to turn off the MOS transistor without increasing the layout area by combining the method of cutting the current by the low leakage circuit and the layout method characterized by setting the gate length of the MOS transistor. It is an object of the present invention to provide a semiconductor memory device capable of cutting off a current and reducing a standby current.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device of the present invention has two
The present invention is applied to a semiconductor memory device having a driver circuit including MOS transistor circuits connected in series in more than two stages, and includes a low leakage circuit that cuts off a current by a switching element and M of each of the MOS transistor circuits.
By combining this with a layout design in which the gate length of the OS transistor is set to a predetermined dimensional ratio, the leakage current of the odd-stage MOS transistor circuits and the even-stage MOS transistor circuits during standby is reduced.

Specifically, the odd-numbered MOS transistor circuits and the even-numbered MOS transistor circuits have a CMOS structure of PMOS transistors and NMOS transistors, and leaks in the odd-numbered MOS transistor circuits during standby. Regarding the interruption of the current, a low leak circuit is connected to the power supply potential side of the PMOS transistors of the odd-numbered MOS transistor circuits.

Regarding shutting off the leakage current flowing through the even-numbered MOS transistor circuits during standby, the PMOS transistors and NMOS transistors of the odd-numbered MOS transistor circuits and the even-numbered M transistors are used.
PMOS transistor and NMO of OS transistor circuit
Set the gate lengths of the S transistors to Lgp1 to Lgp, respectively.
(N-1), Lgn1 to Lgn (n-1), Lgp2
When Lgp (n) and Lgn2 to Lgn (n) are used, Lgp1 to Lgp (n-1) and Lgp2 to Lgp
(N), Lgn1 to Lgn (n-1) << Lgn2 to Lg
p (n) or Lgp1 to Lgp (n-1) = Lgp2 to Lgp (n) << Lgn1 to Lgn (n-1) = Lgn2 to Lgn
The setting is made so as to satisfy the relationship of (n).

In particular, the driver circuit is applied to a control logic circuit of a main word driver or a peripheral circuit.

[0013]

According to the semiconductor memory device described above, the MOS transistor circuits connected in series in two or more stages are
By designing a combination of a low-leakage circuit and a gate length layout of MOS transistors, the odd-numbered M
Regarding the leakage current flowing through the OS transistor circuit during standby, by connecting a low leakage circuit to the power supply potential side of this MOS transistor circuit and turning off the switching element of this low leakage circuit, the odd-numbered MO
It is possible to cut off the leak current flowing through the S transistor circuit.

Regarding the leakage current flowing in the even-numbered MOS transistor circuits during standby, the odd-numbered and even-numbered PMOS transistors are
By setting the gate length of the NMOS transistor to a predetermined dimensional ratio, for example, making the gate length of the even-numbered NMOS transistor larger than that of the other MOS transistors, it is possible to cut off the leak current flowing in the even-numbered MOS transistor circuit. .

In particular, in a main word driver, for example, a main word driver using a hierarchical word system, a method of reducing standby current due to off current is as follows.
By combining the low-leakage circuit and the gate length layout, for example, the current flowing in the odd-numbered stage PMOS transistor is cut and the even-numbered stage NM is cut off.
The current flowing through the OS transistor can also be cut.

Also by applying to the control logic circuit of the peripheral circuit, the reduction of the off current of the odd-numbered PMOS transistors can be dealt with by the connection of the low leak circuit, and the off current of the even-numbered NMOS transistors can be further reduced. The reduction of can be taken by making the gate length of this NMOS transistor larger than that of other MOS transistors.

As a result, a low power product can be obtained by reducing the standby current. For example, a large capacity D
In addition to RAM, low-power memories and memory modules, especially memories used in portable computers, require low-power memories with low standby current. Memory can be provided.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a chip layout diagram showing a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a row decoder in the semiconductor memory device of this embodiment, and FIG. 3 is a CMOS. It is a layout diagram showing a main part of an inverter.

First, the structure of the semiconductor memory device of this embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment uses a hierarchical word system in which, for example, a word line is divided into multiple sub-word lines, and the multi-divided sub-word lines share a set of column decoder and row decoder. Large capacity DRA
M, a plurality of memory arrays MAT having a plurality of memory cells, a row decoder RDEC for selecting a row direction of the memory array MAT, a column decoder CDEC for selecting a column direction, and a peripheral circuit PR. Row address buffer RAB, column address buffer C
AB, address multiplexer AMX, timing generation circuit TG, data input / output circuit I / O and the like are formed on one semiconductor chip by a well-known semiconductor manufacturing technique.

In this DRAM, for example, as shown in FIG. 1, a memory array MAT is divided and arranged at the upper and lower ends of a semiconductor chip, and two memory arrays MAT are arranged at the upper and lower ends, respectively. The row decoders RDEC are arranged in pairs at the center. Further, column decoders CDEC corresponding to the respective memory arrays MAT are arranged on the central side of the memory arrays MAT arranged at the upper and lower ends.

The row decoder RDEC has a main word driver MW for selecting a word line in the row direction.
D, an FX driver FXD, and a low leak circuit LL which is a feature of the present invention, and further includes a memory array M.
Sub word driver SW in the row direction within the AT placement area
D is arranged. Further, sense amplifiers SA are arranged in the column direction in the arrangement area of the memory array MAT.

A row address buffer RAB and a column address buffer CA are provided at the center of the semiconductor chip.
B, peripheral circuit P including address multiplexer AMX, timing generation circuit TG, data input / output circuit I / O, etc.
R is arranged, and a bonding pad PAD for external connection is provided in the central portion.

In the DRAM laid out as described above, the configuration of the main word driver MWD, the sub word driver SWD, the low leak circuit LL, and particularly the operation circuit at the time of standby, which is a feature of this embodiment, is shown in FIG. The circuit configuration will be described below in order.

The main word driver MWD is a two-stage C
There are a plurality of sets of MOS transistor circuits in which MOS inverters are connected in series, and each set of MOS transistor circuits has a CMOS structure with PMOS transistors P1 and P2 and NMOS transistors N1 and N2 connected between the power supply potential VPP and the ground potential. It is configured by being connected in two stages.

Then, to the main word driver MWD, for example, signals / X0 to / Xi which are at "H" level in the standby state are input to the gates of the first stage, and the MOS transistor circuit of the first stage outputs the signals "X" in the standby state. L "
A signal that becomes a level is obtained, and further, a signal that becomes an "H" level is obtained from the second-stage MOS transistor circuit during standby. Complementary signals having different voltage levels are main word line selection signals MWL0 to MWLi, / MWL0 to /
It is input to the sub-word driver SWD as MWLi.

This sub-word driver SWD includes PMOS transistors P3 and NM as shown in FIG.
CMOS structure with OS transistor N3 and NMO
A plurality of sets of MOS transistor circuits including an S-transistor N4 are provided, and a signal having an "H" level during standby is input to the gate of the CMOS structure and the other NM.
The gate of the OS transistor N4 is "L" during standby
The level signal is input, and the sub-word line selection signals SWL0 to SWLi are output.

In the sub-word driver SWD, the power supply potential sides of the PMOS transistor P3 of CMOS structure and the other NMOS transistor N4 are connected to FX signals FX0 to FXi output from the FX driver FXD.

The low leak circuit LL is composed of a PMOS transistor P4 (switching element) connected to the first-stage PMOS transistor P1 of the main word driver MWD and having its source connected to the power supply potential VPP.
The gate of the OS transistor P4 is supplied with the signal / φ1 which is at "H" level during standby, and PM
By turning off the OS transistor P4,
The leakage current in the standby state that flows through the first-stage PMOS transistor P1 of the main word driver MWD connected to the drain of the PMOS transistor P4 is cut off.

Next, the operation of the present embodiment will be described with a detailed description of each constituent element of the DRAM and an outline of the operation.

In the memory array MAT, a plurality of word lines arranged in parallel in the horizontal direction in FIG. 1, a plurality of complementary bit lines arranged in parallel in the vertical direction, and complementary bits to these word lines. A plurality of dynamic memory cells arranged in a grid pattern are included at the intersections of the lines.

As for the word lines forming this memory array MAT, the main word driver MWD selects the upper word line, the FX driver FXD activates the signal selecting the lower word line, and the sub word driver SWD activates the main word line. And the signal of the FX line is decoded to select one word line.

The row decoder RDEC is supplied with an i-bit complementary internal address signal, that is, a non-inverted internal address signal and an inverted internal address signal from the row address buffer RAB, for example.

The main word driver MWD is selectively activated by setting the X timing signal to "H" level. In this operating state, the row decoder R
The DEC fetches and holds the row address signal transmitted from the address multiplexer AMX according to the X timing signal supplied from the timing generation circuit TG. Also, these row address signals are formed and supplied to the row decoder RDEC.

The address multiplexer AMX is a row address which is time-divisionally supplied via an external terminal when, for example, the DRAM is in a normal operation mode and timing "L" level is supplied from the timing generation circuit TG. A signal is selected and transmitted to the row address buffer RAB.

On the other hand, the complementary bit line forming the memory array MAT is coupled to the unit amplifier circuit corresponding to the sense amplifier SA at one side. In addition to the plurality of unit amplifier circuits provided corresponding to the complementary bit lines of the memory array MAT, the sense amplifier SA also includes an NMOS transistor and a complementary bit line for equalizing the complementary bit line pair when the DRAM is in standby. Includes an NMOS transistor that supplies about 1/2 of the voltage of the power supply, an NMOS transistor that connects the complementary bit line to the I / O line, and the like.

The column decoder CDEC is selectively activated by setting the Y timing signal to "H" level. In this operating state, the column decoder CD
The EC decodes the complementary internal address signal and selectively sets the corresponding bit line selection signal to the “H” level.

The column address buffer CAB fetches and holds the column address signal time-divisionally supplied via the external terminal in accordance with the Y timing signal supplied from the timing generation circuit TG. Further, a complementary internal address signal is formed based on these column address signals. Of these, the upper several bits are supplied to the main amplifier selector, and the remaining complementary internal address signals are supplied to the column decoder CDEC.

The timing generation circuit TG receives a row address strobe signal as an activation control signal from an external device,
A column address strobe signal, a write enable signal, and an output enable signal are supplied, the operation mode of the DRAM is determined based on these signals, and various timing signals are formed and supplied to each section of the DRAM.

As described above, the respective constituent elements of the DRAM operate, the word line is selected by the row decoder RDEC by the main word driver MWD, the sub word driver SWD, the FX driver FXD, etc., and the complementary bit line by the column decoder CDEC. , And data can be input / output by writing, erasing and reading with respect to the memory cells of the memory array MAT arranged at the intersections of the word lines and the complementary bit lines.

Next, a method of reducing the standby current due to the off current in the main word driver MWD, which is a feature of this embodiment, will be described.

In the main word driver MWD shown in FIG. 2, the off-current I1 flowing in the first-stage CMOS inverter is the off-current I1 flowing in the second-stage CMOS inverter while the low-leakage circuit LL is connected to the PMOS transistor P1. I2 can be dealt with by setting the gate length of each of the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 to a predetermined dimensional ratio for layout.

First, regarding the reduction of the off current I1 flowing through the PMOS transistor P1 constituting the first stage CMOS inverter, the source of the PMOS transistor P1 is a low leakage circuit LL, that is, the source connected to the power supply potential VPP. The drain of the PMOS transistor P4 forming the leak circuit LL is connected.

This low leak circuit LL and the first stage CMOS
In the connected state with the inverter, during standby,
The signal / φ1 which becomes the "H" level is input to the gate of the PMOS transistor P4 of the low leak circuit LL, whereby the PMOS transistor P4 is turned off so that no current flows.

At this time, in the main word driver MWD, no current flows from the low leak circuit LL to the first-stage PMOS transistor P1 and the PMO
A signal / Xi which is at "H" level during standby is input to the commonly connected gates of the S transistor P1 and the NMOS transistor N1.

As a result, the main word driver MWD
The leak current I1 flowing through the first-stage PMOS transistor P1 can be cut, and the "H" level signal / Xi input to the commonly connected gates
By turning off the PMOS transistor P1 and turning on the NMOS transistor N1, it is possible to output a signal that becomes "L" level from the commonly connected drains in standby.

On the other hand, regarding the reduction of the off current I2 flowing through the NMOS transistor N2 forming the second-stage CMOS inverter, the first-stage PMOS transistor P1 and NMOS transistor N1 and the second-stage PMOS transistor P2 and NMOS transistor N2 are used. The gate length of is set to a predetermined dimensional ratio.

That is, the PMOS transistor P1 and the NMOS transistor N1 in the first stage, and the PMO in the second stage
The gate lengths of the S transistor P2 and the NMOS transistor N2 are Lgp1, Lgn1, Lgp2, and Lgn2, respectively.
If Lgp1, Lgp2, Lgn1 << Lgn
Set so that the relationship of 2 is satisfied.

For example, as shown in FIG.
By setting the gate length of the MOS transistor N2 to be larger than that of the other PMOS transistors P1 and P2 and the NMOS transistor N1 (only the PMOS transistor P2 is shown in the figure), for example, the dimension ratio is 6: 5 or 3: 2. The leak current I2 can be cut by reducing the current flowing through the NMOS transistor N2 in proportion to the gate length.

At this time, during standby, as described above, the operation of the first-stage CMOS inverter causes the operation of the second-stage PMOS transistor P2 and NMOS transistor N2.
A signal of "L" level is input to the commonly connected gates.

As a result, the main word driver MWD
The leak current I2 flowing through the second-stage NMOS transistor N2 can be cut, and the PMO can be changed by the “L” level signal input to the commonly connected gates.
By turning on the S transistor P2 and turning off the NMOS transistor N2, it is possible to output a signal which becomes "H" level in standby from the commonly connected drains.

In this layout, it is possible to set, for example, Lgp1 = Lgp2 << Lgn1 = Lgn2, and in this case PM
OS transistor P1 and PMOS transistors P2 and N
Since the MOS transistor N1 and the NMOS transistor N2 can be laid out with the same size, the layout design can be easily performed.

From the above, the main word driver MWD
In the first stage CMOS inverter
NMO that cuts off current I1 flowing through OS transistor P1 and constitutes the second stage CMOS inverter
The off current I2 flowing through the S transistor N2 can also be cut.

Therefore, according to the DRAM of this embodiment, especially the main word driver MWD using the hierarchical word system.
In combination with the low-leakage circuit LL connected to the first-stage CMOS inverter and the gate length layout of the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 of the first-stage and second-stage CMOS inverters, The leak circuit LL causes the first stage PMO
The leak current I1 flowing through the S-transistor P1 is cut off, and the second-stage NMOS is provided depending on the gate length layout
The leakage current I2 flowing through the transistor N2 can be cut to reduce the standby current due to the off current.

(Second Embodiment) FIG. 4 is a circuit diagram showing a control logic circuit of a peripheral circuit in a semiconductor memory device according to a second embodiment of the present invention.

In the semiconductor memory device of this embodiment, the word line is divided into multiple sub-word lines as in the first embodiment.
A large-capacity DRAM using a hierarchical word system in which one set of column decoders and row decoders are shared by these multi-divided sub-word lines is used. A difference from the first embodiment is that a combination of a low leak circuit and a gate length layout is used. Is applied to the control logic circuit of the peripheral circuit.

That is, in the DRAM of the present embodiment, the control logic circuit of the peripheral circuit PR has a circuit configuration as shown in FIG. 4, and is a plurality of sets of MOS transistor circuits which serially connect a plurality of stages of CMOS inverters. Each set of MOS transistor circuits includes PMOS transistors P1 to P4 and NMOS transistors N1 to N4 connected between the power supply potential VDD and the ground potential.
And a CMOS structure.

In this control logic circuit, the low-leakage circuit LL similar to that of the first embodiment is connected to the sources of the PMOS transistors P1 and P3 which form the odd-stage CMOS inverters such as the first and third stages. The odd-numbered PMOS transistors P1,
The off currents I1 and I3 flowing through P3 can be reduced by using the low leak circuit LL.

On the other hand, even-numbered Cs such as the second and fourth stages
NMOS transistor N forming a MOS inverter
The gate lengths of N2 and N4 are the same as those of the first embodiment except for other PMO
S transistors P1 to P4, NMOS transistor N
1 and N3, the off currents I2 and I4 of the even-numbered NMOS transistors N2 and N4 are formed.
Can be reduced.

For example, in FIG. 4, the gate lengths of the PMOS transistors P1 to P4 and the NMOS transistors N1 to N4 in the first to fourth stages are set to Lgp1 to Lgp, respectively.
4, Lgn1 to Lgn4, Lgp1, Lgn1, Lgp2, Lgp3, Lgn3
By setting so that the relationship of Lgp4 << Lgn2, Lgn4 is satisfied, the off-current I flowing through the even-numbered NMOS transistors N2, N4
2, 2 can be reduced by the layout design of the gate length.

In this layout, for example, Lgp1 = Lgp2 = Lgp3 = Lgp4 << Lgn1 =
It is also possible to set as Lgn2 = Lgn3 = Lgn4. In this case, since MOS transistors of the same kind can be laid out with the same size, layout design can be easily performed.

Therefore, according to the DRAM of this embodiment, especially in the control logic circuit of the peripheral circuit PR,
By combining the low leak circuit LL connected to the odd-numbered CMOS inverters and the layout for increasing the gate lengths of the NMOS transistors N2 and N4 of the even-numbered CMOS inverters, the low-leakage circuit LL allows the odd-numbered PMOS transistors to be connected. The leakage currents I1 and I3 flowing through the transistors P1 and P3 can be cut, and the leakage currents I2 and I4 flowing through the even-numbered NMOS transistors N2 and N4 can be cut according to the gate length layout to reduce the standby current due to the off current. it can.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the DRAM of the above-mentioned embodiment has been described as a large capacity DRAM using the hierarchical word system by the CMOS sub-word driver system, but the present invention is not limited to the above-mentioned embodiment.
The same applies to the NMOS sub-word driver system, and the present invention is particularly effective in a circuit that produces complementary signals, for example, a circuit having many drivers such as a decoder.

Regarding the application of the present invention, a large capacity D
In addition to RAM, low power memories and memory modules, especially memories used in portable computers such as PCs, require low power memories with low standby current. The present invention provides low power memories with high added value. Can be provided.

[0067]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). MOS connected in series with two or more stages
By connecting a low-leakage circuit to the power supply potential side of the odd-numbered MOS transistor circuit with respect to the transistor circuit, it is possible to turn off the switching element of this low-leakage circuit and prevent current from flowing. It is possible to reduce the leakage current flowing through the odd-numbered MOS transistor circuits during standby.

(2). MOS connected in series with two or more stages
In the transistor circuit, by increasing the gate length of the even-numbered NMOS transistors as compared with the gate lengths of the other MOS transistors, the even-numbered MO transistors are
It is possible to reduce the leakage current flowing through the S transistor circuit during standby.

(3) In particular, in the main word driver, the current flowing in the odd-numbered PMOS transistors can be cut and the current flowing in the even-numbered NMOS transistors can also be cut. Can be reduced.

(4) Especially in the control logic circuit of the peripheral circuit, the reduction of the off current of the odd-stage PMOS transistor can be dealt with by connecting the low-leakage circuit, and the even-stage NMOS transistor The reduction of the off current can be dealt with by making the gate length of this NMOS transistor larger than that of other MOS transistors.

(5) According to the above (1) to (4), it is possible to obtain low-power products by reducing the standby current. For example, in addition to large-capacity DRAM, low-power memories and memory modules, especially portable computers. It is possible to provide a high-value-added low-power memory to meet the demand for a low-power memory with a low standby current used in.

[Brief description of drawings]

FIG. 1 is a chip layout diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a row decoder in the semiconductor memory device according to the first embodiment.

FIG. 3 is a layout diagram showing a main part of the CMOS inverter according to the first embodiment.

FIG. 4 is a circuit diagram showing a control logic circuit of a peripheral circuit in a semiconductor memory device which is Embodiment 2 of the present invention.

[Explanation of symbols]

 MAT memory array RDEC row decoder CDEC column decoder PR peripheral circuit RAB row address buffer CAB column address buffer AMX address multiplexer TG timing generator circuit I / O data input / output circuit MWD main word driver FXD FX driver LL low leak circuit SWD sub word driver SA sense Amplifier PAD Bonding pad VPP Power supply potential

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukie Hide Suzuki 2326 Imai, Ome City, Tokyo Inside Device Development Center, Hitachi Ltd. In-house (72) Inventor Kentaka Saito 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Textile Instruments Co., Ltd.

Claims (6)

[Claims] 1. Ms cascaded in at least two stages or more
A semiconductor memory device having a driver circuit for generating complementary signals having different voltage levels by an OS transistor circuit, wherein a low-leakage circuit connected to the MOS transistor circuit and blocking a current by a switching element, and the MOS transistor circuit, respectively. And a layout design for setting the gate length of the MOS transistor to a predetermined dimensional ratio to reduce the leak current of the odd-numbered MOS transistor circuits and the even-numbered MOS transistor circuits during standby. Semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein the odd-stage MOS transistor circuits and the even-stage MOS transistor circuits are PMOS transistors connected between a power supply potential and a ground potential, respectively. A semiconductor memory device having a CMOS structure with an NMOS transistor. 3. The semiconductor memory device according to claim 2, wherein the PMOS of the odd-numbered MOS transistor circuit is provided.
A semiconductor memory characterized in that the low-leakage circuit is connected to a power supply potential side of a transistor, and a switching element of the low-leakage circuit is turned off to cut off a leak current during standby in the odd-numbered MOS transistor circuits. apparatus. 4. The semiconductor memory device according to claim 2, wherein the PMOS of the odd-numbered MOS transistor circuit is provided.
The gate lengths of the transistor and the NMOS transistor and the PMOS transistor and the NMOS transistor of the even-numbered MOS transistor circuit are Lgp1 respectively.
~ Lgp (n-1), Lgn1 to Lgn (n-1), L
gp2-Lgp (n), Lgn2-Lgn (n), Lgp1-Lgp (n-1), Lgp2-Lgp
(N), Lgn1 to Lgn (n-1) << Lgn2 to Lg
The even-numbered MOSs are set so that the relationship of p (n) is satisfied.
A semiconductor memory device, characterized in that a leakage current flowing through a transistor circuit during standby is cut off. 5. The semiconductor memory device according to claim 2, wherein the PMOS transistors of the odd-numbered MOS transistor circuits are provided.
The gate lengths of the transistor and the NMOS transistor and the PMOS transistor and the NMOS transistor of the even-numbered MOS transistor circuit are Lgp1 respectively.
~ Lgp (n-1), Lgn1 to Lgn (n-1), L
When gp2 to Lgp (n) and Lgn2 to Lgn (n), Lgp1 to Lgp (n-1) = Lgp2 to Lgp (n) << Lgn1 to Lgn (n-1) = Lgn2 to Lgn
The even-numbered MOSs are set so that the relationship of (n) is satisfied.
A semiconductor memory device, characterized in that a leakage current flowing through a transistor circuit during standby is cut off. 6. The semiconductor memory device according to claim 1, 2, 3, 4, or 5, wherein the driver circuit is a main word driver or a control logic circuit of a peripheral circuit. .