JPH0983249A - Frequency synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] An object is to provide a frequency synthesizer capable of high-speed channel switching. A PLL synthesizer 1 for inputting a reference signal a and outputting a fixed frequency signal having a predetermined multiple of the frequency of the reference signal a, and a reference signal a serving as a reference clock in accordance with a change in frequency data set from the outside. Of the numerically controlled oscillator 7 that outputs a variable frequency signal whose frequency changes, the reference signal oscillator 6 that supplies the reference signal a to the PLL synthesizer 1 and the numerically controlled oscillator 7, and the output signal of the PLL synthesizer 1 and the numerically controlled oscillator 7. And a mixer 12 for synthesizing the output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer capable of switching channels at high speed.

[0002]

2. Description of the Related Art In recent years, mobile communications such as mobile phones have been widely used in various aspects of society. inside that,
Frequency synthesizers have come to be used as a radio channel switching technique.

FIG. 2 is a block diagram showing the structure of a conventional frequency synthesizer. In FIG. 2, 1 is PLL (ph
ase-locked loop) synthesizer, 2 is a phase comparator for performing phase comparison between the reference signal a and the divided signal b
Is a loop filter that removes harmonics of the output signal of the phase comparator 2, 4 is a voltage controlled oscillator that changes the frequency of the generated signal according to the output voltage of the loop filter 3, and 5 is the frequency of the output signal from the voltage controlled oscillator 4. A frequency divider that divides
Reference numeral 6 is a reference signal oscillator for supplying a reference signal a to the phase comparator 2 in the PLL synthesizer 1.

The operation of the conventional frequency synthesizer configured as described above will be described below. First, the phase comparator 2 performs a phase comparison between the reference signal a output from the reference signal oscillator 6 and the frequency-divided signal b divided by the frequency divider 5, and the frequency-divided signal b is higher than the reference signal a. When the phase is advanced, that is, when the frequency of the divided signal b is higher (higher) than the frequency of the reference signal a, the output voltage of the phase comparator 2 decreases. On the contrary, when the phase of the divided signal b is behind that of the reference signal a, that is, when the frequency of the divided signal b is smaller (lower) than the frequency of the reference signal a, the phase comparator 2
Output voltage rises. The output voltage of the phase comparator 2 has its harmonics removed by the loop filter 3 and becomes the control voltage of the voltage controlled oscillator 4. In the voltage controlled oscillator 4, when the control voltage rises, the frequency of the output signal rises, and when the control voltage falls, the frequency of the output signal falls.
When the frequency becomes higher than the frequency of the reference signal a and the control voltage decreases, the frequency of the output signal of the voltage controlled oscillator 4 decreases. Conversely, when the frequency of the divided signal b becomes lower than the frequency of the reference signal a and the control voltage increases, the frequency of the output signal of the voltage controlled oscillator 4 increases. The output signal of the voltage controlled oscillator 4 is output as the output signal of the PLL synthesizer 1. The frequency of the output signal of the voltage controlled oscillator 4 is divided by the frequency divider 5 and input to the phase comparator 2 as a divided signal b. By changing the frequency division ratio M of the frequency divider 5, the wireless communication channel can be changed. For example, set the division ratio to 1
If it is halved from / 10 to 1/20, a wireless communication channel having a frequency twice the frequency up to then is formed.

The above phase comparator 2, loop filter 3,
When the frequency-divided signal b leads the reference signal a in phase by the loop of the voltage-controlled oscillator 4 and the frequency divider 5, that is, when the frequency of the frequency-divided signal b is high, the output signal of the voltage-controlled oscillator 4 is generated. When the frequency division signal b is delayed in phase with respect to the reference signal a, that is, when the frequency of the frequency division signal b is small, the output of the voltage controlled oscillator 4 is controlled. Control is performed to increase the frequency of the signal. Therefore, control is performed by this loop so that the reference signal a and the divided signal b input to the phase comparator 2 have the same frequency and phase. As a result, the frequency of the output signal of the PLL synthesizer 1 is divided by the frequency divider 5 by the division ratio M, so that the output signal frequency of the PLL synthesizer 1 becomes M times the reference signal a.

Further, when changing the channel of wireless communication, the frequency division ratio M of the frequency divider 5 is changed, but here, the operation of the frequency synthesizer when changing from a channel of a small frequency to a channel of a large frequency. Will be explained. In this case, since the output signal frequency of the voltage controlled oscillator 4 is changed from a low frequency to a high frequency, the frequency division ratio M of the frequency divider 5 is increased. Then, the frequency of the divided signal b input to the phase comparator 2 becomes smaller than the frequency of the reference signal a, so that the output voltage of the phase comparator 2 increases and the output signal frequency of the voltage controlled oscillator 4 increases. Is controlled, and the output signal frequency of the voltage controlled oscillator 4 approaches the frequency after switching. By operating the loop of the PLL synthesizer 1 in this way, the output signal frequency of the PLL synthesizer 1 is switched from a low frequency to a high frequency.

[0007]

However, in the above conventional configuration, when switching the channel of wireless communication,
Since the frequency of the PLL synthesizer 1 is switched by changing the frequency division ratio of the frequency divider 5 and turning the loop of the PLL synthesizer 1, the frequency switching time is PL.
There is a problem that the frequency switching time cannot be shortened due to the limitation by the band of the loop filter 3 of the L synthesizer 1. For example, a frequency synthesizer used for a base station of digital mobile communication or the like requires high-speed channel switching. Therefore, when a conventional frequency synthesizer is used, it is necessary to switch between two frequency synthesizers. There was an increase in cost.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a frequency synthesizer capable of high-speed channel switching.

[0009]

In order to achieve this object, a frequency synthesizer according to claim 1 of the present invention is a PLL synthesizer which inputs a reference signal and outputs a fixed frequency signal of a predetermined multiple of the frequency of the reference signal. And a reference control clock that uses the reference signal as a reference clock to output a variable frequency signal whose frequency changes according to a change in frequency data set from the outside, and a reference that supplies the reference signal to the PLL synthesizer and the numerical control oscillator. It has a configuration including a signal oscillator and a mixer for synthesizing an output signal of the PLL synthesizer and an output signal of the numerically controlled oscillator.

A frequency synthesizer according to a second aspect is the frequency synthesizer according to the first aspect, wherein the PLL synthesizer compares the phases of the reference signal and the divided signal and outputs a phase comparison signal. , A loop filter that removes the harmonics of the phase comparison signal output from the phase comparator, a voltage-controlled oscillator that generates a signal whose frequency corresponds to the output voltage of the loop filter, and the frequency of the signal output from the voltage-controlled oscillator. And a frequency divider for outputting a frequency-divided signal obtained by frequency-dividing to a phase comparator.

A frequency synthesizer according to a third aspect of the present invention is the frequency synthesizer according to the first aspect, in which the numerically controlled oscillator outputs from the counter and the counter which adds phase data based on the frequency data using the reference signal as a reference clock. A storage unit that converts phase data into amplitude data, a D / A converter that converts a digital signal output from the storage unit into an analog signal, and phase data by removing harmonics of the analog signal output from the D / A converter. And a filter that outputs a variable frequency signal whose frequency changes with changes in.

[0012]

With this configuration, the frequency of the PLL synthesizer having a long frequency switching time is fixed by forming a feedback loop, and the frequency of the numerically controlled oscillator having a short frequency switching time is made variable by not forming the feedback loop. Since the frequency can be switched at high speed by the numerically controlled oscillator, high speed channel switching of the frequency synthesizer becomes possible. As a result, even when used in a frequency synthesizer that requires high-speed channel switching, such as a base station for digital mobile communication, two frequency synthesizers are not required, and only one frequency synthesizer is required, reducing the cost of the device. It will be possible. Further, since the PLL frequency synthesizer controls the oscillation frequency according to the phase difference between the reference signal and the frequency-divided signal, an output signal whose phase and frequency of the frequency-divided signal both match the reference signal is accurately generated. be able to. In addition, the numerically controlled oscillator outputs a variable frequency signal that changes according to the phase data based on the externally set frequency data, so that an output signal whose frequency changes rapidly in response to changes in the frequency data can be ensured. Obtainable.

[0013]

【Example】

(Embodiment 1) A frequency synthesizer according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a frequency synthesizer according to this embodiment. In FIG. 1, 1 is a PLL synthesizer, 2 is a phase comparator, 3 is a loop filter, 4 is a voltage controlled oscillator, 5 is a frequency divider, and 6 is a reference signal oscillator. The same reference numerals are given and the description is omitted. Reference numeral 7 is a numerically controlled oscillator that outputs a variable frequency signal, 8 is a counter that adds frequency data using the input reference signal a as a reference clock, and 9 is a storage unit that converts the phase data output from the counter 8 into amplitude data. 10 is a storage unit 9
D / A converter for converting a digital signal output from the converter into an analog signal, 11 is a filter for removing harmonics of the output signal of the D / A converter 10, and 12 is an output signal of the voltage controlled oscillator 4 in the PLL synthesizer 1 and a numerical value. A mixer that synthesizes the output signal of the filter 11 in the controlled oscillator 7 and outputs a signal of the sum frequency, and 13 is a filter that removes unnecessary spurious output from the mixer 12.

The operation of the frequency synthesizer configured as described above will be described below. Since the operation of the PLL synthesizer 1 is the same as the conventional one, the description thereof is omitted, but only the point that the frequency division ratio M of the frequency divider 5 is fixed is different from the conventional one. That is, the output signal frequency of the PLL synthesizer 1 is fixed. As in the conventional example, the reference signal a and the divided signal b input to the phase comparator 2 have the same frequency and phase by the loop of the phase comparator 2, the loop filter 3, the voltage controlled oscillator 4 and the frequency divider 5. Take control to become. As a result, the frequency of the output signal of the PLL synthesizer 1 becomes M because the frequency division ratio of the frequency divider 5 is M.
It is M times the frequency of the reference signal a.

Next, the operation of the numerically controlled oscillator 7 will be described. First, the counter 8 includes the reference signal oscillator 6
The frequency data is added for each clock using the reference signal a output from the clock as a clock. The frequency data means phase data added for each clock, is data for determining the frequency of the numerically controlled oscillator 7, and is set from the outside. In this way, the counter 8 outputs the added phase data. The phase data is converted from the phase data into amplitude data in the storage unit 9 and output. The storage unit 9 stores the amplitude of the sine wave corresponding to each phase,
When the phase data is input from the counter 8, the amplitude data of the sine wave corresponding to this phase data is output. The amplitude data output from the storage unit 9 is converted from a digital signal to an analog signal by the D / A converter 10 and output. Next, the analog signal output from the D / A converter 10 has its harmonics removed by the filter 11, and is output as the output signal of the numerically controlled oscillator 7.

Next, the output signal of the PLL synthesizer 1 and the output signal of the numerically controlled oscillator 7 are combined by the mixer 12,
Output the signal of the sum frequency. The filter 13 removes unnecessary spurious generated from the mixer 12 and outputs it. The output signal from the filter 13 becomes the output signal of the frequency synthesizer.

Here, a case where the channel of wireless communication is changed will be described. First, in the conventional PLL synthesizer 1, when the frequency is switched, P is obtained by changing the frequency division ratio M of the frequency divider 5 and rotating the loop of the PLL synthesizer 1.
Since the frequency of the LL synthesizer 1 is switched,
The frequency switching time is limited by the band of the loop filter 3 of the PLL synthesizer 1, and the frequency switching time cannot be shortened. Therefore, as described above, P
The output signal frequency of the LL synthesizer 1 was fixed. Next, in the numerically controlled oscillator 7, when switching the frequency,
As described above, by changing the frequency data of the counter 8 which is externally set and changing the phase data added by the counter 8 for each clock, the output signal frequency of the numerically controlled oscillator 7 is switched. The switching time of the signal frequency can be shortened. Therefore, the output signal frequency of the numerically controlled oscillator 7 is variable. Since the output signal of the PLL synthesizer 1 and the output signal of the numerically controlled oscillator 7 are combined by the mixer 12 and the sum frequency signal is output, even if the output signal frequency of the PLL synthesizer 1 is fixed, the output signal of the numerically controlled oscillator 7 is fixed. If the frequency is variable, the output signal frequency is variable as a frequency synthesizer. Therefore, the output signal frequency of the PLL synthesizer 1 which takes a long time for frequency switching is fixed, and the output signal frequency of the numerically controlled oscillator 7 having a short frequency switching time is changed by not forming a feedback loop like the PLL synthesizer 1. As a result, the frequency of the frequency synthesizer is switched, so that a frequency synthesizer with a short frequency switching time can be realized. Since the upper limit of the output signal frequency of the numerically controlled oscillator 7 is limited to about 100 MHz, the numerically controlled oscillator 7 alone cannot output a signal having a frequency of 1 GHz or higher required for PHS or the like, and constitutes a frequency synthesizer. I can't.

As described above, according to the present embodiment, the frequency of the PLL synthesizer 1 having a long frequency switching time is fixed, and the frequency of the numerically controlled oscillator 7 having a short frequency switching time is variable, whereby the numerically controlled oscillator 7 is changed. Since the frequency can be switched at high speed, the high-speed channel switching of the frequency synthesizer becomes possible.

[0019]

As described above, according to the present invention, a PLL synthesizer for inputting a reference signal and outputting a fixed frequency signal having a predetermined multiple of the frequency of the reference signal, and a frequency externally set using the reference signal as a reference clock. Numerically controlled oscillator that outputs a variable frequency signal whose frequency changes according to changes in data, reference signal oscillator that supplies a reference signal to a PLL synthesizer and a numerically controlled oscillator, output signal of PLL synthesizer and output of numerically controlled oscillator By having a mixer for synthesizing the signal and the signal, the frequency of the output signal of the numerically controlled oscillator can be changed rapidly according to the change of the frequency data set from the outside, so the frequency of the output signal can be changed quickly. Thus, it is possible to realize a frequency synthesizer capable of high-speed channel switching.

The PLL synthesizer compares the phases of the reference signal and the frequency-divided signal and outputs a phase comparison signal, and a harmonic of the phase comparison signal output from the phase comparator. The loop filter to be removed, a signal with a frequency corresponding to the output voltage of the loop filter is generated, and a frequency-divided signal obtained by dividing the frequency of the signal output from the voltage-controlled oscillator is output to the phase comparator. Since the oscillation frequency of the PLL synthesizer is controlled according to the phase difference between the reference signal and the frequency-divided signal, the output signal whose phase and frequency of the frequency-divided signal both match the reference signal is provided. A frequency synthesizer that can be generated accurately can be realized.

Furthermore, the numerically controlled oscillator uses a reference signal as a reference clock to add phase data based on frequency data, a storage unit that converts the phase data output from the counter into amplitude data, and an output from the storage unit. D / A converter for converting a digital signal to an analog signal and a filter for outputting a variable frequency signal whose frequency changes by removing the harmonics of the analog signal output from the D / A converter and changing the phase data Since the variable frequency signal that changes according to the phase data based on the externally set frequency data is output from the numerically controlled oscillator, the output that changes the frequency quickly in response to the change of the frequency data. It is possible to realize a frequency synthesizer that can reliably obtain a signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency synthesizer according to this embodiment.

FIG. 2 is a block diagram showing a configuration of a conventional frequency synthesizer.

[Explanation of symbols]

 1 PLL Synthesizer 2 Phase Comparator 3 Loop Filter 4 Voltage Controlled Oscillator 5 Frequency Divider 6 Reference Signal Oscillator 7 Numerically Controlled Oscillator 8 Counter 9 Storage Unit 10 D / A Converter 11, 13 Filter 12 Mixer

Claims (3)

[Claims] 1. A PLL synthesizer which inputs a reference signal and outputs a fixed frequency signal of a predetermined multiple of the frequency of the reference signal, and a reference signal which is used as a reference clock in response to a change in frequency data set from the outside. A numerically controlled oscillator that outputs a variable frequency signal whose frequency changes;
A frequency synthesizer comprising: a reference signal oscillator that supplies the reference signal to an L synthesizer and the numerically controlled oscillator; and a mixer that synthesizes an output signal of the PLL synthesizer and an output signal of the numerically controlled oscillator. 2. The PLL synthesizer compares a phase between the reference signal and the frequency-divided signal and outputs a phase comparison signal, and a phase comparison signal output from the phase comparator. A loop filter that removes harmonics,
A voltage-controlled oscillator that generates a signal having a frequency corresponding to the output voltage of the loop filter, and a frequency divider that outputs a frequency-divided signal obtained by dividing the frequency of the signal output from the voltage-controlled oscillator to the phase comparator. The frequency synthesizer according to claim 1, further comprising: 3. The numerically controlled oscillator includes a counter that adds phase data based on the frequency data using the reference signal as a reference clock, and a storage unit that converts the phase data output from the counter into amplitude data. A D / A converter that converts a digital signal output from the storage unit into an analog signal, and a frequency changes by removing the harmonics of the analog signal output from the D / A converter and changing the phase data. The frequency synthesizer according to claim 1, further comprising a filter that outputs a variable frequency signal.