JPH099209A - Video converter - Google Patents

Abstract

(57) [Summary] [Purpose] The original video signal is converted to a video signal of the required horizontal frequency higher than the horizontal frequency of the same signal. [Structure] The first PLL circuit 6 and the first control signal generator 7 generate a write control signal S8 having a required frequency based on the horizontal synchronizing signal S4, and the second PLL circuit 8 and the second PLL circuit 8 Similarly, the control signal generator 9 generates a read control signal S10 having a required frequency based on the horizontal synchronizing signal. As a result, a control signal suitable for each of the signals before and after the conversion is obtained, and the video conversion with the normal aspect ratio is performed. Further, by the synchronization signal generation unit 3, the switching circuit 4, and the synchronization signal determination unit 5, when the normal horizontal synchronization signal S4 does not exist, the pseudo horizontal synchronization signal S5 from the synchronization signal generation unit is the second.
To the PLL circuit, or the first PLL circuit and the second PL
It is sent to both L circuits and the asynchronous state is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video conversion device, and more particularly to a device for converting an original video signal into a video signal having a required horizontal frequency higher than the horizontal frequency of the signal.

[0002]

2. Description of the Related Art FIG. 2 shows one of conventional devices for converting an original video signal under a certain system into a video signal for another system in which the horizontal frequency of the video signal is higher than the horizontal frequency. FIG. 2 is a block diagram of a main part of the conversion device. In the figure, the original video signal is converted from an analog signal into digital video data by the A / D converter 11, and the converted video data is written in the line memory 12. The written video data is read so as to become a video signal of a required horizontal frequency. The writing and reading control is performed by the writing control signal S13 and the reading control signal S14 generated by the control signal generator 14.
These control signals S13 and S14 are PL
The L (phase synchronization) circuit 13 is generated based on the clock signal S12 oscillated so as to be locked to the input horizontal synchronization signal S11. The control signal generator 14 also generates horizontal and vertical composite sync signals S15 synchronized with the read video data based on the clock signal S12. In this way, the video data of the required horizontal frequency and the synchronization signal S
Get 15 and.

[0003]

However, in the case of FIG. 2 described above, the write control signal S13 and the read control signal S14.
There is a restriction that the clock ratio of can only be selected as an integer multiple.
Due to this limitation, for example, if an NTSC video signal is V
When converting to a video signal of GA (IBM standard for personal computers, etc.) specifications, the following problems occur. Now, the number of pixels per line of the VGA specification video signal to be converted is 80.
When 0 pixels (pixels), the horizontal frequency is 31.5 KHz, and the aspect ratio of one pixel composed of RGB is 1: 1, the square pixel frequency Fv of the same VGA is the frequency shown below. Fv = 31.5 (KHz) × 800 (pixels) = 25.175 (MHz) If this Fv is selected as the read clock, the write clock is automatically 1/2 of that, 12.5875 MH.
z.

On the other hand, one of NTSC video signals
Since the number of line pixels is 780 and the horizontal frequency is 15.734 KHz, the square pixel frequency Fn in this case is the frequency shown below. Fn = 15.734 (KHz) × 780 (pixels) = 12.2727 (MHz) To perform normal conversion, Fv / 2 (= 12.5875 MHz)
And Fn must match, but as mentioned above, they do not match. Due to this disagreement, there occurs a problem that the screen after conversion is slightly enlarged in the horizontal direction. In addition to the above, it is good to switch the whole screen with a relay, etc.
The clock must be shared with the VGA when it is combined with the A screen, but in the configuration of FIG. 2, the oscillation becomes unstable when the horizontal synchronizing signal S11 is not input, and this combination becomes difficult. There are also defects. It is an object of the present invention to provide a video conversion device that solves such a problem.

[0005]

According to the present invention, in an apparatus for converting an original video signal into a video signal having a required horizontal frequency higher than the horizontal frequency of the signal, original digital video data relating to the original video signal is written, A line memory read after the writing, a first PLL circuit for generating a first clock signal of a required frequency locked to the horizontal synchronizing signal, which is a reference signal of the horizontal synchronizing signal separated from the original video signal, and the first PLL circuit, A first control signal generator that generates a write control signal used for write control to the line memory based on the first clock signal, and feeds back the generated control signal as a comparison signal in the first PLL circuit; A second PLL circuit which uses the horizontal synchronization signal as a reference signal and generates a second clock signal of a required frequency locked to the horizontal synchronization signal. A read control signal used for read control of the line memory is generated based on the second clock signal, and the generated control signal is fed back as a comparison signal in the second PLL circuit and read out. The present invention provides a video conversion device configured with a second control signal generation unit that generates horizontal and vertical synchronization signals corresponding to video data.

[0006]

The first PLL circuit and the first control signal generator generate a write control signal of a required frequency based on the horizontal synchronizing signal, and the second PLL circuit and the second control signal generator. Similarly, a read control signal having a required frequency is generated based on the horizontal synchronizing signal. As a result, a control signal suitable for each of the signals before and after the conversion is obtained, and the video conversion with the normal aspect ratio is performed. In addition, when the normal horizontal synchronizing signal does not exist, the pseudo horizontal synchronizing signal from the synchronizing signal generating section, the switching circuit and the synchronizing signal discriminating section is sent to the second PLL circuit or the first P circuit.
It is sent to both the LL circuit and the second PLL circuit to avoid an asynchronous condition.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A video conversion device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of a video conversion apparatus according to the present invention. In the figure, S1
Is an analog original video signal, 1 is an analog original video signal S1
A / D conversion unit for converting the video data into digital video data S2,
Reference numeral 2 is a line memory in which the video data S2 from the A / D converter 1 is written under a required write control signal S8 and is read out as video data S3 of a required horizontal frequency under a required read control signal S10. S4 is a regular horizontal sync signal,
3 is a sync signal generator for generating the pseudo horizontal sync signal S5, 4
Is a switching circuit for switching between the normal horizontal synchronizing signal S4 and the pseudo horizontal synchronizing signal S5. The switching circuit 5 determines the presence or absence of the normal horizontal synchronizing signal S4. When the signal S4 is present, the signal S4 is selected. A synchronizing signal discriminating unit which outputs a switching control signal S6 for switching the switching circuit 4 so as to select the horizontal synchronizing signal S5, and 6 generates a first clock signal S7 of a required frequency locked to the horizontal synchronizing signal from the switching circuit 4. A first PLL circuit 7 for generating a write control signal S8 to be used for write control to the line memory 2 based on the first clock signal S7, and a horizontal control circuit 8 from the switching circuit 4. A second PLL circuit that generates a second clock signal S9 of a required frequency locked to the synchronization signal, and 9 is a read used for read control of the line memory 2 based on the second clock signal S9. Generation of the control signal S10, and the synchronizing signal of the horizontal and vertical corresponding to the video data S3 S
11 is a second control signal generation unit for generating 11.

Next, the operation of the present invention will be described. When the normal horizontal synchronizing signal S4 is present, the switching circuit 3 receives the switching control signal S6 from the synchronizing signal discriminating section 5 and outputs it to the signal S4 side (a
Side) and sends the same signal S4 to each PLL circuit. The regular horizontal synchronizing signal S4 is a horizontal synchronizing signal separated from the original video signal S1. The first PLL circuit 6 generates the first clock signal S7 having a required frequency locked to the horizontal synchronizing signal S4, and the required frequency means a frequency adapted to the original video signal S1. For example, as in the case of FIG. 2 described above, the video signal of the NTSC system is VGA.
Clock signal when converting to the specified video signal
The frequency of S7 is an integral multiple of the value of Fn, that is, 12.2727 MHz. The first control signal generator 7 generates a write control signal S8 having a frequency Fn, which is obtained by dividing the first clock signal S7 by an integral multiple of the inverse of the first clock signal S7. As a result, the write control signal S8 is synchronized with the horizontal synchronization signal S4 and is also adapted to the video data S2 in terms of frequency.

On the other hand, the second PLL circuit 8 outputs a horizontal synchronizing signal.
The second clock signal S9 that is an integral multiple of the reference frequency Fv (= 25.175 MHz) is generated when locking to S4 and converting to a VGA specification video signal. This clock signal S9
Based on the above, the second control signal generator 9 generates the read control signal S10 of the frequency Fv divided by the reciprocal of an integral multiple thereof.
As a result, the read control signal S10 is synchronized with the horizontal synchronizing signal S4, and the converted video data S3 (VG
It complies with A). By the above writing and reading, the original video signal of the NTSC system is correctly converted into the video signal of the VGA specification having the double horizontal frequency.

On the other hand, when the normal horizontal synchronizing signal S4 is no longer present due to no signal or the like, the synchronizing signal discriminating unit 5 cannot discriminate the synchronizing signal S4, so that the switching circuit 4 is placed on the synchronizing signal generating unit 3 side. It is switched to (b side), and the pseudo synchronization signal S5 is sent to each PLL circuit. This pseudo sync signal
S5 has the same frequency as the regular synchronization signal S4. The pseudo sync signal S5 causes the PLL circuits 6 and 8 to perform the same stable operation as when the normal sync signal S4 is input. Although the pseudo sync signal S5 is used in both the first PLL circuit 6 and the second PLL circuit 8 in FIG. 1, it may be used only in the second PLL circuit 8. The second PLL circuit 8 is used because it is more necessary to stabilize the read side than the write side. In this case, only the normal horizontal synchronizing signal S4 is input to the first PLL circuit 6 side, as in FIG. Although a comparison signal with respect to the reference signal is required due to the configuration of each PLL circuit, this comparison signal is fed back from each control signal generator 7, 9 as in FIG.

[0011]

As described above, according to the present invention, when an original video signal under a certain system using a line memory is converted into a video signal of another system in which the horizontal frequency of the signal is higher than that of the same. Since the write control signal and the read control signal for the same line memory are generated by separate and independent circuits, it is possible to obtain signals having frequencies suitable for the original video signal and the video signal to be converted. This allows
It is possible to solve the conventional problem of image conversion with an abnormal aspect ratio that the converted image becomes horizontally long. Further, a synchronizing signal generating section for generating a pseudo horizontal synchronizing signal, a switching circuit, etc. are provided, and when the regular horizontal synchronizing signal does not exist, the side is switched to the pseudo horizontal synchronizing signal side. Therefore, even when the regular horizontal synchronizing signal does not exist, the PLL is used. The oscillation operation of the circuit is prevented from becoming unstable. This stabilization of the oscillation operation facilitates the synthesis of video signals of different systems.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a video conversion apparatus according to the present invention.

FIG. 2 is a principal block diagram showing an example of a conventional video conversion device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 Line memory 3 Synchronous signal generation part 4 Switching circuit 5 Synchronous signal determination part 6 1st PLL circuit 7 1st control signal generation part 8 2nd PLL circuit 9 2nd control signal generation part S1 Analog original video signal S3 Converted video data S4 Normal horizontal sync signal S5 Pseudo sync signal S8 Write control signal S10 Read control signal

Claims (3)

[Claims] 1. An apparatus for converting an original video signal into a video signal having a required horizontal frequency higher than the horizontal frequency of the signal, and a line memory in which original digital video data relating to the original video signal is written and read after the writing. A first PLL circuit for generating a first clock signal of a required frequency locked to the horizontal synchronizing signal, which is a horizontal synchronizing signal separated from the original video signal, and the first clock circuit based on the first clock signal. A first control signal generator that generates a write control signal to be used for writing control to the line memory and feeds back the generated control signal as a comparison signal in the first PLL circuit, and the horizontal synchronization signal as a reference signal. A second PLL circuit for generating a second clock signal of a required frequency locked to the horizontal synchronizing signal, and the second clock signal A read control signal to be used for read control of the line memory is generated based on the above, and the generated control signal is fed back as a comparison signal in the second PLL circuit, and the horizontal and horizontal signals corresponding to the read video data are generated. A video conversion device comprising a second control signal generating section for generating each vertical synchronizing signal. 2. A sync signal generator for generating a pseudo horizontal sync signal having the same frequency as the horizontal sync signal of the original video signal, a pseudo horizontal sync signal from the sync signal generator, or a horizontal sync signal separated from the video signal. And the switching circuit that selects and selects the horizontal sync signal of the original video signal, and switches to the same horizontal sync signal side when the same horizontal sync signal exists, and the pseudo sync signal side when the same horizontal sync signal does not exist. A synchronizing signal discriminating section for controlling switching of the switching circuit so that the horizontal synchronizing signal selected by the switching circuit is used as a reference signal in the second PLL circuit. The video conversion device according to claim 1, characterized in that 3. A sync signal generator for generating a pseudo horizontal sync signal having the same frequency as the horizontal sync signal of the original video signal, a pseudo horizontal sync signal from the sync signal generator, or a horizontal sync signal separated from the video signal. And the switching circuit that selects and selects the horizontal sync signal of the original video signal, and switches to the same horizontal sync signal side when the same horizontal sync signal exists, and the pseudo sync signal side when the same horizontal sync signal does not exist. And a synchronization signal discriminating unit for performing switching control of the switching circuit so that any one of the horizontal synchronization signals selected by the switching circuit is used as a reference signal in the first PLL circuit and the second PLL circuit. The video conversion device according to claim 1, wherein the video conversion device is used.