JPH0998068A - Digital filter - Google Patents

Abstract

(57) Abstract: To provide a digital filter having a performance equivalent to that of a conventional memory type digital filter using a memory having a small storage capacity. SOLUTION: An n-stage shift register 1 for shifting an input n-bit parallel input signal by a clock ck,
The n-bit output of each stage of the shift register is set to n of the clock ck.
The selector 2 that outputs the selected bit by bit by the doubled second clock nck and the multiplication result obtained by multiplying the tap coefficient data corresponding to the output of each stage of the shift register are stored, and the multiplication result is read by the n-bit address from the selector. A calculation result storage memory 3, a register unit 4 for sequentially accumulating the multiplication results read from the calculation result storage memory by the second clock nck, and a full addition for fully adding and outputting the multiplication results accumulated in the register unit. Device 5 and output register 6
Consists of

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for processing an n (2 or more natural number, the same applies hereinafter) bit input signal used in digital signal processing in parallel.

[0002]

2. Description of the Related Art In recent years, in digital signal processing, it has often been attempted to realize the same effect as an analog filter by using a digital filter, and the characteristic of a typical FIR type digital filter used for such an application is as follows.
The better the number of taps, the better. In addition, it is more convenient to use the input signal and the output signal as parallel data in terms of signal processing and the configuration of peripheral circuits.

Conventionally, as this type of digital filter, there has been one as shown in FIGS. FIG. 2 shows a conventional F that inputs, processes, and outputs an input signal in bit parallel.
FIG. 3 is a configuration diagram showing the configuration of the IR digital filter, FIG. 3 is a timing diagram showing the operation relationship between the input signal and tap coefficient data, and FIG. 4 is an input signal input in bit parallel and the operation result is read out from the memory and output. It is a block diagram which shows the structure of the conventional memory type digital filter.

First, referring to FIG. 2, the conventional FIR described above is used.
The configuration of the digital filter will be described. In FIG. 2, reference numeral 7 is a parallel input signal from the output of each stage (forming a tap) by inputting n bits constituting a digital parallel input signal in parallel to each first stage by each clock ck and then shifting to one stage. Shift data (D0,
D1, ..., Dn−1, Dn) are output from the shift register (T) consisting of n stages (plural), and ck synchronizes the parallel signal input to the shift register 7 and the shift of the shift register 7. It is a clock to do.

Reference numeral 8 is tap coefficient data (C0, C1, ..., Cn-1, Cn which is preset for a specific application using this FIR type digital filter.
n) are stored in the tap coefficient register, and 9 is shift data (D0, D1, ...
.., Dn-1, Dn) are input respectively and tap coefficient data (C0, C1, ...) From the tap coefficient register 8 is input.
..., Cn-1, Cn) and the multiplication result (X0, X1, ...) output from the multiplier 9.
..., Xn-1, Xn) are added together, and 11 is an output register for temporarily storing the addition result and outputting it as a filter output (Y0) at clock ck time.

Next, the operation of the conventional FIR type digital filter will be described in detail with reference to FIGS. FIG. 3 is a timing diagram in which the horizontal axis is the time axis as shown in the clock ck, and the input or shift data is D0, D1, ..., D for each clock ck.
n-1 and Dn, and tap coefficient data (C0, C1, ...
, Cn−1, Cn) are multiplied, and the multiplication result (X0, X
, ..., Xn−1, Xn) are summed and output as the filter output Y0.

That is, the parallel input signal is the clock c
It is input to the shift register 7 in synchronization with k, and the clock c
Each k is shifted to the next stage, and the input or shift data (D0, D1, ...) At that tap is output from each stage.
..., Dn-1, Dn) are taken out. This input or shift data (D0 to Dn) is multiplied in each multiplier 9 by the tap coefficient data (C0 to Cn) from the tap coefficient register 8 corresponding to each tap, and the multiplication result (X0 to Xn) of each tap. ) Are fully added in the full adder 10, and the result of the full addition is temporarily stored in the output register 11 and output as the filter output Y0 by the clock ck.

Next, referring to FIG. 4, the structure of a conventional memory type digital filter will be described.
In FIG. 4, reference numeral 12 is a parallel input signal from n outputs of each stage (forms a tap) by inputting n bits constituting a digital parallel input signal in parallel to the first stage by a clock ck and then shifting to one stage. Shift register (n = plural) that outputs the shift data (D0 to Dn), and ck is a clock that inputs a parallel signal to the shift register 12 and synchronizes the shift of the shift register 12.

Further, at the output of each stage of the shift register 12, the operation result obtained by multiplying all shift data capable of bit combination by tap coefficient data and fully adding is stored. An operation result storage memory which is addressed by the shift data and reads out the operation result stored therein, 14
Is an output register for temporarily storing the calculation result read from the calculation result storage memory 13 and outputting it as a filter output (Y0) at the clock ck time. In such a memory type digital filter, since the arithmetic operation is performed without performing processing such as "rounding" and the result is stored, the deterioration due to the arithmetic operation can be prevented.

Next, the operation of the conventional memory type digital filter will be described with reference to FIG. First, the parallel input signal is input to the shift register 12 in synchronization with the clock ck, shifted to the next stage for each clock ck, and the shift data (D0 to Dn) at the tap is extracted from the output of each shift register stage. The shift data from the output of each shift register stage is input to the operation result storage memory 13 as its address. The operation result storage memory 13 stores the sum of the multiplication results of the input data whose designated address bit position is "1" and the corresponding tap coefficient data, and the operation result is output by the address. To be done. The output of the calculation result is temporarily stored in the output register 14 and is output as a filter output in synchronization with the clock ck.

[0011]

However, in the above-mentioned conventional FIR type digital filter, there is a problem that the circuit scale becomes large because the number of multipliers corresponding to the number of tap coefficient data is required. Further, in the memory type digital filter, since the memory address is specified by the parallel input data, there is a problem that the memory address increases and a memory having a large storage capacity is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a digital filter having a performance equivalent to that of a conventional memory type digital filter by using a memory having a small storage capacity. .

[0013]

In order to achieve the above object, a digital filter according to the present invention includes an n-stage shift register for simultaneously shifting an input n-bit parallel input signal in synchronization with a clock ck, and a shift register. A selector that selects and outputs the output consisting of n bits of each stage of the register for each bit by the second clock nck having an n-times frequency of the clock ck, and the output of each stage of the shift register is multiplied by the corresponding tap coefficient data. The multiplication result read out from the calculation result storage memory and the calculation result storage memory for storing the multiplication result and reading out the multiplication result by the address composed of n bits output from the n selectors The register unit that accumulates while shifting by the second clock nck and the operation result accumulated in the register unit. A full adder for fully adding the multiplication results from the storage memory and an output register for outputting the output of the full adder in response to a clock ck. It is what

Further, in order to achieve the above-mentioned object, the digital filter according to the present invention selects the output bits of each stage of the shift register from the least significant bit to the most significant bit in order by the selector and outputs it as the address, and the register section The multiplication result from the operation result storage memory addressed by the least significant bit is input to the least significant digit, and the multiplication result from the operation result storage memory addressed by the most significant bit is sequentially input and stored while shifting. It is characterized by.

The digital filter according to the present invention is provided with a selector for selecting and outputting the output bit of each stage of the shift register by the second clock nck which is n times the shift clock ck, and is constituted by the output bit of each selector. The operation result data read from the operation result storage memory by address is input to the register section, and while the register section shifts, the operation result data of the number corresponding to all the output bits of the shift register is accumulated in the register section, and the accumulation By outputting the filter output obtained by fully adding the data, the required memory can be obtained although the calculation result equivalent to the processing of the parallel input signal in the conventional memory type digital filter can be obtained. The storage capacity of can be reduced to 1 / n of the conventional memory,
Accordingly, it is possible to provide a digital filter suitable for LSI implementation.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings and FIG. FIG. 1 is a configuration diagram showing a configuration of a memory type digital filter according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a parallel input of n bits forming a digital parallel input signal to a first stage shift register 1 by a clock ck.
After that, the shift data for one stage is shifted to the shift data (D0 to D) of the parallel input signal from the output of each stage (forming a tap).
It is a shift register consisting of n stages (plural) outputting n).

Further, ck is a clock for synchronizing the input of the parallel input signal to the shift register 1, the shift of the shift register 1 and the output of the filter output from the output register 6, and nck has a frequency n times that of the clock ck. ,
The second clock 2 for synchronizing the selection of each bit of the shift data (D0 to Dn) by the selector 2 and the input and shift of the operation result data from the operation result storage memory 3, 2 is each shift data in each shift register stage It is a selector that selects and outputs n bits from LSB (least significant) bit to MSB (most significant) bit.

Reference numeral 3 stores the operation result obtained by multiplying all shift data capable of bit combination output from the output (each tap) of each stage of the shift register 1 by tap coefficient data. It is an operation result storage memory addressed by each bit output selected from. The addressing and reading method is as follows. First, an address is formed by a set of LSB bits of all shift data (D0 to Dn) by the second clock nck, and the first stage (LSB) of the shift register stored by the address is formed. The multiplication result with the tap coefficient data corresponding to the shift data is read, and thereafter, the address is formed toward the MSB by each bit of the shift data in sequence, and the multiplication result with the tap coefficient data corresponding to each shift register stage is obtained. The multiplication result of the tap coefficient data with respect to the outputs of all the shift register stages is output by the read out n clocks nck (1 clock ck period).

Reference numeral 4 indicates the output of each shift register stage read from the operation result storage memory 3 multiplied by the tap coefficient data corresponding to the stage, and the multiplication result is sequentially read by the second clock nck. A register unit 5 for forming a multiplication result of tap coefficient data for all stages, a full adder 5 for summing the multiplication results of each stage when the multiplication results for all stages of the shift register 1 are formed in the register unit 6, and 6 It is an output register that temporarily stores the addition result output from the full adder 5 and outputs it as a filter output at the clock ck time.

Next, the operation of the digital filter in this embodiment will be described in detail with reference to FIG. First, an n-bit parallel parallel input signal is input to the first stage of the shift register 1 in synchronization with the clock ck, and at the same time, the output (shift data) of each stage of the shift register 1 is sequentially shifted to the next stage for each clock ck. To be done. The n-bit output of each stage of the shift register 1 is input in parallel to the selector 2 of each stage. In each selector 2, the n-bit output is sequentially selected from the LSB bit by the second clock nck which is n times the clock ck and is output to the operation result storage memory 3.

The operation result storage memory 3 is addressed by an n-bit address consisting of LSB bits of the output of each stage of the shift register 1 and outputs the multiplication result corresponding to the first stage of the shift register 1. This addressing and reading is performed with the MSB of the shift data by the second clock nck.
Bits are processed in order. The output of the operation result storage memory 3 is sequentially input from the LSB bit register of the register unit 4, and is shifted to 0, 1, 2, ..., N-1 and the MSB bit register.

All n pieces of data stored in the register unit 4 are input to the full adder 5 and are fully added to the output register 6
Is output to The output register 6 outputs the addition result from the full adder 5 as a filter output in synchronization with the clock ck.

[0023]

The digital filter according to the present invention is configured as described above, and in particular, it has a selector for selecting and outputting the output bit of each stage of the shift register by the second clock nck which is n times the shift clock ck. The operation result data read from the operation result storage memory is input to the register section by the address composed of the output bits of each selector, and the operation result data corresponding to all the output bits of the shift register is shifted while shifting. The output of the filter is obtained by summing the accumulated data and adding the accumulated data, so that it is possible to obtain an operation result equivalent to the processing of the parallel input signal in the conventional memory type digital filter. The storage capacity of the memory can be reduced to 1 / n of the conventional calculation result storage memory. Accordingly, it is possible to provide a digital filter that is also suitable for LSI.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a memory type digital filter according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a conventional FIR digital filter that inputs an input signal in bit parallel, processes it, and outputs it.

FIG. 3 is a timing diagram showing an operation relationship between an input signal and tap coefficient data.

FIG. 4 is a configuration diagram showing a configuration of a conventional memory-type digital filter that inputs an input signal in bit parallel, reads an operation result from a memory, and outputs the operation result.

[Explanation of symbols]

 1, 7, 12 Shift register 2 Selector 3, 13 Operation result storage memory 4 Register section 5, 10 Full adder 6, 11, 14 Output register ck, nck Clock D0-Dn Input data C0-Cn Tap coefficient data X0-Xn Multiplication result data Y0 filter output

Claims (2)

[Claims] 1. An n-stage shift register for simultaneously shifting an input n-bit parallel input signal in synchronization with a clock ck, and an output consisting of n bits in each stage of the shift register having an n-times frequency of the clock ck. A selector which selects and outputs each bit by the second clock nck and a multiplication result obtained by multiplying the output of each stage of the shift register by the tap coefficient data corresponding to the selector, and n selectors output from the n selectors are stored. Operation result memory for reading out the multiplication result by the address constituted by the bit, and a register section for accumulating the multiplication result read out from the operation result memory while shifting by the second clock nck. And a total addition for fully adding the multiplication results from the operation result storage memory accumulated in the register unit. Vessels and makes the output of 該全 adder and an output register for outputting by the clock ck, a digital filter, characterized in that reduced the bits of address for the calculation result storage memory selectively. 2. The selector sequentially selects and outputs the output bits of each stage of the shift register from the least significant bit to the most significant bit, and outputs the address as an address, and the register unit stores the operation result memory addressed by the least significant bit. 2. The multiplication result from the memory is input to the least significant digit, the multiplication result from the operation result storage memory addressed by the most significant bit is sequentially input, and accumulated while shifting. Digital filter.