JPH10107029A - Semiconductor integrated circuit device, method of manufacturing the same, and manufacturing apparatus used therefor - Google Patents

Abstract

(57) Abstract: Unlike a method of forming a wiring pattern using a photolithography technique and a selective etching technique, a semiconductor integrated circuit device capable of finely forming a wiring pattern by a specific manufacturing process, a manufacturing method thereof, and the like Provide a manufacturing device. SOLUTION: After forming a groove 26 in an interlayer insulating film 25, a step of forming, for example, a copper layer 28 as a wiring metal layer on the interlayer insulating film 25, and after or after forming the copper layer 28 By performing a process of fluidizing the copper layer 28 therein, the copper layer 28 as a metal layer for wiring is buried in the groove 26, and a gap is formed between the buried copper layer 28 and the copper layer 28a thereon. 29, and a step of removing the copper layer 28a other than the copper layer 28 buried in the groove 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, a method of manufacturing the same, and a manufacturing apparatus used for the same. The present invention relates to a method and a manufacturing apparatus used for the method.

[0002]

2. Description of the Related Art The present inventors have studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a wiring layer in a semiconductor integrated circuit device, a wiring metal layer such as an aluminum layer is formed on an insulating film by a sputtering method, and then the wiring metal layer is formed by a photolithography process. A resist pattern having the same shape as that of the wiring pattern is formed on the resist film disposed on the substrate, and the wiring pattern is formed by a dry etching process using the resist film as a mask.

[0004] Incidentally, as a document describing a technology for forming a wiring layer in a semiconductor integrated circuit device, for example, “Ninety-Sixth Latest Semiconductor Process Technology” published on November 2, 1989 by Press Journal, p. p273
Some are described in

[0005]

However, the above-described method for manufacturing a wiring layer in a semiconductor integrated circuit device uses a photolithography technique and a selective etching technique to form a wiring pattern. Along with miniaturization, various problems such as difficulty in miniaturization of wiring patterns due to a dry etching process have occurred.

On the other hand, after a wiring metal layer such as an aluminum layer or a copper layer is buried on the insulating film in which the groove is formed, an extra wiring metal layer outside the groove is removed by CMP (Chem).
A method of forming a wiring pattern in a groove by removing the wiring pattern using ical mechanical polishing (chemical mechanical polishing) has been studied.

However, in this method, it is expected that it becomes difficult to embed a wiring metal layer in a fine groove as the wiring becomes finer. Also, in a situation where there are dense portions and isolated portions of fine wiring layers and a mixture of wide wiring layers, the occurrence of dents due to a local increase in polishing rate depending on the wiring pattern and the generation of wiring layers. The metal layer for wiring outside the groove can be precisely formed without the need to peel off the metal layer for wiring in the groove due to stress during processing, or to corrode the metal layer for wiring due to the intrusion of polishing liquid from the peeled portion. It is expected that it will also be difficult to remove the appropriate wiring metal layer).

An object of the present invention is to provide a semiconductor integrated circuit device capable of forming a wiring pattern with a fine structure by a specific manufacturing process, unlike a method of forming a wiring pattern using a photolithography technique and a selective etching technique, and a method of manufacturing the same. Another object of the present invention is to provide a manufacturing apparatus used for the apparatus.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1). In the semiconductor integrated circuit device of the present invention, at least one of the groove and the hole is formed in the insulating film, and the wiring metal layer embedded in at least one of the groove and the hole is formed of the wiring metal layer. By performing a process of fluidizing the wiring metal layer after or during film formation, the wiring metal layer is buried in at least one of the groove and the hole, and the buried wiring metal layer and the After a gap is formed between the wiring metal layer and the upper wiring metal layer, the wiring metal layer other than the embedded wiring metal layer is removed. Alternatively, at least one of the groove and the hole is formed in the insulating film on the semiconductor substrate, and the wiring metal layer has a step portion of the wiring layer formed above the groove or the hole immediately after the film is formed. Without performing fluidization after the film formation, after embedding a metal layer for wiring in at least one of the groove or the hole, for wiring other than the metal layer for wiring being embedded. It is formed with a step of removing the metal layer.

(2). The method for manufacturing a semiconductor integrated circuit device according to the present invention includes, after forming at least one of a groove and a hole in an insulating film, forming a wiring metal layer on the insulating film; By performing a process of fluidizing the wiring metal layer later or during film formation, the wiring metal layer is buried in at least one of the groove and the hole, and the buried wiring metal layer and the buried wiring metal layer are formed thereon. Forming a gap between the wiring metal layer,
Removing the wiring metal layer other than the wiring metal layer embedded in at least one of the groove and the hole. Alternatively, the step of forming at least one of a groove and a hole in the insulating film on the semiconductor substrate, and the step of forming a step portion of the wiring layer above the groove or the hole, insulates the wiring metal layer. Forming on the film,
Removing the wiring metal layer other than the wiring metal layer embedded in at least one of the groove and the hole.

(3). In the manufacturing apparatus of the present invention, the target is set on the target position adjusting mechanism, and the distance between the target and the wafer can be controlled by the target position adjusting mechanism, or the gas introduction into the sputtering chamber can be performed. Three types of gas introduction mechanisms are connected to the unit, a temperature adjustment mechanism that can adjust the temperature of the wafer is installed on a wafer stage on which a wafer can be placed, or the directivity of sputtered particles between the target and the wafer. Has a sputtering chamber for wiring metal film formation or a structure having a function of controlling the wiring metal film formation, and furthermore, a sputtering room and a load lock chamber for the wiring metal film formation, a pretreatment heating chamber,
A sputtering chamber, a plasma processing chamber, and a post-processing chamber for forming a refractory metal film are connected to a transfer chamber via a gate valve.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIG. 1 is a schematic configuration diagram showing a manufacturing apparatus according to an embodiment of the present invention. FIG.
FIG. 2 is a schematic sectional view showing a sputtering chamber for forming a wiring metal film in the manufacturing apparatus shown in FIG. 1.

As shown in FIG. 1, a manufacturing apparatus 1 according to the present embodiment can be used for forming and embedding a metal layer for wiring, and includes a load lock chamber 2, a pretreatment heating chamber 3, Sputtering chamber 4 for refractory metal film formation, plasma processing chamber 5, sputtering chamber 6 for wiring metal film formation
The post-processing chamber 7 is connected to the transfer chamber 8 via a gate valve 9.

The transfer chamber 8, which is a mechanism for loading and unloading wafers into and out of each chamber as necessary, is connected to a vacuum pump (not shown) so that the pressure can be reduced. The above-mentioned chambers are also connected to the transfer chamber 8 with the vacuum state in the transfer chamber 8 because they can be brought into a vacuum state.

In the manufacturing apparatus 1 according to the present embodiment, a load lock chamber 2 other than the sputtering chamber 6 for forming a wiring metal, a pretreatment heating chamber 3, a sputtering chamber 4 for forming a high melting point metal, a plasma processing chamber 5, The post-processing chamber 6 and the transfer chamber 8 to which these chambers are connected are the same as the manufacturing apparatus invented in the past by the present inventor, and thus detailed description thereof is omitted. The manufacturing apparatus invented by the inventor in the past is disclosed in Japanese Patent Application Laid-Open No. 8-162534 and Japanese Patent Application No.
No. 136253.

As shown in FIG. 2, the sputtering chamber 6 for forming a wiring metal in the manufacturing apparatus 1 of the present embodiment
A processing unit that can perform a sputtering process,
A wafer stage 11 on which a wafer 10 is set and a target 12 are arranged inside the sputtering chamber 6.

That is, the wafer 10 is placed on the wafer stage 11. On the wafer stage 11,
A temperature adjustment mechanism (not shown) capable of adjusting the temperature of the wafer 10 is provided. Therefore, by using the temperature control mechanism provided on the wafer stage 11 as a cooling mechanism, the temperature of the wafer 10 can be suppressed, for example, it is possible to suppress a rise in the temperature of the wafer 10 during the formation of the wiring metal layer. Can be controlled.

The wafer stage 11 is provided with a gas introduction pipe 11a connected to a temperature control mechanism. Therefore, argon plasma can be generated and sputtering can be performed while supplying argon gas for cooling the wafer 10 from the back surface of the wafer stage 11 through the gas introduction pipe 11a using the temperature control mechanism.

The target 12 is set on a target position adjusting mechanism 13, and the target position adjusting mechanism 1
3, the distance between the target 12 and the wafer 10 can be controlled.

The gas introduction unit 14 in the sputtering chamber 6 for forming a wiring metal film according to the present embodiment is connected to three types of gas introduction mechanisms 14a to 14c. Ar) gas is introduced, hydrogen (H ₂ ) gas is introduced into the gas introduction mechanism 14b, and oxygen (O ₂ ) gas is introduced into the gas introduction mechanism 14c. Can be supplied to the inside of the sputtering chamber 6.

Further, a structure 15 having a through hole in a direction substantially perpendicular to the wafer 10 can be arranged between the wafer 10 and the target 12 as required. The shape of the through-hole opened in the structure 15 has, for example, a maximum opening length of 3 cm or less and a depth / maximum opening length ratio of 0.9 or less. By providing the structure 15, the structure 15 has a function of controlling the directivity of sputtered particles between the target 12 and the wafer 10. The ratio of the connection hole to the side wall and the bottom surface is 1
The metal layer for wiring can be formed with the step coverage of 0% or more secured.

The sputtering chamber 6 for forming a wiring metal in the above-described manufacturing apparatus 1 according to the present embodiment is provided with a target 12 and a wafer 1 by a target position adjusting mechanism 13.
It is possible to control the distance to zero.

As a result, as a result of the study by the present inventor, the positional relationship where the distance between the target 12 and the wafer 10 is larger than the radius of the wafer 10 or the effective radius R _{1 of the} target 12 and the radius R of the wafer 10 Sum with ₂ (Target 12
Is greater than or equal to the value obtained by dividing the effective radius R ₁ + the radius R _{2 of the} wafer 10 by the square root of three (1.732205), and the mean free path of the sputtered particles during discharge is TW (target 1).
2 / cos [tan ^-1 ） (R ₁
+ R ₂ ) / TW｝] When the wiring metal layer is formed by using a sputtering method under the condition of not less than or equal to, the directivity of sputtered particles incident on the wafer 10 can be improved. Further, the structure 15 having a function of controlling the directivity of the sputtered particles is placed on the wafer 10 and the target 1.
2 under the condition that the distance between the structure 15 and the wafer 10 is not more than の of the mean free path during discharge and not less than twice the height of the structure 15. When the wiring metal layer is formed by using the sputtering method, the directivity of the sputtered particles incident on the wafer 10 can be improved.

According to the manufacturing apparatus 1 of the present embodiment described above, the distance between the target 12 and the wafer 10 and the mean free path at the time of discharge are determined by the sputtering method under the conditions based on the result of the study by the present inventors. Can be used to form the wiring metal layer, so that the directivity of sputtered particles incident on the wafer 10 can be improved.

The manufacturing apparatus 1 according to the above-described embodiment
According to the method, a structure 15 having a function of controlling the directivity of sputtered particles is disposed between the wafer 10 and the target 12, and the distance between the structure 15 and the wafer 10 is determined by the mean free path during discharge. Less than 1/2 of
Since the metal layer for wiring can be formed using a sputtering method under conditions based on the result of the study by the present inventors so that the height of the wiring layer 5 is twice or more the height of the wafer 5, the light is incident on the wafer 10. Directivity of sputtered particles can be improved.

(Embodiment 2) FIGS. 3 to 18 are cross-sectional views showing manufacturing steps of a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device according to the present embodiment and a method for manufacturing the same will be described with reference to FIG.

First, for example, a plurality of MOSFETs (Metal Oxide
After forming a semiconductor field effect transistor (22), an insulating film 23 is formed on the semiconductor substrate 21, and then a contact electrode 24 is formed (FIG. 3). In this case, the manufacturing process for forming the plurality of MOSFETs 22 and the like on the wafer 10 can be performed using various conventional techniques. In the description of the present embodiment, a wafer-like semiconductor substrate 21 and an insulating film 23 formed thereon are collectively referred to as a wafer 10.

That is, a field insulating film made of a silicon oxide film is formed in a device isolation region which is a selective region on the surface of the wafer 10 made of a semiconductor substrate 21 made of, for example, p-type silicon single crystal by using thermal oxidation. I do. In addition,
Although not shown, a channel stopper layer for preventing inversion is formed below the field insulating film. Next, a gate insulating film made of silicon oxide is formed in the active region surrounded by the field insulating film, and a gate electrode made of conductive polycrystalline silicon is formed on the gate insulating film. The gate electrode is formed by sequentially depositing an insulating film made of a conductive polycrystalline silicon film and a silicon oxide film on the wafer 10 and sequentially etching them. afterwards,
A sidewall insulating film made of a silicon oxide film is formed on a side wall of the gate electrode. Thereafter, an n-type impurity such as phosphorus (P) is ion-implanted into the wafer 10 to form an n-type semiconductor region serving as a source and a drain.

Thereafter, an insulating film 23 is formed on the wafer 10, a contact hole is formed in the insulating film 23, and a contact electrode 24 is formed. Specifically, for example, a silicon oxide film as an insulating film 23 is
After being formed using a VD (Chemical Vapor Deposition) method, the surface of the insulating film 23 is flattened using a chemical mechanical polishing (CMP) method. Thereafter, a contact hole is formed in the insulating film 23 using a photolithography technique and a selective etching technique, and then, for example, a tungsten (W) layer as the contact electrode 24 is buried in the contact hole using a selective CVD method or the like. I do.

Next, after a first interlayer insulating film (insulating film) 25 is formed on the wafer 10, a wiring groove 26
Is formed (FIG. 4). That is, for example, a silicon oxide film is formed on the wafer 10 as the interlayer insulating film 25 by plasma CV.
After the formation using the method D, the groove 26 is formed in a portion where the wiring layer is to be disposed by using a photolithography technique and a selective etching technique such as dry etching.

In this case, the first interlayer insulating film 25 is a wiring layer formed in the groove 26 (formed in contact with the side surface of the groove 26) and a wiring layer in which the interlayer insulating film 25 is interposed. In order to reduce the capacitance, a silicon oxide film (an insulating film having a dielectric constant of about 4.2) or an inorganic SO film formed by using a plasma CVD method, which is an insulating film having a dielectric constant of 4.5 or less, is used.
A coated insulating film (an insulating film having a dielectric constant of about 4 or less) such as a G (Spin On Glass) film is used. Therefore, use of an insulating film having a high dielectric constant such as a silicon nitride film (an insulating film having a dielectric constant of about 8) is avoided. The first wiring layer or a wiring layer embedded in a hole such as a connection hole (a metal layer for wiring called a contact electrode, a pillar-shaped pillar or a plug) is 1 A groove such as the groove 26 or a hole such as a connection hole may be formed in the interlayer insulating film 25 of the layer, and the wiring metal layer may be embedded in the groove or the hole.

Thereafter, the wafer 10 is introduced into the load lock chamber 2 of the manufacturing apparatus 1 of the first embodiment, and the vacuum is drawn. After the evacuation is completed, the wafer 10 is transferred to the pretreatment heating chamber 3. In the pretreatment heating chamber 3, the wafer 1
0 is heated to, for example, 200 ° C. to remove impurities such as moisture adsorbed on the wafer 10. FIG. 19 is a process diagram showing a manufacturing process for forming a wiring layer according to the present embodiment.

Next, the wafer 10 is transferred to the sputtering chamber 4 for forming a high melting point metal, and a layer containing a high melting point metal such as titanium nitride (Ti) is formed on the wafer 10.
N) The layer 27 is formed (FIG. 5). The layer containing the high melting point metal is a layer below the wiring layer described later, and is formed to improve the adhesion between the wiring layer and the interlayer insulating film 25. In some cases, a contained layer may be provided as necessary or may not be necessary.
In the case of the present embodiment, an aluminum (Al) layer or an alloy layer of the material can be used as the metal layer for wiring, for example, a copper (Cu) layer, a silver (Ag) layer, or a gold (A) layer.
When a layer u) or an alloy layer of those materials is used, as a layer containing a high melting point metal as a lower layer, a material such as titanium (Ti), tungsten (W), molybdenum (Mo) or the like is used. A metal layer made of a compound (such as TiSi) or an alloy layer of the material (such as TiW) can be used.

Next, the wafer 10 is transferred to the plasma processing chamber 5. In the plasma processing chamber 5, the surface of the wafer 10 is irradiated with, for example, argon (Ar) plasma. The purpose of this is to sputter the surface of the wafer 10 with argon ions to remove the titanium nitride layer 27 in the flat portion of the interlayer insulating film 25 and irradiate the inside of the groove 26 with argon ions to form a wiring layer as described later. The adhesion to the copper layer can be improved (FIG. 6).

The removal of the titanium nitride layer 27 in the flat portion of the interlayer insulating layer 25 may be performed by another manufacturing apparatus such as a CMP apparatus. Further, depending on the mode of the wiring layer formed in the groove 26, the above-mentioned titanium nitride layer 27 is formed.
And the plasma processing need not be performed.

Thereafter, after the plasma processing, the wafer 10 is transferred to the sputtering chamber 6 for forming a wiring metal film. In the sputtering chamber 6 for forming the wiring metal film, the wafer 10
For example, a copper layer (metal layer for wiring) 28 is formed as a first wiring layer (FIG. 7). In this case, as shown in FIG. 7, the directivity of the sputtered particles is made unique during the formation of the copper layer 28, and the thick copper layer 28 is formed on the flat portion of the interlayer insulating film 25, The step coverage in the trench 26 is unique, and a small amount of copper layer 28
Are embedded, and a step in the copper layer 28 is formed thereon. The conditions in the sputtering method when forming the copper layer 28 are as follows.

That is, the sputtering chamber 6 for forming a wiring metal in the manufacturing apparatus 1 of the first embodiment described above.
The distance between the target 12 and the wafer 10 can be controlled by the target position adjusting mechanism 13.

As a result, the distance between the target 12 and the wafer 10 is set to be equal to or greater than the radius of the wafer 10 (approximate setting conditions) or the definite value of the positional relation, and the effective Radius R ₁ and wafer 10
The sum of the radius R ₂ of the (effective radius R ₁ of the target 12
+ The radius R _{2 of the} wafer 10) to the square root of 3 (1.7320)
5) and the mean free path of the sputtered particles during discharge is TW (distance between target 12 and wafer 10) / cos [tan ^-1 ｛(R ₁ + R ₂ ) / T
When the copper layer 28 is formed by using the sputtering method under the condition that W｝] or more, the directivity of the sputtered particles incident on the wafer 10 can be improved. Also,
A structure 15 having a function of controlling the directivity of sputtered particles is disposed between the wafer 10 and the target 12,
The sputtering method is used under the condition that the distance between the structure 15 and the wafer 10 is equal to or less than 1/2 of the mean free path during discharge and equal to or more than twice the height of the structure 15. When the layer 28 is formed, the directivity of sputtered particles incident on the wafer 10 can be improved.

Accordingly, the conditions in the sputtering method for forming the copper layer 28 are specifically as follows.
The distance between the wafer 2 and the wafer 10 is, for example, 200 mm,
Is 200 mm, for example, and the argon gas pressure used for sputtering is 0.01 Pa, for example.

The set temperature of the wafer stage 11 is, for example, 10 ° C., thereby cooling the wafer 10 during film formation. The set temperature of the wafer stage 11 is 10
The temperature may be 0 ° C. or lower, and the copper layer 28 may be formed without heating or the wafer 10 may be cooled, or a high-temperature film forming process may be performed after the copper film 28 is formed.

Next, the wafer 10 is loaded into the post-processing chamber 7, and
The wafer 10 is heat-treated under reduced pressure. Heat treatment conditions are pressure
0.002 Pa, the temperature is 300 ° C., and the time is 3 minutes. By this heat treatment, the copper layer 28 is fluidized,
While the trench 26 is filled with the copper layer 28, the copper layer 28 a in the flat portion of the interlayer insulating film 25 and the copper layer 28 inside the trench 26 can be separated at the upper part of the sidewall of the trench 26, and the copper layer 28 inside the trench 26 and its A void (void) 29 can be formed between the upper copper layer 28a (FIG. 8). In the following description, the copper layer 28 after fluidization is sectioned, the copper layer inside the groove 26 is defined as 28, and the copper layer in the flat portion of the interlayer insulating film 25 is defined as 28a.

In this case, the copper layer 28 as a wiring metal layer
Of fluidizing the copper layer 28 as the wiring metal layer by heat treatment under reduced pressure after or during the formation of the copper layer 28 as the wiring metal layer, or After forming the copper layer 28 as a layer, a process of fluidizing the copper layer 28 as a wiring metal layer by heat treatment under a high pressure of 100 atm or more, or forming a copper layer 28 as a wiring metal layer is performed. After performing in an atmosphere containing oxygen, a mode in which a process of fluidizing the copper layer 28 as a metal layer for wiring by heat treatment in an atmosphere containing hydrogen may be performed.

Next, after taking out the wafer 10 from the manufacturing apparatus 1, an object 30 made of an adhesive substance such as a resin tape is attached to the surface of the copper layer 28a on the wafer 10 (FIG. 9). Thereafter, the object 30 is operated to operate the object 3
By peeling the copper layer 28a stuck on the interlayer insulating film 25 from the interlayer insulating film 25 (FIG. 10), the copper layer 28a on the flat portion of the interlayer insulating film 25 is selectively removed, and the first layer in the groove 26 is formed. A copper layer 28 is formed as a wiring layer (FIG. 11).

The step of leaving the copper layer 28 as the first wiring layer, that is, the copper layer 28 buried in the groove 26, and removing the unnecessary copper layer 28a above the gap 29 thereon is described above. In addition to the step, a step of removing the copper layer 28a to be removed by using a chemical mechanical polishing method or a mechanical polishing method, or forming a sacrificial film on the surface of the copper layer 28a to be removed, and then using a dry etching method or a wet etching method. To remove the copper layer 28a as a wiring layer to be removed and its sacrificial film, or
9, a resist film is formed on the surface of the copper layer 28a to be removed, and the resist film is used as a mask by dry etching or wet etching.
, Or after substantially removing the removed copper layer 28a using any of the various removal steps described above for the removed copper layer 28a, further removing the copper using chemical-mechanical polishing or mechanical polishing. A step of completely removing layer 28a can be used.

In another embodiment of the present invention, the wiring above the groove 26 or the hole of the interlayer insulating film 25 can be formed without performing the above-described process of fluidizing the copper layer 28 as the wiring metal layer. By forming a copper layer 28 as a wiring metal layer on the interlayer insulating film 25 in such a manner that a step portion of the layer is formed, the copper layer 28 in the flat portion of the interlayer insulating film 25 is formed.
a and the copper layer 28 inside the groove 26 can be separated, so that a copper layer as a wiring metal layer other than the copper layer 28 as a wiring metal layer embedded in at least one of the groove 26 and the hole is formed. 28a can be removed using the various techniques described above.

Next, a second interlayer insulating film (insulating film) 31 is formed on the wafer 10, and a groove 32 for forming a second wiring layer is formed in a selective region thereof. The manufacturing process in this case includes the above-described first interlayer insulating film 25 and a groove 26 for forming a first wiring layer in a selective region thereof.
Can be performed using the same step as the step of forming Then, using a selective etching method, a specific groove 3 is formed.
A connection hole (a hole referred to as a through hole or a contact hole) 33 is formed in 2 (FIG. 12).

Thereafter, a wiring metal layer 34 made of, for example, tungsten or the like is formed in the connection hole 33 by using a selective CVD method or the like (FIG. 13). In this case, the wiring metal layer 3
4 is formed so as to protrude above the connection hole 33.

Next, a copper layer (metal layer for wiring) 35 as a second wiring layer embedded in the groove 32 is formed (FIG. 14). In this case, the manufacturing process of the copper layer 35 can be performed using the same process as the process of forming the copper layer 28 as the first wiring layer described above.

Next, a third interlayer insulating film (insulating film) 36 is formed on the wafer 10, and a groove 37 for forming a third wiring layer is formed in a selective region thereof. afterwards,
The connection hole 3 is formed in a specific groove 37 by using a selective etching method.
8 (FIG. 15). The manufacturing process in this case includes a process of forming the above-described second interlayer insulating film 31, a groove 32 for forming a second wiring layer in a selective region thereof, and a connection hole 33 in the groove 32. It can be performed using similar steps.

Thereafter, using the interlayer insulating film 36 as a mask,
An operation of removing the copper layer 35 below the connection hole 38 by using a selective etching method is performed (FIG. 16). Next, a wiring metal layer 39 made of, for example, tungsten or the like is formed in the connection hole 38 by using a selective CVD method or the like (FIG. 17). In this case, the wiring metal layer 39 is formed so as to protrude above the connection hole 38 and is formed so as to be in contact with the lower wiring metal layer 34 and be integrated therewith. By forming the wiring metal layer 39 and the wiring metal layer 34 thereunder in this state, the contact resistance can be reduced.

Next, for example, a copper layer (metal layer for wiring) 40 is formed as a third wiring layer embedded in the groove 37 (FIG. 18). The manufacturing process of the copper layer 40 in this case can be performed using the same process as the process of forming the copper layer 28 as the first wiring layer described above.

Thereafter, the above-described manufacturing process is repeated to form a multilayer wiring layer as required, and then a passivation film (not shown) is formed to manufacture the semiconductor integrated circuit device of the present embodiment. End the process.

In the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the interlayer insulating film 25 having the trench 26 is formed.
For example, after forming a copper layer 28 as a wiring metal layer thereon, a process of fluidizing the copper layer 28 after or during the formation of the copper layer 28 is performed, so that the wiring metal layer is formed in the groove 26. And a gap 29 between the buried copper layer 28 and the copper layer 28a thereon.
And a step of removing the copper layer 28a other than the copper layer 28 as the wiring metal layer embedded in the groove 26.

In the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, the step portion of the wiring layer is formed above the groove 26 or the hole of the interlayer insulating film 25. Is formed on the interlayer insulating film 25 so that the copper layer 28 on the flat portion of the interlayer insulating film 25 is formed.
a, a step of dividing the copper layer 28 inside the groove 26, and a step of removing the copper layer 28a other than the copper layer 28 as the wiring metal layer embedded in the groove 26.

As a result, according to the above-described method for manufacturing a semiconductor integrated circuit device of the present embodiment, a conventional wiring layer pattern is formed using a photolithography technique and a selective etching technique. By forming, for example, the copper layer 28 as a wiring layer without using a manufacturing process, even if the wiring layer width and the distance between adjacent wiring layers are extremely small, high-precision dimensions can be obtained by fine processing. The wiring layer can be manufactured with high accuracy.
Further, even in a situation where there are dense portions and isolated portions of the fine wiring layer and a mixture of wide wiring layers, the wiring metal layer outside the groove 26 (unnecessary wiring metal layer) can be precisely formed. ) Allows the wiring layer to be manufactured with high dimensional accuracy by fine processing.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the first interlayer insulating film 25 is formed.
As a material of an interlayer insulating film such as a silicon oxide film (an insulating film having a dielectric constant of about 4.2) or an inorganic S film formed by using a plasma CVD method, which is an insulating film having a dielectric constant of 4.5 or less.
By using a coating insulating film such as an OG film (an insulating film having a dielectric constant of about 4 or less) or the like, it is embedded in the groove 26 formed in the interlayer insulating film 25 (of the groove 26). The capacitance of the wiring layer such as the copper layer 28 (which is in contact with the side surface) can be reduced, and the copper disposed on the wiring layer such as the copper layer 28 with the second interlayer insulating film 31 interposed therebetween. Since the capacitance between the wiring layers such as the layer 35 can also be reduced, a high-performance and highly reliable wiring layer structure can be obtained.

Further, the method of manufacturing a semiconductor integrated circuit device of the present embodiment described above
When the wiring metal layer 34 is formed in the connection hole 33 formed in the wiring hole 2, the wiring metal layer 34 is buried in the connection hole 33 so that the surface of the wiring metal layer 34 protrudes from the connection hole 33. 34 are formed. A connection hole 38 is formed in the groove 37 in the upper interlayer insulating film 36 on the connection hole 33.
Is formed so that the back surface of the wiring metal layer 39 buried in the connection hole 38 is directly connected to the surface of the wiring metal layer 34 therebelow.

As a result, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment described above, the wiring metal layer 34 buried in the connection hole 33 and the wiring buried in the connection hole 38 above the wiring metal layer 34. Since the contact resistance can be reduced by being formed integrally with the metal layer 39 for use, a high-performance and highly reliable wiring layer structure can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, as a manufacturing process of the wiring metal layer buried in the groove or the hole of the above-described embodiment, a step of burying the wiring metal layer in the groove or the hole and removing the unnecessary wiring metal layer thereafter. The term “step” refers to a mode in which the steps are repeated a plurality of times to form a wiring layer having a complicated structure corresponding to a design specification. The present invention provides a manufacturing step in which the steps are performed at least once. Can be applied to a manufacturing process of forming a wiring layer corresponding to a design specification.

Further, according to the present invention, a semiconductor substrate forming a semiconductor element can be changed to an SOI (Silicon on Insulator) substrate, and a semiconductor in which various semiconductor elements such as a MOSFET, a CMOSFET and a bipolar transistor are combined is used. An integrated circuit device and a method for manufacturing the same can be provided.

Further, the present invention relates to a MOSFET, a CMO
Logic system or DR with SFET etc. as components
AM (Dynamic Random Access Memory), SRAM (St
The present invention can be applied to various semiconductor integrated circuit devices having a memory system such as an aticRandom Access Memory) and a method of manufacturing the same.

[0066]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a wiring layer pattern is formed without using a conventional wiring layer pattern manufacturing process of forming a wiring layer pattern using photolithography technology and selective etching technology. For example, by forming a copper layer (metal layer for wiring), even if the wiring layer width and the distance between adjacent wiring layers are extremely small, the wiring layer can be formed with high precision dimensional accuracy by fine processing. Can be manufactured. Further, even in a situation where there are dense portions and isolated portions of fine wiring layers and a mixture of wide wiring layers, a wiring metal layer (such as an unnecessary wiring Metal layer)
, It is possible to manufacture a wiring layer with high dimensional accuracy by fine processing.

(2). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the material of the interlayer insulating film (insulating film) such as the first interlayer insulating film (insulating film) is an insulating film having a dielectric constant of 4.5 or less. A silicon oxide film (an insulating film having a dielectric constant of about 4.2) or an applied insulating film such as an inorganic SOG film (an insulating film having a dielectric constant of about 4 or less) formed by a plasma CVD method is used. By doing so, it is possible to reduce the capacity of a wiring layer such as a copper layer embedded in a groove formed in the interlayer insulating film (contacting the side surface of the groove), and to reduce the copper layer and the like. 2 on the wiring layer of
Since the capacitance between the wiring layer such as a copper layer and the like, which is disposed with the interlayer insulating film of the first layer interposed therebetween, can be reduced, a high-performance and highly reliable wiring layer structure can be obtained.

(3). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the wiring metal layer buried in the connection hole and the wiring metal layer buried in the connection hole above the wiring hole are formed so as to be integrated. By doing so, the contact resistance can be reduced, and a high-performance and highly reliable wiring layer structure can be obtained.

(4). According to the semiconductor integrated circuit device of the present invention, since the semiconductor device is manufactured by the above-described method of manufacturing a semiconductor integrated circuit device of the present invention, the wiring layer width and the distance between adjacent wiring layers are extremely small by fine processing. It can be structured. In addition, a high-performance and highly-reliable wiring layer structure can be obtained by reducing the capacitance between the wiring layers and the adjacent wiring layers and reducing the contact resistance between the wiring metal layers embedded in the connection holes. Can be.

(5). According to the manufacturing apparatus of the present invention, the distance between the target and the wafer and the mean free path at the time of discharge are formed by sputtering using the sputtering method under conditions based on the results of the study by the present inventors. Being able to form a film can improve the directivity of sputtered particles incident on the wafer.

Further, according to the manufacturing apparatus of the present invention, a structure having a function of controlling the directivity of sputtered particles is arranged between the wafer and the target, and the distance between the structure and the wafer is reduced by the discharge. The metal layer for wiring is formed using a sputtering method under a condition based on the result of the study of the present inventor so that the mean free path at the time is not more than 1/2 and not less than twice the height of the structure. Being able to form a film can improve the directivity of sputtered particles incident on the wafer.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a manufacturing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a sputtering chamber for forming a wiring metal film in the manufacturing apparatus shown in FIG.

FIG. 3 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 15 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a step of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 19 is a process diagram showing a manufacturing process of forming a wiring layer in a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Manufacturing apparatus 2 Load lock room 3 Pre-processing heating room 4 Sputtering room for refractory metal film formation 5 Plasma processing room 6 Sputtering room for wiring metal film formation 7 Post-processing room 8 Transfer room 9 Gate valve 10 Wafer 11 Wafer stage 11a gas introduction pipe 12 target 13 target position adjustment mechanism 14 gas introduction section 14a gas introduction mechanism 14b gas introduction mechanism 14c gas introduction mechanism 15 structure 21 semiconductor substrate 22 MOSFET 23 insulation film 24 contact electrode 25 interlayer insulation film (insulation film) 26 Groove 27 Titanium nitride layer 28 Copper layer (metal layer for wiring) 28 a Copper layer (metal layer for wiring to be removed) 29 Void 30 Object 31 Interlayer insulating film (insulating film) 32 Groove 33 Connection hole 34 Metal layer for wiring 35 Copper layer ( (Metal layer for wiring) 36 interlayer insulating film (insulating film) 37 groove 38 connection 39 wiring metal layer 40 of copper layer (wiring metal layer)

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/768 H01L 21/90 D (72) Inventor Hiji Yamaguchi 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Nobuo Owada 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (9)

[Claims] At least one of a groove and a hole is formed in an insulating film on a semiconductor substrate, and a wiring metal layer embedded in at least one of the groove and the hole is used for forming the wiring metal layer. By performing a process of fluidizing the wiring metal layer after or during the formation of the metal layer, the wiring metal layer is embedded in at least one of the groove and the hole, and the embedded wiring is embedded therein. Forming a gap between the wiring metal layer and the wiring metal layer thereover, and then removing the wiring metal layer other than the embedded wiring metal layer. At least one of a groove or a hole is formed in the insulating film, and the wiring metal layer is
Immediately after the film formation, a step portion of the wiring layer is formed above the groove or the hole, and the wiring is formed in at least one of the groove or the hole without performing fluidization after the film formation. A semiconductor integrated circuit device formed by burying a metal layer for wiring and then removing a wiring metal layer other than the buried metal layer for wiring. 2. A step of forming at least one of a groove and a hole in an insulating film on a semiconductor substrate, a step of forming a wiring metal layer on the insulating film, and forming the wiring metal layer. By performing a process of fluidizing the wiring metal layer later or during the film formation, the wiring metal layer is buried in at least one of the groove or the hole and the buried wiring metal layer and the Forming a gap between the upper wiring metal layer and a step of removing a wiring metal layer other than the wiring metal layer embedded in at least one of the groove and the hole. A step of forming at least one of a groove and a hole in an insulating film on a semiconductor substrate, and a step of forming a step portion of a wiring layer above the groove or the hole; Forming a layer on the insulating film; and removing a wiring metal layer other than the wiring metal layer embedded in at least one of the groove or the hole. A method for manufacturing a semiconductor integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of forming a wiring metal layer on the insulating film includes the step of forming a distance TW between a target and a wafer.
Radius R of but effective radius R ₁ + wafer sum (target radius R ₂ of the effective radii R ₁ and wafer target
₂ ) is equal to or greater than a value obtained by dividing the square root of 3 (1.732205), and the mean free path of the sputtered particles during discharge is TW.
/ Cos [tan ^-1 {(R ₁ + R ₂ ) / TW}] or more, using a sputtering method to form a metal layer for wiring using a sputtering method. A structure having a function of controlling the directivity of sputtered particles is provided therebetween, and the distance between the structure and the wafer is equal to or less than の of the mean free path during discharge, and A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a wiring metal layer by using a sputtering method under a condition that the height is twice or more. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of fluidizing the wiring metal layer includes reducing the pressure after or during the formation of the wiring metal layer. A process of fluidizing the wiring metal layer by a lower heat treatment, or a process of fluidizing the wiring metal layer by a heat treatment under a high pressure of 100 atm or more after the formation of the wiring metal layer, or A method for manufacturing a semiconductor integrated circuit device, comprising: forming a wiring metal layer in an atmosphere containing oxygen, and then performing a process of fluidizing the wiring metal layer by a heat treatment in an atmosphere containing hydrogen. Method. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the wiring metal layer is an aluminum layer, a copper layer, a silver layer, a gold layer, or a layer thereof. A semiconductor integrated circuit characterized by using an alloy layer of a material, or using a copper layer, a silver layer or a gold layer, or an alloy layer of such a material and a refractory metal layer or an alloy layer of the material as a lower layer thereof Device manufacturing method. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the wiring metal layer is not embedded in at least one of the groove and the hole. Removing the wiring metal layer as a step of attaching an object made of an adhesive substance to the surface of the wiring metal layer to be removed, and then manipulating the object to remove the wiring metal layer attached thereto; or A step of removing the wiring metal layer to be removed using a chemical mechanical polishing method or a mechanical polishing method, or forming a sacrificial film on the surface of the wiring metal layer to be removed, and then using a dry etching method or a wet etching method. Removing the wiring metal layer and the sacrificial film to be removed, or forming a resist film on the surface of the wiring metal layer to be removed on the groove of the insulating film. A step of removing the wiring metal layer to be removed using a dry etching method or a wet etching method using the resist film as a mask, or, after substantially removing the wiring metal layer to be removed using any of the above steps, A method for manufacturing a semiconductor integrated circuit device, further comprising a step of completely removing the wiring metal layer to be removed by using a chemical mechanical polishing method or a mechanical polishing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein a metal layer for wiring is buried in a connection hole formed in a groove in said insulating film. Forming the wiring metal layer so that the surface of the wiring metal layer embedded in the connection hole protrudes from the connection hole, or formed in a groove in the insulating film. Burying a wiring metal layer in the connection hole, forming a connection hole in a groove in an upper insulating film on the connection hole, and forming a back surface of the wiring metal layer embedded in the connection hole. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a wiring metal layer so as to be directly connected to a surface of a wiring metal layer embedded in a lower connection hole. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein said insulating film is one kind of insulating film or a plurality of kinds of insulating films. Even with a stacked structure of
4.5 or less, or an insulating film of the same type as an insulating film below the wiring metal layer and an insulating film on a side surface of the wiring metal layer. Manufacturing method. 9. The manufacturing apparatus used in the method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the target is set on a target position adjusting mechanism, and the target is set by the target position adjusting mechanism. A sputtering chamber for forming a wiring metal film capable of controlling a distance between the target and the wafer; and a gas introduction unit in the sputtering chamber,
A type of gas introduction mechanism is connected, and has a sputtering chamber for forming a wiring metal film that can supply each gas or a mixed gas thereof as necessary to the inside of the sputtering chamber. The mountable wafer stage has a sputtering chamber for wiring metal film formation in which a temperature control mechanism capable of controlling the temperature of the wafer is installed. Also, the directivity of sputtered particles is controlled between the target and the wafer. It has a sputtering chamber for wiring metal film formation in which a structure having a function is installed, or a sputtering chamber and a load lock chamber for the wiring metal film formation, a pretreatment heating chamber, and a high melting point metal film formation chamber. The sputtering chamber, the plasma processing chamber and the post-processing chamber are connected to the transfer chamber via a gate valve. Apparatus.