JPH10107034A - Word line manufacturing method - Google Patents

Word line manufacturing method

Info

Publication number
JPH10107034A
JPH10107034A JP9011965A JP1196597A JPH10107034A JP H10107034 A JPH10107034 A JP H10107034A JP 9011965 A JP9011965 A JP 9011965A JP 1196597 A JP1196597 A JP 1196597A JP H10107034 A JPH10107034 A JP H10107034A
Authority
JP
Japan
Prior art keywords
layer
silicon
metal silicide
word line
silicide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9011965A
Other languages
Japanese (ja)
Inventor
Uu Der-Yuan
ウー デル−ユアン
Chun Shen Ii
チュン シェン イー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW085111565A external-priority patent/TW316326B/en
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of JPH10107034A publication Critical patent/JPH10107034A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】 【課題】 ワードラインのパターン化を容易に行えるワ
ードラインの製造方法を提供する。 【解決手段】 基板上に多数の列のゲートを形成する。
金属珪化物層をゲートの上方に形成した後、シリコン富
有層を形成する。シリコン富有層は高シリコン濃度を持
つ他の金属珪化物層かまたは純粋なシリコン層である。 (57) [Summary] [PROBLEMS] To provide a word line manufacturing method capable of easily patterning word lines. A plurality of rows of gates are formed on a substrate.
After forming a metal silicide layer above the gate, a silicon rich layer is formed. The silicon-rich layer is another metal silicide layer with a high silicon concentration or a pure silicon layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は一般に半導体集積回
路（ＩＣ）の製造に関し、特に、ダイナミックランダム
アクセスメモリ回路中のワードライン（単語線）の製造
に関する。The present invention relates generally to the manufacture of semiconductor integrated circuits (ICs), and more particularly, to the manufacture of word lines in dynamic random access memory circuits.

【０００２】[0002]

【従来の技術】ダイナミックランダムアクセスメモリ
（ＤＲＡＭ）のキャパシタ（コンデンサ）の表面積を最
大にするために、キャパシタは一般にワードラインの上
方に形成される。しかし、ワードラインと蓄電セルは両
方導電性層であるので、それらの間には絶縁層が必要で
ある。酸化珪素（珪素酸化物）および窒化珪素（珪素窒
化物）は両方とも絶縁層として広く使用されている。し
かし、窒化珪素を用いることは関連するトランジスタの
ゲートに潜在的な応力効果を生じさせると共にゲートの
パターン化の際の困難さが生ずる。したがって、酸化珪
素がこの用途に対して最もよく用いられる材料である。
蒸着が酸化珪素（頂部酸化物）層を形成するためによく
用いられ、特に、７００℃における低圧化学蒸着（ＬＰ
ＣＶＤ）が効率がよいので好ましい。2. Description of the Related Art In order to maximize the surface area of a capacitor (capacitor) of a dynamic random access memory (DRAM), the capacitor is generally formed above a word line. However, since both the word line and the storage cell are conductive layers, an insulating layer is required between them. Both silicon oxide (silicon oxide) and silicon nitride (silicon nitride) are widely used as insulating layers. However, the use of silicon nitride creates potential stress effects on the gate of the associated transistor and creates difficulties in patterning the gate. Therefore, silicon oxide is the most commonly used material for this application.
Deposition is often used to form silicon oxide (top oxide) layers, especially at 700 ° C. low pressure chemical vapor deposition (LP
CVD) is preferred because of its high efficiency.

【０００３】下記はＤＲＡＭ製造の際に用いられるワー
ドラインを形成するためのプロセスを述べるものであ
る。The following describes a process for forming word lines used in DRAM manufacturing.

【０００４】図３を参照すると、ゲート酸化物層１４と
ワードライン１６を持った基板１０が設けられる。次
に、耐火性タングステン珪化物（ＷＳｉ2 ）層１８がポ
リシリコン材料であるワードライン１６上に形成され
る。この方法は相互連結抵抗を減少させる。問題の珪化
物は下記の３つの基本的な技術によって形成され、いず
れの技術も珪化物１８を形成する熱工程がその後行われ
る。 （１）ポリシリコン層１６上への純粋なタングステンの
蒸着、（２）２つの供給源（共通蒸発源）からシリコン
およびタングステンの同時蒸発、（３）複合ターゲット
からの、または共通スパッタリングまたは積層化による
タングステン珪化物のスパッタ蒸着。Referring to FIG. 3, a substrate 10 having a gate oxide layer 14 and word lines 16 is provided. Next, a refractory tungsten silicide (WSi 2 ) layer 18 is formed over the word line 16 which is a polysilicon material. This method reduces the interconnect resistance. The silicide in question is formed by three basic techniques, each of which is followed by a thermal step to form silicide 18. (2) co-evaporation of silicon and tungsten from two sources (common evaporation source); (3) co-sputtering or lamination from a composite target; Vapor deposition of tungsten silicide.

【０００５】[0005]

【発明が解決しようとする課題】次に、図４を参照する
と、絶縁層２０が、タングステン珪化物層１８をその後
に蒸着される層から分離するために、タングステン珪化
物層１８の表面上に形成されねばならない。蒸着した酸
化珪素および窒化珪素がこの用途に用いられるが、７０
０℃におけるＬＰＣＶＤによって形成された酸化珪素層
が一般に一層良好な材料特性を与えるので、好ましい。
形成された酸化物層２０は安定でなければならないし、
適切な電気物理特性を呈しなければならない。しかし、
実際には、タングステン珪化物層１８の表面は、例えば
７００℃のような高温で酸素が存在すると、容易にタン
グステン酸化物に変換する。タングステン酸化物は初期
には揮発性であるが、頂部酸化物層２０が蒸着工程の結
果によって蒸着した後ではタングステン酸化物がタング
ステン珪化物層１８の上部表面に残ることは避けられな
い。したがって、望ましくないタングステン酸化物（Ｗ
Ｏ3 ）の層２２が酸化珪素層２０の下に形成されるのは
避けられない。言い換えると、タングステン酸化物層２
２がタングステン珪化物層１８と酸化珪素層２０との間
に形成される。さらに、タングステン酸化物層２２は滑
らかでなく、多数の凸凹の面を持つので、酸化珪素の表
面も同様に荒くなる。観察される他の結果は、ポリシリ
コン層１６が厚い一方、対照的に、タングステン珪化物
層１８が薄いことである。前述の望ましくない結果によ
ってワードライン線１６のパターン化を困難にする。Referring now to FIG. 4, an insulating layer 20 is formed over the surface of tungsten silicide layer 18 to separate tungsten silicide layer 18 from subsequently deposited layers. Must be formed. Evaporated silicon oxide and silicon nitride are used for this application,
Silicon oxide layers formed by LPCVD at 0 ° C. are generally preferred because they provide better material properties.
The formed oxide layer 20 must be stable,
Must exhibit appropriate electrophysical properties. But,
Actually, the surface of the tungsten silicide layer 18 is easily converted to tungsten oxide when oxygen is present at a high temperature such as 700 ° C. Although the tungsten oxide is initially volatile, it is inevitable that the tungsten oxide will remain on the upper surface of the tungsten silicide layer 18 after the top oxide layer 20 has been deposited as a result of the deposition process. Therefore, the undesirable tungsten oxide (W
It is inevitable that the layer 22 of O 3 ) is formed under the silicon oxide layer 20. In other words, the tungsten oxide layer 2
2 is formed between the tungsten silicide layer 18 and the silicon oxide layer 20. Further, since the tungsten oxide layer 22 is not smooth and has many uneven surfaces, the surface of the silicon oxide is similarly roughened. Another observed result is that the polysilicon layer 16 is thicker, while the tungsten silicide layer 18 is thinner. The aforementioned undesirable consequences make patterning of the word line 16 difficult.

【０００６】したがって、本発明の目的は、前述の問題
を克服したワードラインの製造方法を提供することにあ
る。Accordingly, it is an object of the present invention to provide a word line manufacturing method which overcomes the above-mentioned problems.

【０００７】[0007]

【課題を解決するための手段】本発明は、前述の目的
を、基板上に複数の列のゲートを形成し、ゲートの各列
に第１の金属珪化物層を形成し、珪素富有である他の金
属珪化物層を形成するか、またはそれに代えて前に形成
した金属珪化物層上に珪素層を形成することから成るワ
ードラインの新規な製造方法によって達成する。SUMMARY OF THE INVENTION The present invention addresses the foregoing objects by providing a plurality of rows of gates on a substrate and forming a first metal silicide layer in each row of the gates, which is silicon rich. This is achieved by a novel method of manufacturing word lines comprising forming another metal silicide layer or, alternatively, forming a silicon layer on a previously formed metal silicide layer.

【０００８】[0008]

【発明の実施の形態】以下に、添付図面を参照して本発
明の実施例を詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

【０００９】最初に図１を参照すると、ゲート酸化物層
２４とポリシリコンワードライン２６を持った基板２０
が用意される。次に、耐火性金属珪化物層２８、好まし
くは、タングステン珪化物がワードライン上に形成され
る。この点までの製造工程は当業者にとって公知である
ので、詳細には説明しない。次に、シリコン富有金属珪
化物、または純粋シリコン層３０が金属珪化物層２８の
上部表面に形成される。かくして、層３０は層２８より
高濃度のシリコンを持つ。このシリコン富有金属珪化物
層３０は、好ましくは、反応体シリコン塩化物（ＳｉＣ
ｌ2 Ｈ2 ）およびタングステン弗化物（ＷＦ6 ）で化学
蒸着されたタングステン珪化物層である。タングステン
弗化物は腐食性ガスであり、比較的高い密度を持ち、室
温でかなり高い蒸気圧を持つ。市販のコールドウオール
（ｃｏｌｄ−ｗａｌｌ）システムがタングステン珪化物
蒸着に用いられて成功を収めている。シリコン塩化物と
タングステン弗化物は、例えば、１：１の比でよい。Referring first to FIG. 1, a substrate 20 having a gate oxide layer 24 and polysilicon word lines 26 is shown.
Is prepared. Next, a refractory metal silicide layer 28, preferably tungsten silicide, is formed over the word lines. Manufacturing steps up to this point are known to those skilled in the art and will not be described in detail. Next, a silicon rich metal silicide or pure silicon layer 30 is formed on the upper surface of the metal silicide layer 28. Thus, layer 30 has a higher concentration of silicon than layer 28. This silicon-rich metal silicide layer 30 is preferably made of reactant silicon chloride (SiC).
l 2 H 2 ) and tungsten fluoride (WF 6 ) chemical vapor deposited tungsten silicide layer. Tungsten fluoride is a corrosive gas, has a relatively high density, and a fairly high vapor pressure at room temperature. Commercially available cold-wall systems have been successfully used for tungsten silicide deposition. The ratio between silicon chloride and tungsten fluoride may be, for example, 1: 1.

【００１０】次に、図２を参照すると、次に、頂部酸化
物層３２がシリコン富有タングステン珪化物または純粋
珪素の層３０の上部面に形成される。この方法で、タン
グステン酸化物の形成という欠点がないことが見いださ
れており、したがって、ワードラインのパターン化の困
難性が小さくなる。さらに、酸化物層３２の表面は滑ら
かに保たれる。さらに、本発明の前述の実施例に従って
ワードラインを製造することによって、ゲート、ポリシ
リコン２６または金属珪化物層２８の厚みは変化しな
い。Referring now to FIG. 2, a top oxide layer 32 is then formed on top of the silicon-rich tungsten silicide or pure silicon layer 30. In this way, it has been found that there is no disadvantage of the formation of tungsten oxide, thus reducing the difficulty of patterning the word lines. Further, the surface of the oxide layer 32 is kept smooth. Further, by manufacturing the word lines in accordance with the foregoing embodiment of the present invention, the thickness of the gate, polysilicon 26 or metal silicide layer 28 does not change.

【００１１】本発明は好ましい実施例で説明してきた
が、本発明はこの実施例に限定されるものではない。反
対に、本発明は種々の変形および同様な手順を含むもの
である。したがって、本発明の範囲は、すべてのそのよ
うな変形や同様な手順を含むように最も広義に解釈すべ
きである。Although the invention has been described with reference to a preferred embodiment, the invention is not limited to this embodiment. On the contrary, the invention includes various modifications and similar procedures. Therefore, the scope of the present invention should be interpreted in the broadest sense to include all such variations and similar procedures.

【００１２】[0012]

【発明の効果】以上説明したように、本発明によれば、
ワードラインのパターン化が容易なワードラインの製造
方法が得られる。As described above, according to the present invention,
A method of manufacturing a word line in which the word line can be easily patterned can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１は本発明のワードライン製造方法の好まし
い実施例の工程を示す断面図である。FIG. 1 is a sectional view showing the steps of a preferred embodiment of the word line manufacturing method of the present invention.

【図２】図２は本発明のワードライン製造方法の好まし
い実施例の工程を示す断面図である。FIG. 2 is a sectional view showing the steps of a preferred embodiment of the word line manufacturing method of the present invention.

【図３】図３はワードラインを製造する従来例の工程を
示す断面図である。FIG. 3 is a cross-sectional view showing a process of a conventional example for manufacturing a word line.

【図４】図４はワードラインを製造する従来例の工程を
示す断面図である。FIG. 4 is a cross-sectional view showing a process of a conventional example for manufacturing a word line.

【符号の説明】[Explanation of symbols]

２４ ゲート酸化物層 ２６ ポリシリコン ２８ 耐火性金属珪化物層 ３０ シリコン富有金属珪化物、または純粋シリコン
層 ３２ 頂部酸化物層24 gate oxide layer 26 polysilicon 28 refractory metal silicide layer 30 silicon rich metal silicide or pure silicon layer 32 top oxide layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 21/336 (72)発明者 イー チュン シェン 台湾 タイチュン シティ クオフェン ストリート レイン 70 ナンバー 30──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 21/336 (72) Inventor Yi Chun Shen Taiwan Taichung City Kuofen Street Rain 70 Number 30

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 ワードラインの製造方法において、 基板を用意し、 基板上にゲートを形成し、 ゲート上に第１金属珪化物層を形成し、 第１金属珪化物層より高い濃度のシリコンを持つ第２金
属珪化物層を第１金属珪化物層上に形成する、 ことを特徴とする製造方法。In a method for manufacturing a word line, a substrate is prepared, a gate is formed on the substrate, a first metal silicide layer is formed on the gate, and silicon having a higher concentration than the first metal silicide layer is formed. Forming a second metal silicide layer having the second metal silicide layer on the first metal silicide layer. 【請求項２】 請求項１記載の製造方法に従って製造さ
れたダイナミックランダムアクセスメモリ（ＤＲＡＭ）
のワードライン。2. A dynamic random access memory (DRAM) manufactured according to the method of claim 1.
Word line. 【請求項３】 第２金属珪化物層の上方に頂部酸化物層
をさらに形成することを特徴とする請求項１記載の製造
方法。3. The method of claim 1, further comprising forming a top oxide layer above the second metal silicide layer. 【請求項４】 ワードラインの製造方法において、 基板を用意し、 基板上にゲートを形成し、 ゲート上に第１金属珪化物層を形成し、 金属珪化物層上にシリコン層を形成する、 ことを特徴とする製造方法。4. A method for manufacturing a word line, comprising: providing a substrate, forming a gate on the substrate, forming a first metal silicide layer on the gate, and forming a silicon layer on the metal silicide layer. A manufacturing method characterized in that: 【請求項５】 請求項４記載の製造方法に従って製造さ
れたダイナミックランダムアクセスメモリ（ＤＲＡＭ）
のワードライン。5. A dynamic random access memory (DRAM) manufactured according to the manufacturing method according to claim 4.
Word line. 【請求項６】 シリコン層の上方に頂部酸化物層をさら
に形成することを特徴とする請求項１記載の製造方法。6. The method according to claim 1, further comprising forming a top oxide layer above the silicon layer.
JP9011965A 1996-09-21 1997-01-07 Word line manufacturing method Pending JPH10107034A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
TW085111565A TW316326B (en) 1996-09-21 1996-09-21 Manufacturing method of word line
TW85111565 1996-09-21
GB9624435A GB2319658B (en) 1996-09-21 1996-11-25 Method of fabricating a word line
NL1007868A NL1007868C2 (en) 1996-09-21 1997-12-23 Method for manufacturing a word line, and integrated semiconductor circuit obtained therewith.
FR9800082A FR2773418B1 (en) 1996-09-21 1998-01-07 METHOD FOR MANUFACTURING A WORD CONDUCTOR

Publications (1)

Publication Number Publication Date
JPH10107034A true JPH10107034A (en) 1998-04-24

Family

ID=27447012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9011965A Pending JPH10107034A (en) 1996-09-21 1997-01-07 Word line manufacturing method

Country Status (5)

Country Link
JP (1) JPH10107034A (en)
DE (1) DE19648733C2 (en)
FR (1) FR2773418B1 (en)
GB (1) GB2319658B (en)
NL (1) NL1007868C2 (en)

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KR100771538B1 (en) 2005-12-14 2007-10-31 주식회사 하이닉스반도체 Manufacturing method of semiconductor device having low resistance tungsten-polyside gate and recess channel

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DE19648733C2 (en) 2002-11-07
FR2773418A1 (en) 1999-07-09
DE19648733A1 (en) 1998-04-16
NL1007868C2 (en) 1999-06-24
FR2773418B1 (en) 2002-12-06
GB9624435D0 (en) 1997-01-15
GB2319658B (en) 2001-08-22
GB2319658A (en) 1998-05-27

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