JPH10136290A - Liquid crystal display - Google Patents

Abstract

(57) Abstract: The present invention relates to a liquid crystal display that can perform optimal display in response to a deviation of the timing of a synchronization signal in a video signal from a standard one, such as during special reproduction of a VTR. A display device is provided. SOLUTION: A plurality of vertical counters 23 and 24 for performing countdown related to control on the vertical scanning side based on a synchronization signal included in a video signal, and a liquid crystal is displayed based on count values of the plurality of vertical counters 23 and 24. A liquid crystal display device comprising: signal generation means for generating a display drive signal for driving a display panel to display. The vertical counters 23 and 24 are configured to have different conditions for resetting in response to a plurality of processing steps of the signal generation means when the synchronization signal deviates from the standard generation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, in addition to a liquid crystal display panel, for example, a video signal including a synchronizing signal is converted to an RGB signal.
A chroma circuit for demodulating a (Red-Green-Blue) signal, a synchronizing signal separating circuit for extracting a synchronizing signal from the video signal,
Also, a controller, a scanning side driving circuit, a signal side driving circuit, etc. are provided, and a control signal is sent from the controller to the scanning side driving circuit or the signal side driving circuit. A drive signal is output, and display driving of the display panel is performed.

Here, the control signals sent from the controller include a signal indicating a drive timing and a signal for matching a display position of an image with a horizontal and vertical position of a display panel. , Are generated based on a synchronization signal extracted from the video signal.

In recent liquid crystal display devices, for example, three-dimensional Y / C (Y: luminance signal, C: color signal)
A device including a signal processing circuit for achieving high image quality such as a separation circuit and a noise reduction circuit, or a so-called picture-in-picture
Some screens have a function to combine multiple images on one screen, or to insert symbols (characters) such as channels in the image (superimpose).
In the processing of such a video signal as well, based on the synchronization signal included in the video signal, in a state where the video signal is located in the horizontal scanning period and the vertical scanning period, the video signal is recognized in the horizontal and vertical scanning directions. Control is performed so that processing corresponding to the phase position is performed.

Among the controls based on the synchronization signal in the video signal as described above, as a control method corresponding to the phase in the vertical scanning direction, for example, a counter (vertical counter)
, The number of horizontal synchronization signals is counted from the time of input of the vertical synchronization signal, and a predetermined process is performed based on the counted value, or a counter (vertical counter)
In general, a clock signal generated in the same cycle (or a divided cycle) as the horizontal sync signal from the time of input of the vertical sync signal is counted, and a predetermined process is performed based on the count value. .

[0006] The generation cycle of the vertical synchronizing signal is one cycle, and reset is performed when the count number corresponding to the generation cycle of the vertical synchronizing signal is reached. For example, in the case of a counter that counts in a half cycle of the horizontal synchronizing signal generation cycle, first, it is reset when the first vertical synchronizing signal is input, and counts the clock signal generated in the half cycle. And the count number becomes a value (for example, “524” or “6”) corresponding to the generation cycle of the vertical synchronization signal.
24 "), that is, resetting at the same time as the second vertical synchronization signal is input.

As a method of resetting the counter, for example, the count number is a value corresponding to the generation cycle of the vertical synchronizing signal (for example, "524" or "624 if counting is performed by 1/2 the frequency of the horizontal synchronizing signal"). )),
An internal vertical synchronization signal indicating that the value has been reached is generated, and reset when this internal vertical synchronization signal is input or when a vertical synchronization signal (external vertical synchronization signal) extracted from a video signal is input. What you do is normal.

When there are a plurality of input video signals, such as when displaying a picture-in-picture, a counter similar to the above is provided for each video signal.
By causing each video signal to be counted, processing control suitable for the synchronization signal of each video signal is performed.

[0009]

However, in the above liquid crystal display device, for example, a VTR (Video Tape Rec.
When special playback of order), that is, rewind playback or fast forward playback, is performed, the timing of generation of the vertical synchronization signal in the video signal is shifted from the standard timing, so that signal processing based on the above vertical synchronization signal is usually performed. There was a problem that it was not performed as expected.

Specifically, as shown in FIG. 4 which is a timing chart of each signal accompanying a vertical synchronizing signal at the time of VTR reproduction, at the time of normal reproduction, the synchronizing signal (CSY) included in the video signal is as standard. Therefore, the above-described internal vertical synchronization signal (internal VD) and external vertical synchronization signal (external VD)
D) coincides with the generation timing. However, at the time of fast forward playback, the external VD is generated earlier than usual because the synchronization signal in the video signal is faster than the standard, and the vertical counter is reset by this external VD.
Does not occur. Also, during rewind reproduction, since the synchronization signal in the video signal is later than the standard, the internal VD is generated first, and then the external VD is generated later. for that reason,
The vertical counter is first reset by the internal VD, and is reset again by the delayed external VD during the countdown started from the reset.

Therefore, during rewind reproduction, the vertical counter is reset by two in response to one external VD input.
It is performed twice, and extra control is performed by the countdown during that time.

For example, if the circuit configuration is such that the display drive on the vertical scanning side of the liquid crystal display panel is started by the count value during the countdown, one external V
The driving on the vertical scanning side is performed twice for D, which causes a problem that the displayed image is instantaneously double seen.

In a case where a control signal is output to a signal processing circuit for character insertion and display according to the count value during the counting and a superimposing process of character display is started, This causes a problem that two consecutive control signals are output to the signal processing circuit.

Further, the amount of such a shift in the timing of the synchronizing signal during the special reproduction of the VTR varies depending on the tape speed and the mechanical structure of the VTR. Have difficulty.

The present invention has been made in order to solve the above-mentioned problem. Even when the generation timing of a vertical synchronizing signal in a video signal deviates from a standard one, for example, during special reproduction of a VTR, the deviation is eliminated. It is an object of the present invention to provide a liquid crystal display device capable of performing optimum display in response.

[0016]

According to a first aspect of the present invention, there is provided a vertical counter for performing a countdown related to control on a vertical scanning side based on a synchronization signal included in a video signal. A signal generating means for generating a display drive signal for driving a liquid crystal display panel based on a count value of a vertical counter, wherein the signal generating means inputs the video signal and performs display. It has a plurality of processing steps until a drive signal is generated, and the vertical counter corresponds to the plurality of processing steps when the generation timing of a vertical synchronization signal included in the video signal deviates from a standard one. And a plurality of counters having different reset conditions.

According to the first aspect of the present invention, when a video signal is inputted, the display driving signal is generated by performing processing in a plurality of processing steps of the signal generating means based on the count value of the vertical counter. . Here, a plurality of vertical counters are provided, and a plurality of counters individually correspond to each processing of the signal generating means. Since the plurality of counters have different conditions for resetting according to each processing step when the vertical synchronizing signal in the video signal deviates from the standard generation timing, for example, during the special reproduction of the VTR, Even when the vertical synchronizing signal in the video signal deviates from the standard generation timing, for example, the reset corresponding to each processing step and the countdown from the reset are performed by the plurality of counters. Then, by the countdown, appropriate signal processing is performed in each processing step. Therefore, even when the vertical synchronizing signal of the video signal deviates from the standard generation timing, an appropriate display can be performed according to the deviation.

Here, the plurality of processing steps of the signal generation means include, for example, signal processing for achieving high image quality such as three-dimensional Y / C separation processing and noise reduction processing, so-called picture-in-picture. Processing to combine multiple images on one screen, superimposition processing for embedding symbol (character) display such as channel display in an image, display signal and drive signal to scanning side drive circuit and signal side drive circuit Any processing may be included as long as vertical synchronization is required in processing from input of a video signal to output of a display drive signal, such as control processing for outputting a video signal. Further, the reset condition corresponding to the above process is, for example, the input of an external vertical synchronization signal, the input of an internal vertical synchronization signal, the simultaneous input of an external vertical synchronization signal and an internal vertical synchronization signal, or the external vertical synchronization signal. Conditions may be set according to the characteristics of each processing step, such as after a predetermined number of counts from the input of the synchronization signal or the internal vertical synchronization signal.

According to a second aspect of the present invention, in the liquid crystal display device according to the first aspect, the vertical counter is configured to input a vertical synchronizing signal included in the video signal or change a count value to a generation cycle of the vertical synchronizing signal. A first vertical counter that is reset based on reaching a corresponding predetermined value;
A second vertical counter that is reset only based on the input of a vertical synchronization signal included in the video signal.

According to the second aspect of the present invention, the same countdown is normally performed in the first and second vertical counters, but when the synchronization signal in the video signal deviates from the standard, the first countdown is performed. A different countdown is performed between the vertical counter and the second vertical counter. Specifically, when the synchronization signal is delayed from the standard, the first counter is first reset when the count value reaches a predetermined value corresponding to the generation cycle of the vertical synchronization signal, and thereafter,
It is reset again by the delayed vertical synchronizing signal. Also,
If the sync signal of the video signal is earlier than the standard, the first
Is reset by a vertical synchronizing signal that arrives earlier than the standard. That is, it is reset before the count value reaches a predetermined value corresponding to the generation cycle of the vertical synchronization signal. On the other hand, the second counter is reset only by the vertical synchronizing signal regardless of whether the synchronizing signal in the video signal is delayed or advanced from the standard.

Therefore, of the plurality of processing steps of the signal generating means, the count resetting is performed both when the count value reaches a predetermined value corresponding to the generation cycle of the vertical synchronization signal and when the vertical synchronization signal is input. The first vertical counter can cope with a process suitable for the method, and the second vertical counter can cope with a process suitable for a counting method reset only by the vertical synchronizing signal. I can do it.

The reset condition of the first and second vertical counters does not depend on the amount of shift of the synchronization signal in the video signal. Is not uniform,
The same correspondence is possible.

According to a third aspect of the present invention, in the liquid crystal display device according to the second aspect, when the count value of the first vertical counter reaches a predetermined value corresponding to a generation cycle of a vertical synchronization signal, A decoder for generating an internal vertical synchronizing signal indicating that the value has become a value, and inputting the internal vertical synchronizing signal and the vertical synchronizing signal in the video signal, generating timing of the internal vertical synchronizing signal and inputting the vertical synchronizing signal. Determining means for determining whether the timings coincide with each other; and resetting means for resetting the first and second vertical counters based on a result of the determination by the determining means. The first and second vertical counters are reset when the result of the determination by the means is coincident, and based on the generation of the internal vertical synchronization signal when the result of the determination is inconsistent. Reset the can first vertical counter, it has a structure that resets said first and second vertical counter based on the input of the vertical synchronizing signal of said video signal.

According to the third aspect of the present invention, the reset conditions of the first and second vertical counters described in the second aspect can be reliably realized.

According to a fourth aspect of the present invention, in the liquid crystal display according to the second or third aspect, the signal generating means includes a plurality of stages of processing for embedding symbol display such as channel display. The configuration is such that the fitting process is controlled based on the count value of the vertical counter.

According to the fourth aspect of the present invention, since the embedding process of the symbol display is performed based on the count value of the second vertical counter, when the synchronizing signal in the video signal deviates from the standard. However, the control of the fitting process is performed only once for one input of the vertical synchronization signal. Therefore, for example, in the conventional control of the vertical counter, there is a problem that two start signals of the fitting process are continuously output, but according to the present invention, the problem can be solved. .

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 10 according to an embodiment of the present invention, and FIG.
FIG. 3 is a schematic circuit diagram of a controller 20 that outputs a control signal to each of the signal processing circuits therein.

The liquid crystal display device 10 includes an interface circuit 12 for receiving a video signal from the outside, a chroma circuit 13 for demodulating the video signal into an RGB signal, a superimpose circuit 14, a sync separation circuit 15,
The signal side drive circuit 16 and the vertical scan side drive circuit 17, for example, the liquid crystal display panel 1 using the active matrix system
8, a video signal is input from the tuner 52 or the VTR 54 of the external device 50,
In addition to displaying an image based on the video signal, for example, a symbol display (character display) indicating the volume of the liquid crystal display device 10 is superimposed on the image display. The above-mentioned chroma circuit 13, superimpose circuit 14, signal side drive circuit 16 and vertical scan side drive circuit 17 constitute a signal generation means.

The sync separation circuit 15 is a circuit for separating and extracting a vertical sync signal and a horizontal sync signal from a video signal (composite video signal) in which a luminance signal, a color signal and a sync signal are mixed. Then, the horizontal synchronization signal and the vertical synchronization signal are output to the controller. This vertical synchronization signal is called an external vertical synchronization signal (external V synchronization signal: EXTVD).

The superimpose circuit 14 includes an A / D converter, a line memory, a sampling clock, a write clock, a character ROM (Read Only
Memory), a D / A converter, etc.,
The GB signal is once converted to a digital signal and written to the line memory, and at the same time, predetermined character data in the character ROM is overwritten at a predetermined position in the line memory, and then the data in the line memory is converted into an analog signal. It is designed to convert and output. Thus, for example, a symbol display signal indicating a volume or the like is embedded (superimposed) in the video signal, and the symbol display can be performed on the video display.

Here, the RGB converted into a digital signal
For the process of writing signals to line memory,
It is performed every time the clock signal is input based on the clock signal of the sampling clock, and the process of overwriting the character data in the line memory is performed based on the clock signal of the write clock. ing. The clock signal of the sampling clock is synchronized with the horizontal synchronizing signal in the video signal, and the frequency of the horizontal synchronizing signal is doubled (for example, 910).
Times and 1820 times).

The write clock is controlled so as to start clock transmission based on the input of a control signal (LCD control output) from the controller 20.
This controls which phase position on the horizontal and vertical scanning sides of the RGB signal is overwritten with the symbol display signal. For example, for a standard video signal, a control signal is input from the controller 20 at the same timing as the external vertical synchronization signal, so that a symbol is displayed at an appropriate position on the liquid crystal display panel. I have.

The signal side driving circuit 16 latches the input video signal for one horizontal scanning period and supplies a data signal to the signal line of the liquid crystal display panel 18. In the process of latching this signal, the video signal is latched from the beginning to the end of one horizontal scanning period based on a control signal (LCD control output) from the controller 20.

The vertical scanning side drive circuit 17 receives a control signal (LCD control output) from the controller 20 and outputs
For example, a scanning drive signal is output to the scanning lines of the liquid crystal display panel 18 one by one. The scan drive signal is controlled by a control signal of the controller 20 to which scan line is output.

As shown in FIG. 2, the controller 20 includes first and second decoders 21 and 22, first and second vertical counters 23 and 24, and a V-synchronous coincidence judging block as judging means and resetting means. 25, a horizontal counter and a horizontal decoder (not shown) involved in the control on the horizontal scanning side.

The first and second vertical counters 23,
Reference numeral 24 counts a clock signal generated by a clock (not shown) or the like, and outputs the count value to the first and second decoders 21 and 22, respectively. The clock signal is synchronized with the horizontal synchronizing signal and has a frequency twice that of the horizontal synchronizing signal. Further, the first and second vertical counters 23,
Reference numerals 24 are reset based on reset signals (VD, VD) output from the V synchronization coincidence determination block 25, respectively.

The frequency of the clock signal need not be twice as high as that of the horizontal synchronizing signal. If a control signal related to the vertical scanning, such as the same frequency as that of the horizontal synchronizing signal or three times as high, can be generated. Any frequency may be used.

The first decoder 21 outputs a predetermined control signal to the chroma circuit 13, the signal side drive circuit 16 and the vertical scan side drive circuit 17 based on the count value of the first vertical counter. In addition, the first decoder 21 determines that the count value of the first vertical counter is a value corresponding to the generation period of the vertical synchronization signal (for example, “524” in the case of the NTSC system for an interlace scanning signal, and the case of the PAL system When “624” or the like is reached, an internal vertical synchronization signal (internal V synchronization signal:
SELFR).

The second decoder 22 outputs a predetermined control signal to the superimpose circuit 14 based on the count value of the second vertical counter. For example,
When the count value reaches a predetermined value (for example, “0”) after the reset and near the reset, a start signal is output to the superimpose circuit 14.

The V synchronization coincidence determination block 25 outputs an external vertical synchronization signal (external V synchronization signal: E
XTVD) and the internal V synchronization signal from the first decoder 21 to determine whether or not the input timings of the external V synchronization signal and the internal V synchronization signal match. Also, if the determination result is a match, the first
Reset signals (VD, VD) are output to the first and second vertical counters 23 and 24, respectively. If the determination results do not match, the first and second vertical counters 23 and 24 are input by input of an external V synchronization signal. And outputs a reset signal only to the first vertical counter 23 in response to the input of the internal V synchronization signal.

The liquid crystal display device 10 of this embodiment is configured as described above. The controller 20 including the first and second vertical counters 23 and 24 controls the video signal, for example, during the special reproduction of a VTR. When the middle synchronization signal deviates from the standard generation, an appropriate display is performed by performing control corresponding to the deviation as described below.

That is, when a video signal from the tuner 52 or a video signal from the VTR 52 for normal reproduction is input to the liquid crystal display device 10, first, the video signal is transmitted through the interface circuit 12 to the chroma circuit 1.
3 and the sync separation circuit 15.

When the video signal is input to the sync separation circuit 15, the sync signal in the video signal is separated by the sync separation circuit 15, and the horizontal sync signal and the external vertical sync signal are output to the controller 20.

In the controller 20, the first and second vertical counters 23 and 24 count down as described below based on the horizontal synchronization signal and the external vertical synchronization signal. Although not shown, the horizontal counter in the controller 20 performs a countdown reset every time a horizontal synchronization signal is input.

FIG. 3 is a time chart of each signal involved in the countdown of the vertical counters 23 and 24.
FIG. 3A is a time chart when a standard video signal is input.

As shown in FIG. 3A, in a standard video signal (C-Sync), a vertical synchronization signal is generated for each field, and a predetermined number (for example, in the case of the NTSC system) in one field. "262", and "312" in the case of the PAL system).

Therefore, the external vertical synchronizing signal (EXTVD)
Is input to the V synchronization match determination block 25 for each field.

The internal vertical synchronizing signal (SELFR)
Indicates that the count value of the first vertical counter 23 is a predetermined value (for example, “524”,
Since it is output from the first decoder 21 when it reaches “624”, it is generated at the same timing as EXTTVD.

The SELFR and EXTVD are input to the V synchronization coincidence determination block 25. The V synchronization coincidence determination block 25 determines that the input timings of SELFR and EXTVD coincide with each other. , 24 are simultaneously output.

Thus, while the standard video signal is being input, the same countdown is performed in the first and second vertical counters 23 and 24. That is, EXT
After it becomes “0” at the input of VD (same as the input of SELFR), the countdown is performed in a half cycle of the horizontal synchronizing signal, and the predetermined count value (“52
4 "or" 624 ") and reset again. Then, such a countdown is repeated.

On the other hand, the video signal input to the chroma circuit 13 is demodulated into RGB signals in the circuit based on a control signal from the controller 20 and sent to the superimpose circuit 14. The control signal here includes an LCD control output and an output from a horizontal decoder (not shown), and the output from the horizontal decoder mainly performs processing based on the position of the video signal in one horizontal period.

The RGB signals are output to the superimpose circuit 14.
Is first converted into a digital signal by the A / D converter, and the RGBD digital signal from the beginning to the end of one horizontal period is written in the line memory.
Thereafter, the RGB digital signals written in the line memory are sequentially read from the beginning to the end of one horizontal period, converted to analog by the D / A converter, and sent to the signal side driving circuit. During this time, if the signal written in the line memory is for a predetermined scanning line, the character data in the character ROM is overwritten on the line memory, whereby the symbol display signal is set at a predetermined position in the video signal.

The processing of the superimpose circuit 14 is performed based on a control signal from the controller 20 including an LCD control output from the second decoder and an output from a horizontal decoder (not shown). For example, the process of writing a signal from the beginning to the end of one horizontal period in the line memory is performed in a state where the position of the signal during one horizontal period is recognized by the output from the horizontal decoder. The process of overwriting the character data on the signal of the predetermined scanning line is performed in a state where the position on the vertical scanning side is recognized by the LCD control output. Recognition of the position on the vertical scanning side
For example, when the count value of the second vertical counter 24 reaches a predetermined value (for example, “0”), a start signal is output to the superimpose circuit 14 and the like. That is, a predetermined number of scanning lines is recognized by counting the number of times of writing to the line memory from the input of the start signal.

When the overwritten RGB signal of the symbol display signal is input to the signal side drive circuit 16, the circuit latches the start and end of one horizontal period of the RGB signal, and each signal line of the liquid crystal display panel 18 is latched. Is supplied with a data signal. At the same time, a control signal (LCD control output) is output from the controller 20 to the vertical scanning side driving circuit 17,
A scan drive signal is output to a predetermined scan line. As a result, liquid crystal driving is performed at each intersection of each signal line and a predetermined scanning line of the liquid crystal display panel 18 described above.
The display of the scanning line is performed.

The display of one scan line as described above is sequentially performed for all the scan lines, whereby the display of the RGB signal in which the symbol display signal is overwritten is performed.

When a special reproduction (fast-forward) video signal is input from the VTR 54 to the liquid crystal display device 10, the controller 20 counts differently from the standard case.

FIG. 3B shows a timing chart of each signal when a fast-forward video signal is input.

In the fast-forward video signal (C-Sync), the generation timing of the vertical synchronization signal is advanced, and the generation interval of the vertical synchronization signal is equal to the number of one field (for example, “2”).
62 ”or“ 312 ”).

Therefore, the external vertical synchronizing signal (EXTVD)
Is input to the V sync match determination block 25 before the horizontal sync signal is sent for one field.

As a result, the first vertical counter 23 is reset before terminating the count corresponding to the generation cycle of the vertical synchronization signal in the standard time, so that SELFR is not output.

Therefore, only the EXTTVD is input to the V synchronization coincidence determination block 25, and the SELFR is not input.
In the synchronization match determination block 25, SELFR and EXT
It is determined that the input timing with VD does not match. Then, the reset signals (VD, VD) of the first and second vertical counters 23, 24 are simultaneously output based on the EXTVD.

While the fast-forward video signal is being input, the first and second vertical counters 23 and 24 perform the same countdown. In detail, EX
After it becomes “0” at the input of TVD, it becomes 1 /
The countdown is performed in two cycles, and before reaching the count value (e.g., "524" or "624") corresponding to the generation cycle of the vertical synchronization signal, reset is performed again by the input of EXTVD. Then, such a countdown is repeated.
The EXTTVD input shift is not uniform depending on the VTR fast-forward speed or the mechanical structure of the VTR, but is large and is "30H (30 in the horizontal synchronization period).
Times).

By such counting, the content of the control signal output from the controller 20 changes as follows, and the signal processing of the video signal also changes accordingly. That is, the count values of the first and second vertical counters 23 and 24 start counting from "0", and the EXTTVD
(For example, assuming that the count value is shifted by "10H", the count value is reset to "504").
A control signal based on the count is sent to perform the same signal processing as in the above standard, but the count is not counted (for example, assuming that the count is shifted by “10H”, the count is “5”).
05-524 ") is not output, and no signal processing is performed based on the control signal.

For example, no drive signal is output to the corresponding scanning line of the vertical scanning side drive circuit 17, and the display corresponding to that is cut off.

Even when a video signal for special reproduction (rewind) is input from the VTR 54 to the liquid crystal display device 10, the controller 20 performs counting different from the standard case.

FIG. 3C shows a timing chart of each signal when a rewind video signal is input.

In the rewind video signal (C-Sync), the generation timing of the vertical synchronizing signal is delayed, and the generation interval of the vertical synchronizing signal is equal to the number of one field (for example, "26").
2 ”or“ 312 ”).

Therefore, the external vertical synchronizing signal (EXTVD)
Is input to the V sync match determination block 25 with a slight delay after the horizontal sync signal is sent for one field.

The SELFR is output when the first vertical counter 23 performs a count corresponding to the generation cycle of the vertical synchronization signal in the standard time, and is thus output earlier than the EXTTVD input.

Therefore, since EXTVD and SELFR are input to the V synchronization coincidence determination block 25 at a timing shifted, the SEL
It is determined that the input timings of FR and EXTVD do not match. Then, a reset signal (VD) to the first counter 23 is output based on the SELFR, and then EX
First and second vertical counters 23, 2 based on TVD
4 reset signals (VD, VD) are output simultaneously.

It should be noted that this EXTTVD input shift is V
It is not uniform depending on the rewinding speed of the TR and the mechanical structure of the VTR, but is large and shifts by about "30H (30 times the horizontal synchronization period)".

During the input of the rewind video signal, the first and second vertical counters 23 and 24 perform different countdowns.
After it becomes “0” at the input of XTVD, 1
/ 2 cycle, and counts down to the count value (“524” or “6”) corresponding to the vertical synchronization signal generation cycle in the standard time.
24 "), first, the first vertical counter 23 is reset.

The first vertical counter 23 starts counting from "0" again, while the second vertical counter 24 starts counting after the count value corresponding to the generation cycle of the vertical synchronization signal in the standard time (for example, "0"). 525 ”or later, or“ 625 ”or later).

Then, the first and second counters 23 and 24 are reset by the delayed EXTTVD.
For example, assuming that "10H" has been delayed, the first counter 23
Is reset with a count value of “19”, and the second counter 24 is reset with a count value of “544”.

That is, in the first vertical counter 23, “0,1, ‥‥, 523,524,0,1, ‥‥, 1
8, 19, 0, 1, ‥‥ ”is counted by the second vertical counter 24 as“ 0, 1, ‥‥, 524, 52 ”.
5, {, 543, 544, 0, 1} "are respectively performed at the same timing. Then, such a countdown is repeated.

By such a count, the content of the control signal output from the controller 20 changes as follows. That is, counting is started from "0" by the first and second vertical counters 23 and 24, and the internal synchronization signal (S
Until the first vertical counter 23 is reset by ELFR), a control signal based on the count number during that time is sent. However, from the output of the internal synchronizing signal (SELFR) to the input of the external synchronizing signal (EXTVD), the count value of “0” to “19” is received from the first vertical counter 23 side (when delayed by 10H). Is transmitted from the second counter 24 side to “525” to “54”.
A control signal based on the count value up to “4” (in the case of a delay of 10H) is sent (for example, there is no control signal).

As a result, the external synchronization signal (EXTVD)
From the input to the output of the internal synchronization signal (SELFR)
The same signal processing as in the above standard is performed. From the output of the internal synchronization signal (SELFR) to the external synchronization signal (EX
Until the input of TVD), the signal side drive circuit 16 and the vertical scan side drive circuit 17 supply a drive signal to the scan line based on the count value during this period, and display on the scan line based on the count value is performed. Done. That is, the image appears double for a moment. However, during this time, the start signal for the process of overwriting the character data is not output to the superimpose circuit 14. Then, such signal processing is repeated.

In other words, the process of inserting character data is performed only once for each input of the external synchronization signal (EXTVD). The problem that the start signal is input twice to the impose circuit 14 is prevented.

As described above, according to the liquid crystal display device 10 of this embodiment, the signal generation means (the chroma circuit 1) for generating the display drive signal based on the count value of the vertical counter.
3, superimpose circuit 14, signal side drive circuit 1
6. In the vertical scanning side drive circuit 17), the first vertical counter 23 and the second vertical counter 24 separately correspond to the respective processing steps, and the synchronization signal included in the video signal is a standard signal. Since the first and second vertical counters are reset under different conditions when deviation occurs, for example, when the synchronization signal in the video signal deviates from the standard, such as a special reproduction of a VTR. In addition, different resets and countdowns are performed by the first and second vertical counters, and the different countdowns allow, for example, separate control of the superimpose circuit 14 and other circuits. Therefore, appropriate signal processing can be performed for each processing step, and even when the synchronization signal of the video signal deviates from the standard generation, an appropriate display can be performed according to the deviation. .

In particular, when the synchronization signal in the video signal is shifted by the first and second vertical counters, when the count value reaches a predetermined value corresponding to the generation cycle of the vertical synchronization signal, and when the vertical synchronization signal is shifted. A process suitable for a counting method that is reset both at the time of input (for example, processing of the vertical scanning side drive circuit 17) and a processing suitable for a counting method that is reset only by a vertical synchronization signal (for example, super , Etc.) can be separately handled.

Further, since the reset conditions of the first and second vertical counters do not depend on the amount of the shift of the synchronizing signal in the video signal, the amount of the shift of the synchronizing signal, for example, in the special reproduction of a VTR, Is not uniform,
The same correspondence is possible.

Further, the reset operation of the first and second vertical counters under the above-described reset condition is reliably performed by the operation of the first decoder 21 and the V synchronization coincidence determination block 25.

Further, since the second vertical counter corresponds to the embedding process of the symbol display of the superimpose circuit 14, even if the synchronization signal in the video signal deviates from the standard, the vertical synchronization signal can be used. For one input,
The inset processing control can be performed only once. Therefore, for example, in the conventional control of the vertical counter, there is a problem that two start signals of the fitting process are continuously output, but according to the present invention, the problem is solved.

The present invention is not limited to the liquid crystal display device 10 of this embodiment. For example, the driving method of the liquid crystal is not limited to active matrix driving, but may be direct matrix (multiplex) driving. The driving method is also applicable. Further, as the signal generating means, in addition to the signal generating means in this embodiment, a signal processing circuit for improving image quality or a signal processing circuit for adding a special function such as picture-in-picture may be provided.
A vertical counter with further different reset conditions may be provided for these signal processing circuits, and appropriate control may be performed based on the count value. Also, GS
The second vertical counter is used for a signal having a short vertical blanking period (a signal in which a video signal is output in several H (horizontal scanning periods) from a vertical synchronizing signal) such as a video signal for RT and a wide screen. Control is effective.

[0086]

According to the first aspect of the present invention, in the signal generating means for generating a display drive signal based on the count value of the vertical counter, a plurality of counters are separately provided for a plurality of processing steps of the signal generating means. The processing of each processing step is performed based on the count values of the plurality of counters, and when the synchronization signal included in the video signal deviates from the standard generation, the plurality of processing is performed. Are reset under the reset conditions corresponding to the respective processing steps. Therefore, even if the synchronization signal in the video signal deviates from the standard, for example, in the special reproduction of a VTR, the plurality of counters Reset corresponding to each processing step and countdown from the reset can be performed. And
By the countdown, appropriate signal processing is performed in each processing step, so that even if the synchronization signal of the video signal deviates from the standard generation, an appropriate display can be performed in accordance with the deviation.

According to the second aspect of the present invention, in particular, the first
And the second vertical counter resets both when the count value reaches a predetermined value corresponding to the generation cycle of the vertical synchronization signal and when the vertical synchronization signal is input, when the synchronization signal in the video signal is shifted. Each of the processing steps suitable for the counting method performed and the processing step suitable for the counting method reset only by the vertical synchronization signal can be separately dealt with.

Further, since the reset conditions of the first and second vertical counters do not depend on the amount of the shift of the synchronizing signal in the video signal, the amount of the shift of the synchronizing signal is different, for example, in the special reproduction of a VTR. Is not uniform,
The same correspondence is possible.

According to the third aspect of the present invention, when the count value of the first vertical counter reaches a predetermined value corresponding to the generation cycle of the vertical synchronizing signal, the internal vertical signal indicates that the value has reached that value. A decoder for generating a synchronizing signal; inputting the internal vertical synchronizing signal and the vertical synchronizing signal in the video signal; and determining whether the generation timing of the internal vertical synchronizing signal matches the input timing of the vertical synchronizing signal. 3. A resetting means for resetting the first and second vertical counters according to claim 2, comprising: a judging means for judging whether the first and second vertical counters are reset based on a judgment result of the judging means. The conditions can be reliably realized.

According to the fourth aspect of the present invention, in particular, since the second vertical counter corresponds to the embedding process of the symbol display such as the channel display, the synchronization signal in the video signal is shifted from the standard. The vertical synchronization signal 1
It is possible to control the fitting process only once for each input. Therefore, for example, in the conventional control of the vertical counter, there is a problem that two start signals of the fitting process are continuously output, but according to the present invention, the problem can be solved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device as an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an outline of a circuit configuration of a controller of FIG. 1;

FIGS. 3A and 3B are timing charts showing timings of a reset signal and the like with respect to a synchronization signal included in a video signal, and FIG. 3A is a timing chart for a video signal in a standard time, and FIG. Timing chart for the video signal of
(C) is a timing chart for a video signal during special reproduction (rewind).

FIG. 4 is a timing chart showing a synchronizing signal and a generation timing of each signal according to a VTR reproducing method for explaining a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 13 Chroma circuit 14 Superimpose circuit 15 Synchronization separation circuit 16 Signal side drive circuit 17 Vertical scan side drive circuit 18 Liquid crystal display panel 20 Controller 21 First decoder 22 Second decoder 23 First vertical counter 24 Second Vertical counter 25V synchronization match judgment block

Claims (4)

[Claims] 1. A vertical counter for performing a countdown involved in control on a vertical scanning side based on a synchronization signal included in a video signal, and a display for driving a liquid crystal display panel based on a count value of the vertical counter. A signal generation unit for generating a drive signal, wherein the signal generation unit has a plurality of processing steps until the video signal is input and a display drive signal is generated, and the vertical counter is And a plurality of counters having different conditions for resetting corresponding to the plurality of processing steps when the generation timing of the vertical synchronization signal included in the video signal deviates from a standard one. Characteristic liquid crystal display device. 2. The apparatus according to claim 1, wherein the vertical counter receives an input of a vertical synchronization signal included in the video signal, or
A first vertical counter that is reset based on a count value reaching a predetermined value corresponding to a generation cycle of the vertical synchronization signal, and a first vertical counter that is reset based only on input of a vertical synchronization signal included in the video signal 2. The liquid crystal display device according to claim 1, further comprising a second vertical counter. 3. A decoder for generating, when the count value of the first vertical counter reaches a predetermined value corresponding to a generation cycle of a vertical synchronization signal, generating an internal vertical synchronization signal indicating the value. Determining means for inputting the internal vertical synchronizing signal and the vertical synchronizing signal in the video signal, and judging whether or not the generation timing of these internal vertical synchronizing signals and the input timing of the vertical synchronizing signal coincide with each other; Based on the result of the determination by the determination means, the first and second
Resetting means for resetting the vertical counters of the above, wherein the resetting means resets the first and second vertical counters when the result of the judgment by the judging means is coincident, and when the result of the judgment is inconsistent And resetting the first vertical counter based on the generation of the internal vertical synchronization signal, and resetting the first and second vertical counters based on the input of a vertical synchronization signal of the video signal. 3. The liquid crystal display device according to 2. 4. The process of the signal generating means in a plurality of stages includes an inset process of displaying a symbol such as a channel display, and the inset process is controlled based on a count value of the second vertical counter. The liquid crystal display device according to claim 2, wherein