JPH10143462A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve noise resistance by external noise and to improve reliability by resetting an input/output mode every time the write instruction and read instruction of one time is executed. SOLUTION: In the case of setting a port to an output mode so as to output data, by inputting write signals 104 and port selection signals 103 simultaneously transferred from an internal bus 10 at the time of the output of the data 102 to an AND circuit 12, an input/output mode latch 1 is set to the output mode by input/output mode signals 113 which are the output of the AND circuit 12. In the case of setting the port to an input mode so as to input the data, by inputting the port selection signals 103 and read signals 105 to a NAND circuit 13, the input/output mode latch 1 is reset and set to the input mode by reset signals 112 which are the output of the NAND circuit 13. In such a manner, the input/output mode of the port is reset at the time of setting a value to an output latch and at the time of inputting the data from the port.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a setting of an input / output mode for setting and operating peripheral functions.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional microcomputer uses a port selection signal 203 and a port input / output mode signal 201 which are transferred from an internal bus 30 according to software instructions. Input / output mode latch 21 for outputting control signal 206
An AND circuit 29 for outputting an output control signal 207 from the write signal 204 and the port selection signal 203; and an input control signal 20 from the read signal 205 and the port selection signal 203.
8, an output latch 23 that outputs data 202 by an output control signal 207, an input latch 24 that inputs data 211 by an input control signal 208, and an output buffer controlled by an input / output control signal 206. 27, an input buffer 28 controlled by an input / output control signal 206 passed through an inverter 29, and an input / output port 25 connected to the output buffer 27 and the input buffer 28.

In the conventional input / output port shown in FIG. 3, in order to switch the port to output, a port selection signal 2 transferred from the internal bus 30 by a software instruction is used.
03 and the port input / output mode signal 201 put the input / output mode latch 21 into the output mode, and the input / output control signal 2
06 is output, and the output buffer 27 is set in an output enabled state.

Similarly, in order to switch the port to input, the input / output mode latch 21 is set to the input mode by the port input / output mode signal 201 and the port selection signal 203 which are transferred from the internal bus 30 by the instruction of software, and The control signal 206 is output. Input control signal 208
Is input to the input buffer 28 through the inverter 22.

When data is output from a conventional port, data 202, a write signal 204, and a port selection signal 203 are transferred from the internal bus 30. The logical product of the write signal 204 and the port selection signal 203 is calculated by the AND circuit 2
9 and outputs the result to the output latch 23 as the output control signal 207.

The output latch 23 converts the data 202 and the output control signal 207 as output data 209 into the output buffer 2.
7 is output. Data 209 is output from output buffer 27 to port 25.

When inputting data, an input / output mode
In response to the input / output control signal 206 output from the latch 21, the data 210 input to the input buffer 28 in the input enabled state is output to the input latch 24.

[0008] Read signal 205 and port selection signal 203
Is performed by the AND circuit 26, and the result is output to the input latch 24 as an input control signal 208.

The input latch 24 outputs input data 210 to the internal bus 30 in response to the input of the input control signal 208.

[0010]

In the conventional microcomputer, once a value is set in the input / output mode latch, unless the software is intentionally refreshed by software, the value is specifically reset only when the same setting is used. I never did. Therefore, the input / output mode of the port or the contents of the output latch may be changed due to the influence of external noise, surge, or the like, and an abnormal operation may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer having an input / output mode latch for setting input / output of a port by software in view of the above-mentioned problems of the prior art. By re-setting the input or output mode of the input / output port, the noise resistance due to external noise is improved,
The purpose is to improve reliability.

[0012]

According to the present invention, there is provided a microcomputer having an input / output mode latch for setting input / output of a port by software. The latch is reset to the output mode by hardware, and the input / output mode latch is reset to the input mode by hardware when a read instruction is executed.

According to the present invention, the input / output mode of the port is reset when a value is set to the output latch and when data is input from the port. Therefore, there is no need to refresh the port mode.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. FIG. 1 is an electric circuit diagram showing the configuration of the embodiment of the present invention.

In this embodiment, as shown in FIG. 1, an input / output mode latch 1 for outputting an input / output mode signal 101 transferred from an internal bus 10 and an input / output control signal 106 corresponding to a port selection signal 103 is provided. An AND circuit 9 for outputting an output control signal 114 corresponding to the port selection signal 103 and the write signal 104 transferred from the internal bus 10, and an output control signal 1 for the data 102 transferred from the internal bus 10.
Output latch 3 for outputting to output buffer 7 corresponding to 14
And a port selection signal 103 transferred from the internal bus 10
AND circuit 6 for outputting an input control signal 108 corresponding to the read signal 105 and the read signal 105; an input latch 4 for outputting data 110 of the input buffer 8 to the internal bus 10 in response to the input control signal 108; An output buffer 7 controlled by 106 to output data 109 of the output latch 3 to the port 5; an input buffer 8 controlled by the input / output control signal 106 to output input data 111 of the port 5 to the input latch 4; A which outputs an input / output mode signal corresponding to the port selection signal 103 and the write signal 104 transferred from the bus 10 to the input / output mode latch
ND circuit 12 and NAND circuit 1 that outputs reset signal 112 to input / output mode latch 1 from port selection signal 103 and read signal 105 transferred from internal bus 10
Three.

The feature of this embodiment is that an AND circuit 12 and a NAND circuit 13 are newly added to the circuit configuration of the conventional example shown in FIG. The operation of the other circuits except for the added circuit is basically the same as that of the conventional example described above.

In this embodiment, when the port is set to the output mode for outputting data, the write signal 104 and the port selection signal 103 transferred from the internal bus 10 are simultaneously output when the data 102 is output. The input / output mode latch 113 is set to the output mode by the input / output mode signal 113 which is the output of the AND circuit 12.

When outputting data, the data 102, the write signal 104, and the port selection signal 103 are transferred from the internal bus 10. The logical product of the write signal 104 and the port selection signal 103 is performed by the AND circuit 9, and the result is output to the output latch 3 as the output control signal 114.
The input / output control signal 106 output from the input / output mode latch 1 puts the output buffer 7 in an input enabled state.

The output latch 3 outputs the data 102 and the output control signal 114 to the output buffer 7 as output data 109. Data 109 is output from output buffer 7 to port 5
Is output to

Similarly, when the port is set to the input mode for inputting data, the port selection signal 103 and the read signal 105 are input to the NAND circuit 13 so that the reset signal 112 output from the NAND circuit 13 is output.
Resets the input / output mode latch 1 to set the input mode.

When inputting data, the input / output control signal 10 output from the input / output mode latch 1 is input.
6 outputs the data 111 input from the input buffer 8 in the input enabled state to the input latch 4.

Read signal 105 and port select signal 103
Is performed by the AND circuit 6 and the result is input control signal 1
08 and output to the input latch 4.

The input latch 4 outputs data 110 to the internal bus 10 in response to the input of the input control signal 108.

According to the present embodiment, as shown in the flowchart of FIG. 2, in order to output data by a conventional microcomputer, data is set in an output latch as shown in FIG. 2B (step B1). Thereafter, it is necessary to set the input / output mode of each port (step B2). In order to output data with the microcomputer of the present invention, as shown in FIG. 2A, when data is set in the output latch, the port mode is reset (step A1). , And the program can be shortened.

Even when the input instruction is executed, in the conventional microcomputer, even if the port originally used as the input port is switched to the output port due to external noise or the like, the correct value is obtained after the port mode refresh operation is performed. However, in the microcomputer of the present invention, the mode is reset to the input when the input command is executed, so that the data can be input reliably.

That is, by setting the port every time a write command or a read command is executed according to the present invention, the input / output mode is not inverted due to external noise or the like.

[0027]

As described above, in this microcomputer, the input / output mode is reset every time one write command and one read command are executed. Therefore, the input / output mode is inverted due to external noise or the like. Even at the port, correct operation can be performed at the time of instruction execution, and abnormal operation can be prevented.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2A is a flowchart showing a processing procedure in an embodiment of the present invention, and FIG. 2B is a flowchart showing a processing procedure in a conventional example.

FIG. 3 is an electric circuit diagram showing a configuration of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input / output mode latch 2 inverter 3 output latch 4 input latch 5 port 6 AND circuit 7 output buffer 8 input buffer 9 AND circuit 10 internal bus 11 OR circuit 12 AND circuit 13 NAND circuit 21 input / output mode latch 22 inverter 23 output Latch 24 Input latch 25 Port 26 AND circuit 27 Output buffer 28 Input buffer 29 AND circuit 30 Internal bus 101 I / O mode signal 102 Data 103 Port selection signal 104 Write signal 105 Read signal 106 I / O control signal 107 Reset signal 108 Input control Signal 109 output data 110 input data 111 data 112 reset signal 113 input / output mode signal 114 output control signal 201 port input / output mode signal 202 data 203 port Selection signal 204 write signal 205 read signal 206 input / output control signal 207 output control signal 208 input control signal 209 output data 210 input data 211 data

Claims (5)

[Claims] In a microcomputer having an input / output mode latch for setting input / output of a port by software, the input / output mode latch is reset to an output mode by hardware when a write instruction is executed. Microcomputer. 2. A microcomputer having an input / output mode latch for setting input / output of a port by software, wherein the input / output mode latch is reset to an input mode by hardware when a read instruction is executed. Microcomputer. 3. A microcomputer having an input / output mode latch for setting input / output of a port by software outputs an input / output control signal corresponding to an input / output mode signal transferred from an internal bus and a port selection signal. An input / output mode latch, an AND circuit that outputs an input / output mode signal corresponding to a port selection signal and a write signal transferred from the internal bus to the input / output mode latch, and a port selection signal transferred from the internal bus. An AND circuit that outputs an output control signal corresponding to a write signal; an output latch that outputs data transferred from an internal bus to an output buffer in response to the output control signal; A microphone having an output buffer for outputting data from an output latch to a port. Computer. 4. A microcomputer having an input / output mode latch for setting input / output of a port by software, outputs an input / output control signal corresponding to an input / output mode signal transferred from an internal bus and a port selection signal. An input / output mode latch, a NAND circuit that outputs a reset signal from the port select signal and the read signal transferred from the internal bus to the input / output mode latch, and is controlled by the input / output control signal to input data of the port. An input buffer for holding, an AND circuit for outputting an input control signal corresponding to a port selection signal and a read signal transferred from the internal bus, and outputting data of the input buffer to the internal bus in response to the input control signal A microcomputer having an input latch. 5. A microcomputer having an input / output mode latch for setting input / output of a port by software outputs an input / output control signal corresponding to an input / output mode signal transferred from an internal bus and a port selection signal. An input / output mode latch, an AND circuit that outputs an input / output mode signal corresponding to a port selection signal and a write signal transferred from the internal bus to the input / output mode latch, and a port selection signal transferred from the internal bus. A NAND circuit that outputs a reset signal from a read signal to the input / output mode latch, an AND circuit that outputs an output control signal corresponding to a port selection signal and a write signal transferred from an internal bus, An output latch for outputting data transferred from an internal bus to an output buffer; An output buffer controlled by a control signal to output data from the output latch to a port; an input buffer controlled by the input / output control signal to hold input data of the port; and a port selection signal transferred from an internal bus And an AND circuit for outputting an input control signal corresponding to a read signal; and an input latch for outputting data of the input buffer to an internal bus in response to the input control signal. .