JPH10189631A5 - Semiconductor device manufacturing method and mold used in this manufacturing method - Google Patents

Semiconductor device manufacturing method and mold used in this manufacturing method

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Publication number
JPH10189631A5
JPH10189631A5 JP1997309603A JP30960397A JPH10189631A5 JP H10189631 A5 JPH10189631 A5 JP H10189631A5 JP 1997309603 A JP1997309603 A JP 1997309603A JP 30960397 A JP30960397 A JP 30960397A JP H10189631 A5 JPH10189631 A5 JP H10189631A5
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JP
Japan
Prior art keywords
mold
resin
manufacturing
semiconductor device
internal space
Prior art date
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Granted
Application number
JP1997309603A
Other languages
Japanese (ja)
Other versions
JPH10189631A (en
JP3902846B2 (en
Filing date
Publication date
Application filed filed Critical
Priority to JP30960397A priority Critical patent/JP3902846B2/en
Priority claimed from JP30960397A external-priority patent/JP3902846B2/en
Publication of JPH10189631A publication Critical patent/JPH10189631A/en
Publication of JPH10189631A5 publication Critical patent/JPH10189631A5/en
Application granted granted Critical
Publication of JP3902846B2 publication Critical patent/JP3902846B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Claims (7)

樹脂を用いて半導体チップを被覆してパッケージを形成する樹脂封止型の半導体装置の製造方法であって、
リードフレームに搭載された前記半導体チップのパッドと前記リードフレームのインナーリードとをボンディングワイヤで接続する第１の工程と、
昇降可能な金型キャビティ可動部を有する上型及び当該上型と一体となって内部空間を形成する下型からなる金型を用い、前記半導体チップ及び前記ボンディングワイヤを含む部分を前記金型の前記内部空間に設置する第２の工程と、
前記金型キャビティ可動部を下降させて前記ボンディングワイヤの上部を押圧し、ワイヤ高さを規制した状態のまま前記金型内に前記樹脂を充填する第３の工程と、
前記金型キャビティ可動部を前記パッケージの表面高さ位置まで戻し、この動作により形成された未充填空間に更に前記樹脂を充填する第４の工程とを含むことを特徴とする半導体装置の製造方法。 A method for manufacturing a resin-sealed semiconductor device in which a semiconductor chip is covered with resin to form a package,
a first step of connecting pads of the semiconductor chip mounted on a lead frame to inner leads of the lead frame with bonding wires;
a second step of using a mold including an upper mold having a movable mold cavity portion that can be raised and lowered and a lower mold that is integrated with the upper mold to form an internal space, and placing a portion including the semiconductor chip and the bonding wires in the internal space of the mold;
a third step of lowering the mold cavity movable part to press the upper part of the bonding wire and filling the resin into the mold while regulating the wire height;
and a fourth step of returning the mold cavity movable part to a surface height position of the package and further filling the unfilled space formed by this movement with the resin. 前記第４の工程において、前記金型内に充填された前記樹脂が未硬化の内に前記未充填空間に更に前記樹脂を充填することを特徴とする請求項１に記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein in the fourth step, the unfilled space is further filled with the resin while the resin filled in the mold is still unhardened. 前記金型キャビティ可動部は、前記内部空間内に前記樹脂を充填することを特徴とする請求項１又は２に記載の半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein the mold cavity movable portion fills the resin into the internal space. 樹脂を用いて半導体チップを被覆してパッケージを形成し、半導体装置を製造する金型であって、
昇降可能な金型キャビティ可動部を有する上型と、当該上型と一体となって内部空間を形成する下型とを備えることを特徴とする金型。 A mold for manufacturing a semiconductor device by covering a semiconductor chip with a resin to form a package,
A mold characterized by comprising an upper mold having a mold cavity movable part that can be raised and lowered, and a lower mold that is integrated with the upper mold to form an internal space. 前記金型キャビティ可動部には、少なくとも前記半導体チップに接続されたボンディングワイヤとの接触面に滑り止め加工が施されていることを特徴とする請求項４に記載の金型。5. The mold according to claim 4, wherein the mold cavity movable part has an anti-slip treatment applied to at least the surface that comes into contact with the bonding wires connected to the semiconductor chip. 前記滑り止め加工は、梨地処理であることを特徴とする請求項４又は５に記載の金型。6. The mold according to claim 4, wherein the anti-slip treatment is a matte finish. 前記金型キャビティ可動部は、前記内部空間内に前記樹脂を充填することを特徴とする請求項４〜６のいずれか１項に記載の金型。The mold according to claim 4 , wherein the mold cavity movable portion fills the resin into the internal space.
JP30960397A 1996-10-25 1997-10-24 Manufacturing method of semiconductor device and mold used in this manufacturing method Expired - Fee Related JP3902846B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30960397A JP3902846B2 (en) 1996-10-25 1997-10-24 Manufacturing method of semiconductor device and mold used in this manufacturing method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP29981996 1996-10-25
JP8-299819 1996-10-25
JP30960397A JP3902846B2 (en) 1996-10-25 1997-10-24 Manufacturing method of semiconductor device and mold used in this manufacturing method

Publications (3)

Publication Number Publication Date
JPH10189631A JPH10189631A (en) 1998-07-21
JPH10189631A5 true JPH10189631A5 (en) 2005-06-30
JP3902846B2 JP3902846B2 (en) 2007-04-11

Family

ID=26562085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30960397A Expired - Fee Related JP3902846B2 (en) 1996-10-25 1997-10-24 Manufacturing method of semiconductor device and mold used in this manufacturing method

Country Status (1)

Country Link
JP (1) JP3902846B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100566496B1 (en) 2001-12-07 2006-03-31 야마하 가부시키가이샤 Apparatus for manufacturing semiconductor device
JP5543084B2 (en) 2008-06-24 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル Manufacturing method of semiconductor device

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