JPH10197847A - Liquid crystal display - Google Patents

Abstract

(57) [Problem] To provide a liquid crystal display device with less flicker. SOLUTION: In an active matrix type liquid crystal display panel in which pixels are arranged in a matrix, one frame is divided into three fields. In the first field,
The image data is written to the pixels on the two consecutive lines of the first, second, seventh, eighth, thirteen, thirteen,..., And the subsequent four lines are skipped. Here, the polarity of the image data to be written to the pixels in the first line and the second line is reversed. Similarly, in the second frame, lines 3, 4, 9, 10,..., And in the third frame, lines 5, 6, 11, 12,. Change. As a result, there is no variation in the ratio between the number of pixels of positive polarity and the number of pixels of negative polarity, and the positional distribution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that drives a liquid crystal panel with a liquid crystal by an MFD (Multi-Field Driving) method.

[0002]

2. Description of the Related Art An MFD method is known as a driving method of an active matrix type liquid crystal panel.

In the MFD method, for example, one frame is divided into three fields. That is, in this method, 1
In the field, the image signal is written only to one third of the pixels in one screen, and the time for writing the image signal to each pixel is lengthened. When the liquid crystal panel is driven by this method, a signal is written to each pixel of the liquid crystal panel with the polarity shown in FIG. Note that, in FIG. 13, a row is shown in the vertical direction (a group of pixels connected to the same gate line; the same applies hereinafter), and a field is shown in the horizontal direction. Also,
1V is one vertical period.

However, when the liquid crystal panel is driven by this method, a pixel to which a positive polarity voltage is applied at a certain time (hereinafter, referred to as a positive polarity pixel) and a pixel to which a negative polarity voltage is applied (hereinafter referred to as a pixel). Hereinafter, the ratio of the number of pixels having a negative polarity varies (a maximum of 2: 1 or 1: 2). This liquid crystal panel has a drawback that flicker is noticeable due to the variation in the ratio between the number of pixels of the positive polarity and the number of pixels of the negative polarity.

In order to improve this drawback, a method of changing the polarity of the voltage applied to the pixels every three rows (line inversion method) as shown in FIG. 14 is also used. According to this method, the number of positive polarity pixels and the number of negative polarity pixels are the same in each field, and there is no variation in the ratio of these numbers. Thereby, flicker can be improved more than in the above case.

However, according to this method, pixels having the same polarity may be arranged in three rows, and the positional distribution of positive and negative pixels is biased. And
There has been a problem that flicker occurs due to such a bias in the positional distribution between the positive polarity pixel and the negative polarity pixel.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a liquid crystal display device which is less likely to cause flicker.

[0008]

In order to achieve the above object, a liquid crystal display device according to the present invention comprises an active matrix type liquid crystal panel in which pixels are arranged in a matrix, and 2 m (n + 1) of the matrix in each field. A selection driving means for sequentially selecting 2m rows every other row, changing a row to be selected for each field and selecting all rows in one frame composed of (n + 1) fields, and a 2m (n + 1) row of image signals; Signal driving means for holding every 2 m rows every other time and writing a signal corresponding to the held 2 m row image signals to the pixels of the 2 m rows selected by the selection driving means alternately with the opposite polarity for each row; And m and n are natural numbers.

In the above liquid crystal display device, the number of pixels for writing an image signal with a positive polarity and the number of pixels for writing an image signal with a negative polarity are the same. That is, there is no variation in the ratio between the number of positive polarity pixels and the number of negative polarity pixels. Moreover, pixels having the same polarity are arranged in up to two rows, and there is no positional deviation between positive polarity pixels and negative polarity pixels. Therefore, it is possible to suppress the occurrence of flicker in the liquid crystal panel.

In the above-mentioned liquid crystal display device, for example, the selection driving means has means for sequentially selecting each of the continuous 2m rows at a time of (n + 1) times of one horizontal period, and the signal driving means comprises: There may be provided a means for sequentially writing the signals corresponding to the held image signals of 2 m rows to the rows selected by the selection driving means.

In the above liquid crystal display device, the signal driving means may further include means for inverting the polarity of a signal to be written to the pixel for each frame.

In the above liquid crystal display device, it is possible to increase the time for writing a signal to the pixel. Therefore, it is preferable to apply the present invention to a liquid crystal display device having a liquid crystal panel in which liquid crystal having spontaneous polarization is sealed between a pair of substrates arranged opposite to each other.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to this embodiment. As shown in the figure, this liquid crystal display device has a video signal processing unit 0, a control unit 1,
It comprises a level shift circuit 2, a common voltage generation circuit 3, a gate driver 4, a source driver 5, and a liquid crystal panel 6.

The video signal processing unit 0 receives a video signal and extracts a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC from the video signal. Further, the video signal processing unit 0 generates a dot clock signal DOTC based on the extracted vertical synchronization signal VSYNC and horizontal synchronization signal HSYNC.
Generate K. The video signal processing unit 0 converts the analog image signal in the video signal into a dot clock signal DOTC.
Sampling is performed in synchronization with K to extract a digital image signal D1.

The control unit 1 includes a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC supplied from the video signal processing unit 0.
A data polarity signal POLD, a common polarity signal POLC, a source driver control signal group CONTS, and a gate driver control signal group CONTG are generated based on C and the dot clock DOTCK. The configuration of the control unit 1 will be described later in more detail.

The inversion / level shift circuit 2 performs processing such as contrast adjustment and gamma correction on the image signal D1 supplied from the video signal processing unit 0. Further, it generates an image signal D2 in which the polarity of the image signal D1 is inverted / non-inverted according to the data polarity signal POLD supplied from the control unit 1.

The common voltage generating circuit 3 applies a common potential having a predetermined polarity to the common electrode of the liquid crystal panel 6 in accordance with the common polarity signal POLC supplied from the control unit 1. The gate driver 4 controls a predetermined gate line 4 according to a gate control signal group CONTG supplied from the control unit 1.
Select 0 and drive.

The source driver 5 sequentially latches the image signal D2 supplied from the inversion / level shift circuit 2 according to the source control signal group CONTS supplied from the control unit 1, and sets a potential corresponding to the latched image signal to a predetermined value. Give to pixel electrode. The configuration of the source driver 5 will be described later in more detail.

As shown in FIG. 2, the liquid crystal panel 6 has a liquid crystal 63 sealed in a cell in which a pair of transparent substrates 61 and 62 arranged opposite to each other are bonded with a sealing material 64. As the liquid crystal 63, a liquid crystal having spontaneous polarization such as a ferroelectric liquid crystal or an antiferroelectric liquid crystal is used.

A common electrode 65 is provided on the opposite surface of the transparent substrate 61.
Are formed. The common electrode 65 is connected to the common voltage generation circuit 3. On the other hand, on the opposing surface of the transparent substrate 62, a plurality of pixel electrodes 66 are formed in a matrix. Each pixel electrode 66 has a thin film transistor (TF
T) 67 drain is connected. In addition, TFT6
The gate of 7 is connected to the gate line 40, and the source of the TFT 67 is connected to the source line 50.

On the opposite surface of the transparent substrate 61, a horizontal alignment film 68 is formed so as to cover the common electrode 65.
The pixel electrode 66 and the TFT 6
7, a horizontal alignment film 69 is formed. These horizontal alignment films 68 and 69 are rubbed in a predetermined direction.

A spacer 70 is provided between the transparent substrates 61 and 62 so as to keep the distance between the transparent substrates 61 and 62 constant.
Is inserted. Further, polarizing plates 71 and 72 are arranged outside the transparent substrates 61 and 62, respectively.
A backlight (not shown) is arranged outside the polarizing plate 72.

Next, the configuration of the control unit 1 will be described in detail with reference to the block diagram of FIG. As shown in FIG. 3, the control unit 1 includes a line counter 1a, a field counter 1b, a start row setting ROM 1c, a control counter 1d,
1e, dot counter 1f, decoders 1g-1j, AN
It comprises D circuits 1k-1p, an OR circuit 1q, and a toggle counter 1r.

The line counter 1a receives the horizontal synchronizing signal HS
It counts up each time YNC is input, is cleared each time the vertical synchronization signal VSYNC is input, and counts the number of lines of the image signal from the vertical synchronization signal VSYNC. When the line counter 1a counts a predetermined value, the decoder 1g outputs a start signal GSRT for instructing the gate driver 4 to start.

The field counter 1b is composed of a hexadecimal counter and counts six fields. In the start row setting ROM 1c, the initial value (negative number) of the control counter 1d is written, and the output of the field counter 1b is the address of each initial value.

The control counter 1d outputs 0 from the decoder 1g.
Is output, the initial value (negative number) output from the start row setting ROM 1c is preset, and the horizontal synchronization signal HSY is output.
It counts up to 0 each time NC is input. The time when the value of the control counter 1d becomes 0 is the start timing for each field.

The control counter 1e is constituted by a hexadecimal counter, which counts up each time the horizontal synchronizing signal HSYNC is input, and is cleared each time 0 is output from the control counter 1d. The dot counter 1f counts up for each pulse of the dot clock DOTCK, and is cleared every time the horizontal synchronization signal HSYNC is input.

The decoder 1h includes a field counter 1b
Outputs the data polarity signal POLD and the common polarity signal POLC at a predetermined timing based on the value counted by the control counter 1e and the value counted by the control counter 1e.

The decoder 1i has control counters 1d, 1e
And outputs signals DC21 to DC25 based on the value of. Here, the timing at which the control counter 1e starts counting up from 0 differs for each field. For this reason,
The output timing of the signals DC21 to DC25 differs for each field. That is, the signals DC21 to DC25 control the operation within one vertical period for each field.

FIGS. 4 to 6 show timing charts of the signals DC21 to DC25. Here, FIG.
FIG. 5 shows the case of the fourth field (the value of the field counter 1b is 0 or 3), FIG. 5 shows the case of the second and fifth fields (the value of the field counter 1b is 1 or 4), and FIG. The case of a field (the value of the field counter 1b is 2 or 5) is shown, respectively.

The signals DC21 and DC22 control the generation of the gate shift clock YCLK. Signal D
C23 controls generation of a source start signal SSRT for instructing start of operation of the shift register in the source driver 5. The DC 24 includes a switching signal HCNT for switching a latch circuit described later and the source driver 5.
Is controlled to generate the source clear signal SCLR for clearing the output of the control circuit. The DC 25 controls generation of an output enable signal SOE described later.

The decoder 1j outputs a gate clear signal GCLR for turning off the output of the gate driver 4 and signals DC31 to DC3 based on the value of the dot counter 1f.
6 is output. These signals control the operation within one horizontal period, and the timing chart is shown in FIG.

The signals DC31 and DC32 control the generation timing of the gate shift clock YCLK. That is, the signal DC31 generates one pulse in one horizontal period, and causes the gate driver 4 to select two consecutive gate lines 40. The signal DC32 is the signal DC32
In this example, five pulses are generated in one horizontal period, and the gate driver 4 skips four rows to select the next fifth gate line 40.

The signal DC33 is the source start signal SS
RT is output at a predetermined timing during one horizontal period. The signal DC34 outputs the switching signal HCNT at a predetermined timing during one horizontal period. The signal DC35 outputs the source clear signal SCLR at a predetermined timing during one horizontal period. Signal DC
Reference numeral 35 is for outputting the output enable signal SOE at a predetermined timing during one horizontal period.

The AND circuit 1k comprises a signal DC21 and a signal DC21.
The AND circuit 11 takes the logical product of the signal DC22 and the signal DC32. The OR circuit 1q is AND
The logical sum of the output signals of the circuits 1k and 1l is calculated and a gate shift clock YCLK is output. The gate shift clock YCLK is supplied to the gate driver 4 in the same field for three times.
After selecting the first gate line 40 in the horizontal period, 3
The gate line 40 of the next row in the horizontal period is selected, and
The gate line 40 is selected by skipping four lines from there for three horizontal periods.

The AND circuit 1m includes a signal DC23 and a signal DC23.
33, and outputs a source start signal SSRT. The source start signal SSRT is supplied to the source driver 4 as image signals D2 of two consecutive rows in the same field.
, And the image signals D2 of the next two rows are latched by skipping four rows. Also, the start signal SSRT
Switches input to a latch circuit in the source driver 5 described later.

The AND circuit 1n includes a signal DC24 and a signal DC24.
The logical AND of 35 is output and a source clear signal SCLR is output. The source clear signal SCLR is generated at a different timing for each field and clears the output from the source driver 5.

The AND circuit 1o comprises a signal DC24 and a signal DC24.
AND of 34. The output signal of the AND circuit 1o becomes the clock input of the toggle counter 1r, and the toggle counter 1r outputs the switching signal HCNT. Switching signal HC
NT is output at a different timing for each field,
In the same field, data is output every three horizontal periods. The switching signal HCNT switches an output from a latch circuit in the source driver 5 described later.

The AND circuit 1p includes a signal DC25 and a signal D25.
Logical AND of C36 and output enable signal S
Outputs OE. Output enable signal SOE
, The first output timing differs for each field. The output enable signal SOE causes the D / A converter 53 to output a signal.

The source control signal group CONTS described above
Are the source start signal SSRT and the switching signal HCN
T, an output enable signal SOE, a source clear signal SCLR, and a source clock SCLK.
The gate control signal group CONTG includes the gate start signal G
It comprises an SRT, a gate shift clock YCLK, and a gate clear signal GCLR.

The dot clock signal DOTCK is
It is output from the control unit 1 as the source clock signal SCLK as it is. The source clock signal SCLK shifts the bit of the shift register of the source driver 5 as described later.

Next, regarding the configuration of the source driver 5,
This will be described in detail with reference to FIG. As illustrated, the source driver 5 includes a shift register 51 and a latch circuit 5.
2a and 52b, a D / A (digital-analog) converter 53, a switch 54 for switching inputs to the latch circuits 52a and 52b, and a switch 55 for switching outputs from the latch circuits 52a and 52b.

The shift register 51 turns on the output of the first bit when the source start signal SSRT is input, and thereafter shifts the bit to be turned on each time the source clock signal SCLK is input.

The latch circuits 52 a and 52 b sequentially latch the image signal D 2 supplied from the inversion / level shift circuit 2 in accordance with the output of the shift register 51. Which of the latch circuits 52a and 52b latches the image signal D2 depends on the switch 54 being switched by the source start signal SSRT. That is, the image signal D2 of the odd-numbered row is latched by the latch circuit 52a, and the image signal D2 of the even-numbered row is latched by the latch circuit 52b.

The D / A converter 53 converts the image signal D2 latched by the latch circuits 52a and 52b into an analog signal in accordance with the output enable signal SOE, and applies a potential corresponding to the signal to the pixel electrode 66. It is. The output of the D / A converter 53 is cleared by the source clear signal SCLR. Note that the latch circuit 5
2a or 52b, the image signal D2 latched by D
The switch 55 switches the output to the / A converter 53 according to the switching signal HCNT.

Hereinafter, the operation of the liquid crystal display device according to this embodiment will be described. In this embodiment, a case where one frame is divided into three fields will be described. Also, the polarity of the signal to be written to the pixel is inverted in frame units. In this embodiment, frames in which signal polarities are opposite to each other are referred to as first and second frames, respectively.
The three fields in the first frame are referred to as first, second, and third fields, respectively, and the three fields in the second frame are referred to as fourth, fifth, and sixth fields, respectively.

In the video signal processing unit 0, the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC are converted from the video signal.
C is extracted. Also, the extracted vertical synchronizing signal VSYN
A dot clock signal DOTCK is generated in synchronization with C and the horizontal synchronization signal HSYNC. Further, the image signal in the video signal is sampled in synchronization with the dot clock signal DOTCK, and the image signal D1 is extracted.

The image signal D 1 sampled in the video signal processing section 0 is output to the inversion / level shift circuit 2. The vertical synchronizing signal VSYNC extracted by the video signal processing unit 0 is used as a clear signal as a line counter 1a.
Is supplied to the field counter 1b as a clock signal. The horizontal synchronization signal HSYNC is used as a clock signal for the line counter 1a, the control counters 1d, 1e.
Is supplied to the dot counter 1f as a clear signal. On the other hand, the dot clock signal DOTCK is supplied to the dot counter 1f as a clock signal.

The line counter 1a receives the horizontal synchronizing signal HS
It counts up each time YNC is input, and is cleared each time the vertical synchronization signal VSYNC is input. When the line counter 1a counts a predetermined value, the decoder 1
g outputs a gate start signal GSRT.

The field counter 1b counts up each time the vertical synchronization signal VSYNC is input. That is, 0 to 5 are output in accordance with the timing at which the image signals D1 of the first to sixth fields are extracted. The initial value stored in the start row setting ROM 1c according to the output of the field counter 1b is the horizontal synchronizing signal H
It is set to the control counter 1d at the timing when SYNC is supplied.

Here, in the first and fourth fields (outputs of the field counter 1b are 0 and 3), the control counter 1
d is set to -2. In the third and fifth fields (outputs of the field counter 1b are 1, 4), -4 is set in the control counter 1d. In the third and sixth fields (the output of the field counter 1b is 2, 5), -6 is set in the control counter 1d. Control counter 1d
Counts up each time the horizontal synchronization signal HSYNC is input, and when the value becomes 0, the control counter 1e
Clear The control counter 1e outputs the horizontal synchronization signal HS
It counts up every time YNC is input.

The output signal of the field counter 1b and the output signal of the control counter 1e are supplied to a decoder 1h, and the decoder 1h outputs a data polarity signal POLD and a common polarity signal POL based on these signals.
Generate C. Here, the data polarity signal POLD is supplied to the inversion / level shift circuit 2. The common polarity signal POLC is supplied to the common voltage generation circuit 3.

The output signals of the control counters 1d and 1e are respectively supplied to the decoder 1i. The decoder 1i outputs signals DC21, DC22, DC2 based on these signals.
3. Output DC24 and DC25.

On the other hand, the dot counter 1f counts up each time the dot clock signal DOTCK is input, and is cleared each time the horizontal synchronization signal HSYNC is input.

The output signal of the dot counter 1f is supplied to a decoder 1j. The decoder 1j outputs a gate clear signal GCLR and a signal DC31 based on this signal.
DC32, DC33, DC34, DC35, and DC36 are generated and output.

The output timings of the data polarity signal POLD and the common polarity signal POLC output from the decoder 1h and the signals DC21 to DC25 output from the decoder 1j differ for each field. Therefore, the driving of the liquid crystal panel 6 by the gate driver 4 and the source driver 5 differs for each field. Hereinafter, the driving of the liquid crystal panel 6 will be described for each field.

The first frame is composed of first, second and third fields. First, the driving of the liquid crystal panel 6 in the first field will be described with reference to FIGS.
This will be described with reference to FIG.

In the first field, 0 is output from the field counter 1b. At this time, the decoder 1h outputs the data polarity signal POLD and the common polarity signal POL depending on whether the value of the control counter 1e is odd or even.
Invert / non-invert C. That is, the inversion / level shift circuit 2 sets the image signal D2 of the odd-numbered row of the liquid crystal panel 6 to a positive polarity, and sets the image signal D2 of the even-numbered row to a negative polarity.
Control these signals.

The image signal D2 of the first row is supplied to the source driver 5
During the horizontal period input to the decoder 1i, the signal DC23 output from the decoder 1i is at a high level. Here, when the signal DC33 output from the decoder 1j rises, the source start signal SSRT is output to the shift register 51 and the switch 54. Thus, the output bits of the shift register 51 are sequentially shifted for each pulse of the source clock SCLK (dot clock signal DOTCK),
The image signal D2 (positive polarity) of the first row is latched by the latch circuit 52a.

The gate start signal GSRT is output from the decoder 1g when the image signal D2 supplied to the source driver 5 has finished the pixels in the first row of the liquid crystal panel 6. As a result, the gate driver 4 selects the first gate line.

At the output timing of the gate start signal GSRT, the signal DC21 becomes low level. The signal DC22 is at a low level from the timing of the vertical synchronization signal VSYNC. Therefore, the gate shift clock YCLK is not generated until one of the signals goes high next time. Therefore, the gate line of the first row is selected for the next three horizontal periods until the signal DC21 becomes high.

While the gate line 40 of the first row is selected, the signal DC25 is at the high level, and the output enable signal SOE is output. During this time, the image signal D2 latched by the latch circuit 52a is output. After being converted into an analog signal by the A / D converter 53, it is output to the source line 50. A potential corresponding to the image signal D2 output to the source line 50 is applied to the first row of pixel electrodes 66 via the TFT 67. That is, a positive-polarity image signal is written to the pixels in the first row.

On the other hand, the signal DC23 is also at the high level during the horizontal period in which the image signal D2 of the second row is being input. Here, when the signal DC33 rises, the source start signal SSRT is output to the shift register 51 and the switch 54. As a result, the mode is switched from the latch circuit 52a to the latch circuit 52b, and the image signal D2 (negative polarity) of the second row is sequentially latched by the latch circuit 52b.

After three horizontal periods when the writing of the image signals of the first row to the pixels is completed, the signal DC21 becomes high level during the horizontal period in which the image signals D2 of the fifth row are input to the source driver 5. Here, the gate clock signal YCLK is supplied to the one-pulse gate driver 4 by the signal DC31, and the selected row of the gate driver 4 becomes the second gate line. During the switching of the selected row, the gate clear signal GCLR is input to the gate driver 4, and the potential of the gate line 40 is set to the gate-off voltage of the TFT 67.

In this horizontal period, the signal DC24 is also at the high level. Thereby, the switching signal HCNT
Is output to the switch 55, and the image signal D2 of the second row latched by the latch circuit 52b is output. And
Similarly, the image signal D2 in the second row is also supplied to the D / A converter 5
The signal is D / A converted at 3 and output. That is, in the three horizontal periods, the image signals in the second row are written to the pixels in the second row with negative polarity.

The image signal D2 on the seventh row after the writing of the image signal on the second row has passed for two horizontal periods is applied to the source driver 4
, The signal DC23 goes high again. Here, when the source start signal SSRT is output, the switch 54 is switched, and the output bit of the shift register 51 is moved, so that the image signal D2 of the seventh row is latched in the latch circuit 52a.

The writing of the image signals in the second row to the pixels is completed, that is, the latching of the image signals in the seventh row is completed.
In a horizontal period in which the image signal D2 of the row is input to the source driver 5, the signal DC22 is at a high level. At this time, the gate shift clock YCLK is generated by the signal DC32.
Are supplied to the gate driver 4, and the selected row of the gate driver 4 becomes the seventh row. Also, during this horizontal period, the signal DC24 is also at the high level, and the switching signal HCNT is output at the timing when the signal DC34 is output. As a result, the image signal D2 of the seventh row latched by the latch circuit 52a is output.

Hereinafter, latch circuits 52a and 52
While sequentially switching the image signal D2 latched by b and the gate line 40 selected by the gate driver 4, the image signal is written to the pixel.

The operation of the first field will be briefly described with reference to FIG. In this figure, "1H"
Represents one horizontal period. As can be seen from the figure, the image signal D2 supplied to the source driver is 1, 2, 7, 8,.
• The source driver 5 takes in the line and every two lines every six lines into the source driver 5 and holds it.

The gate driver 4 includes 1, 2, 7,.
Eighth row and three horizontal period gate lines 40 are selected for every two rows every three rows. Then, in this selection period, the corresponding image signals are written to the pixels. At this time, since the captured image signal D2 has a positive polarity in the odd-numbered rows and a negative polarity in the even-numbered rows, the image signal to be written into the pixels also has a positive polarity in the odd-numbered rows and a negative polarity in the even-numbered rows.

Next, the driving of the liquid crystal panel 6 in the second field will be described with reference to FIGS. 3, 5, and 7. FIG. In the second field, the signal DC21 is at the high level for two horizontal periods after the output of the gate start signal GSRT, during which the gate shift clock YCLK is supplied to the gate driver 4 twice by the signal DC31. As a result, the gate driver 4 selects the third gate line 40.

By this time, the image signal D2 of the third row is latched in the latch circuit 52a. In the horizontal period in which the image signal D2 of the next fourth row is supplied to the source driver 5, the signal DC24 becomes high level, and the switching signal HCNT and the source clear signal SCLR are output. Further, the signal DC25 becomes high level, and the output enable signal SOE is output. As a result, the image signal D2 latched by the latch circuit 52a is output, and the corresponding image signal is written to the pixel. Second
In the field, the subsequent operation is the same as in the first field.

The operation in the second field will be briefly described with reference to FIG. In this figure, “1”
“H” represents one horizontal period. As can be seen, the image signal D2 supplied to the source driver is 3, 4, 9, 10
... The line is changed from the first field to the first field, and two lines are taken in the source driver 5 every six lines and stored.

The gate driver 4 has three, four, nine,
In the tenth row and the first field, the selected row is changed, and two horizontal rows are selected every three rows for three horizontal periods. Then, in this selection period, the corresponding image signals are written to the pixels. At this time, since the captured image signal D2 has a positive polarity in the odd-numbered rows and a negative polarity in the even-numbered rows, the image signal to be written into the pixels also has a positive polarity in the odd-numbered rows and a negative polarity in the even-numbered rows.

Next, the driving of the liquid crystal panel 6 in the third field will be described with reference to FIGS. 3, 6, and 7. FIG. In the third field, the signal DC21 is at the high level for four horizontal periods after the output of the gate start signal GSRT, during which the gate shift clock YCLK is supplied to the gate driver 4 four times by the signal DC31. As a result, the gate driver 4 selects the fifth gate line 40.

By this time, the image signal D2 of the fifth row is latched in the latch circuit 52a. In the horizontal period in which the image signal D2 of the next sixth row is supplied to the source driver 5, the signal DC24 becomes high level, and the switching signal HCNT and the source clear signal SCLR are output. Further, the signal DC25 becomes high level, and the output enable signal SOE is output. As a result, the image signal D2 latched by the latch circuit 52a is output, and the corresponding image signal is written to the pixel. Third
In the field, subsequent operations are the same as those in the first and second fields.

The operation of the third field will be briefly described with reference to FIG. In this figure, “1”
“H” represents one horizontal period. As can be seen, the image signal D2 supplied to the source driver is 5, 6, 11, 1
Line 2 and the first and second fields are changed.
Every two lines, two line sentences are fetched and stored in the source driver 5.

The gate driver 4 includes 5, 6, 1
.., And the first and second fields, the selected rows are changed, and two horizontal rows are selected every three rows for three horizontal periods. And during this selection period,
The corresponding image signals are written to the pixels. At this time, the captured image signal D2 has a positive polarity in the odd-numbered rows,
Since the even row has a negative polarity, the image signal written to the pixel also has a positive polarity in an odd row and a negative polarity in an even row.

In the second frame, the data polarity signal POL
D and the common polarity signal POLC are output after being inverted from those in the first frame. Therefore, the polarity of the image signal D2 output from the inversion / level shift circuit 2 and the polarity of the common potential VCOM output from the common voltage generation circuit 3 are opposite to those of the first frame. In other words, the polarity is opposite to the polarity of the signal written to each pixel of the liquid crystal panel 6, and the odd rows have a negative polarity, and the even rows have a positive polarity. For other operations, the first, fourth, fifth and sixth fields are respectively
Same as a few fields.

FIG. 12 shows the polarity of the voltage applied to each pixel of the liquid crystal panel by the above operation. In this figure, the vertical represents rows and the horizontal represents fields. In the figure, "1
“V” represents one vertical period. As can be seen from the figure, the number of positive polarity pixels and the number of negative polarity pixels are the same in any vertical period. Further, in any vertical period, up to two rows of pixels having the same polarity continue, and there are no more than three rows.

As described above, according to the liquid crystal display device of this embodiment, there is no variation in the ratio between the number of positive polarity pixels and the number of negative polarity pixels. In addition, there is no variation in the positional distribution of the positive polarity pixels and the negative polarity pixels. Therefore, the spatial frequency of the liquid crystal panel can be increased, and the occurrence of flicker can be suppressed.

Further, since a sufficient time can be taken for writing signals to each pixel, it is possible to drive a liquid crystal panel using a liquid crystal having spontaneous polarization such as a ferroelectric liquid crystal or an antiferroelectric liquid crystal. It is particularly suitable.

In the above-described embodiment, an example has been described in which one frame is constituted by three fields by thinning out image data by one third. However, the present invention is not limited to this. The present invention can be applied to all cases where one frame is composed of an arbitrary number N of two or more fields. In this case, the image data may be thinned out by a factor of N and used.

In the above embodiment, the gate driver 4
Has selected two consecutive gate lines in each frame, skipped an even number of consecutive gate lines, and selected the next two consecutive gate lines. That is, two consecutive rows are selected every six rows in each frame. However, the present invention is not limited to this.

The present invention selects an arbitrary even-numbered gate line in each frame, skips a multiple of the number of the selected selected gate lines, and then selects another arbitrary even-numbered gate line. It can be applied to the case. In other words, the present invention provides two consecutive 2m (n + 1) rows.
It can be applied to the case where m rows are selected (m, n: natural numbers).

In this case, the source driver 5 may have a configuration capable of latching image signals for 2 m lines. Also,
The polarity of the signal to be written to the pixels in the selected 2m rows may be alternately reversed (for example, positive, negative, positive, negative...) For each row.

In the above embodiment, the inversion / level shift circuit 2 inverts the polarity of the image signal in line units and frame units. That is, the polarities of the image signals in the same row were the same. However, the polarity of the image signal may be further reversed for each pixel. In this case, of two consecutive rows selected in the same field, if the polarity of the image signal in the odd-numbered row is “+ − + − +...”, The polarity of the image signal in the even-numbered row is “ -+-+ -... "
The polarity may be reversed for each row.

When the polarity is inverted on a pixel-by-pixel basis in this manner, in the next frame, the polarity of the image signal in the odd-numbered row is set to “− + − + −. The polarity of the signal may be “+ − + − +...” And the polarity may be reversed for each frame. As a result, the positional distribution of the positive polarity pixels and the negative polarity pixels does not fluctuate, and the occurrence of flicker can be further suppressed.

In the above embodiment, the polarity of the image signal D1 extracted from the video signal by the video signal processing unit 0 is inverted by the inversion / level shift circuit 2 line by line or frame by frame. However, if the source driver 5 is provided with a means for inverting the polarity of the image data to be written to each pixel, the source driver 5 does not
May be supplied.

In the above embodiment, the source driver 5
Used a digital source driver. However, the present invention can also be applied to a liquid crystal display device using an analog source driver.

In the above embodiment, an example in which a liquid crystal panel in which a liquid crystal having spontaneous polarization such as a ferroelectric liquid crystal or an antiferroelectric liquid crystal is sealed between a pair of transparent substrates has been described. However, the present invention can also be applied to a device using a liquid crystal panel in which a nematic liquid crystal having no spontaneous polarization is sealed between a pair of substrates.

In the above embodiment, the liquid crystal panel 6
Polarizing plates 7 are provided outside the pair of transparent substrates 61 and 62, respectively.
1, 72. In addition, the backlight system controls the amount of light transmitted from the backlight. However, the liquid crystal panel used in the present invention may not include one or both of the polarizing plates, and may be a reflection type including a reflecting plate instead of a backlight.

In the above embodiment, an active matrix type liquid crystal display device using a TFT as an active element has been described, but the present invention is not limited to this. For example, the present invention can be applied to an active matrix type liquid crystal display device using another active element such as MIM (Metal Insulator Metal).

[0095]

As described above, according to the present invention,
Since there is no bias in the ratio of the number of pixels of positive polarity to the number of pixels of negative polarity and in the positional distribution, generation of flicker can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a configuration of a liquid crystal panel in the liquid crystal display device of FIG.

FIG. 3 is a block diagram illustrating a configuration of a control unit in the liquid crystal display device of FIG.

FIG. 4 is a timing chart of signals for controlling operation within one vertical period (first and fourth fields) output from the decoder according to the embodiment of the present invention.

FIG. 5 is a timing chart of signals for controlling operation within one vertical period (second and fifth fields) output from the decoder according to the embodiment of the present invention.

FIG. 6 is a timing chart of signals for controlling the operation within one vertical period (third and sixth fields) output from the decoder according to the embodiment of the present invention.

FIG. 7 is a timing chart of a signal for controlling operation within one horizontal period output from the decoder according to the embodiment of the present invention.

8 is a block diagram illustrating a configuration of a source driver in the liquid crystal display device of FIG.

FIG. 9 is a timing chart illustrating a driving operation of the liquid crystal panel in the first and fourth fields according to the embodiment of the present invention.

FIG. 10 is a timing chart illustrating a driving operation of the liquid crystal panels in the second and fifth fields according to the embodiment of the present invention.

FIG. 11 is a timing chart illustrating a driving operation of a liquid crystal panel in third and sixth fields according to the embodiment of the present invention.

FIG. 12 is a diagram illustrating the polarity of a voltage applied to a liquid crystal according to an embodiment of the present invention.

FIG. 13 is a diagram for explaining the polarity of a voltage applied to liquid crystal in a conventional example.

FIG. 14 is a diagram for explaining the polarity of a voltage applied to a liquid crystal in a conventional example.

[Explanation of symbols]

0: video signal processing unit, 1: control unit, 2: inversion / level shift circuit, 3: common voltage generation circuit, 4: gate driver, 5: source driver, 6 ... Liquid crystal panels,
1a: line counter, 1b: field counter,
1c: start row setting ROM, 1d, 1e: control counter, 1f: dot counter, 1g to 1j: decoder,
1k-1p ... AND circuit, 1q ... OR circuit, 1r ...
Toggle counter, 51... Shift register, 52a, 5
2b: Latch circuit, 53: D / A converter, 61, 62
... Transparent substrate, 63 ... Liquid crystal, 65 ... Common electrode, 66 ...
Pixel electrode, 67 ... Thin film transistor (TFT)

Claims (4)

[Claims] 1. An active matrix type liquid crystal panel in which pixels are arranged in a matrix, and 2m (n + 1) of the matrix in each field.
Continuously select 2m rows every other row, change the selected row for each field, and change
A selection driving unit for selecting all the rows in the frame; an image signal held for every 2 m (n + 1) rows for 2 m rows; and a signal corresponding to the held 2 m row image signal is selected by the selection driving unit. A signal driving means for alternately writing the pixels of 2 m rows with opposite polarities for each row, wherein m and n are natural numbers. 2. The method according to claim 1, wherein the selection driving means includes means for sequentially selecting each of the continuous 2m rows at a time of (n + 1) times of one horizontal period. 2. The liquid crystal display device according to claim 1, further comprising: means for sequentially writing signals corresponding to the image signals of (a) to (c) in a row selected by the selection driving means. 3. The liquid crystal display device according to claim 1, wherein said signal driving means further comprises means for inverting the polarity of a signal to be written to said pixel for each frame. 4. The liquid crystal panel according to claim 1, wherein a liquid crystal having spontaneous polarization is sealed between a pair of substrates disposed opposite to each other. The liquid crystal display device as described in the above.