JPH10270601A - Semiconductor device - Google Patents

Abstract

(57) [Problem] In a conventional semiconductor device, wire bonding is performed outside a chip, so that an outer shape becomes larger, a resin thickness becomes thicker, and an external terminal is further deformed with respect to a chip size. There was fear. A carrier having bumps formed on an upper surface of a chip is fixed with an adhesive. The bump 5 exposes an end face that is not directly connected to the metal wiring pattern on the upper surface of the carrier 2 so as to be used as an external electrode. The pads on the upper surface of the chip 1 and the pads on the upper surface of the carrier 2 are electrically connected by short and low loop-shaped wires 4. The upper surface of the chip 1 and other parts have a structure covered with the sealing resin 6. With the above structure, the mounting area can be reduced to the chip size, and the size can be reduced. Since electrical connection is achieved by short and low loop-shaped wires arranged in the chip area, the thickness can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a chip having an area approximately equal to the area of a package, a carrier portion approximately equal to the area of the chip, a pad on the upper surface of the carrier and a pad on the upper surface of the chip within the chip area. Short, low loop-shaped wire, electrical connection, carrier electrically connected by wire, and carrier excluding bumps, excluding the carrier top and carrier stuck. The present invention relates to a semiconductor device having a single-sided mold in which a chip upper surface is covered with a sealing resin and a chip lower surface is exposed.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view of a conventional semiconductor device. FIG. 4 is a perspective view of a conventional semiconductor device. In the figure, 1 is a chip, 7 is a die pad, 3 is an adhesive, 4 is a wire, 8 is a lead, and 6 is a sealing resin.

In a conventional semiconductor device, as shown in FIGS. 3 and 4, a chip 1 is connected on a die pad 7 with an adhesive 3. One end of the lead 8 is electrically connected to the chip 1 by the wire 4. The other end of the lead 8 is processed into a gull wing shape.

As described above, the conventional semiconductor device includes a chip 1
Die pad 7 connected to chip 1 with adhesive 3
The wire 4 and one end of the lead 8 electrically connected to the chip 1 by the wire 4 are completely covered with the sealing resin 6.

[0005]

However, in the above-mentioned conventional semiconductor device, wire bonding is performed outside the chip, so that the outer shape and the resin thickness are increased with respect to the chip size, and the external terminals are further increased. There was a problem that there was a risk of deformation.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. A chip having the same area as the package, a carrier having the same area as the chip, a pad on the upper surface of the carrier and a pad on the upper surface of the chip are provided. The part that is electrically connected by the short and low loop-shaped wire placed in the chip area, the part that is electrically connected by the carrier part and the wire, and the top part of the carrier and the carrier excluding the bump part Covering the exposed chip upper surface excluding the stuck part with sealing resin and having a single-sided mold structure exposing the chip lower surface, it can be made thinner, smaller, and prevent deformation of external terminals. It is an object of the present invention to provide a semiconductor device which is easy to assemble and can be assembled.

[0007]

In order to achieve this object, a semiconductor device according to the present invention comprises a chip having an area approximately equal to the area of a package, a metal wiring pattern having pads and external electrodes connected on a silicon wafer. A chip having a carrier area substantially equal to the area of the chip and an area approximately equal to the area of the package having bumps formed on the upper surface thereof, and a pad on the upper surface of the carrier and a pad on the upper surface of the chip which are arranged within the chip area in a short and Exposed chip except for the part that is electrically connected by the low loop-shaped wire, the part that is electrically connected to the carrier part and the wire, the upper part of the carrier excluding the bump part, and the part where the carrier is stuck. It has a single-sided mold that exposes the lower surface of the chip for the purpose of covering the upper surface with a sealing resin.

By adopting the above-mentioned means, a thinner and smaller external terminal can be prevented from being deformed as compared with a conventional semiconductor device, and a semiconductor device which can be assembled by applying an existing technology can be easily provided.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to this embodiment.
FIG. 2 is a perspective view of the semiconductor device of the present embodiment.

1 and 2, in a semiconductor device according to the present embodiment, a carrier 2 on which a bump 5 is formed is fixed to an upper surface of a chip 1 with an adhesive 3. In order to use the bump 5 as an external electrode, an end face which is not directly connected to the metal wiring pattern on the upper surface of the carrier 2 is exposed, and is formed by a tape carrier package bump forming technique. The pad on the upper surface of the chip 1 and the carrier 2
The top pad is a short, low loop wire 4
Is electrically connected. The carrier 2 has a metal wiring pattern formed by connecting pads and external electrodes on a silicon wafer. The adhesive 3 is an insulative one and adheres to the entire surface or points. The chip 1
The upper surface portion, the upper surface portion of the carrier 2, the pads on the upper surface of the chip 1 electrically connected by the wires 4, the pad portions on the upper surface of the carrier 2, and the bumps 5 are covered with a sealing resin 6. It has a structure that is

The above description and figures make the advantages associated with this embodiment evident. Specifically, it has been clarified that the outer shape of the chip can be reduced without increasing the outer shape, and the thickness of the resin can be reduced without increasing the thickness. Therefore,
Obviously, there is provided a semiconductor device according to this embodiment that fully satisfies the advantages described above.

Although the present embodiment has been described with reference to specific examples, it is not intended that the present embodiment be limited to these specific examples. Therefore, this embodiment is intended to cover all variations and modifications that fall within the scope of the invention.

[0014]

As described above, by using the semiconductor device according to the present invention, the mounting area can be reduced to the chip size and the size can be reduced. In order to make electrical connection with short and low loop-shaped wires arranged within the chip area,
Can be made thinner.

Further, since there is no deformable external terminal, deformation of the external terminal can be prevented. Further, the assembly can be performed by applying the existing technology, and there is no need to add a new process.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a perspective view of a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

FIG. 4 is a perspective view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Chip 2 Carrier 3 Adhesive 4 Wire 5 Bump 6 Sealing resin 7 Die pad 8 Lead

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 23/12 F

Claims (1)

[Claims] A chip having an area approximately equal to the area of a package; a carrier portion having an area approximately equal to the area of the chip formed on a silicon wafer by forming a metal wiring pattern and a bump connected to pads and external electrodes on an upper surface thereof; A portion where the pad on the upper surface of the carrier and the pad on the upper surface of the chip are electrically connected by a short and low loop-shaped wire disposed in the chip area, and an electrical connection is established by the wire and the carrier portion. Having a single-sided mold structure in which the upper surface of the carrier excluding the bump portion and the upper surface of the chip excluding the portion where the carrier is stuck are covered with a sealing resin, and the lower surface of the chip is exposed. A semiconductor device characterized by the following.